Impact of Process Variation on Input-Referred Offset in Current Mode Sense Amplifiers Meenakshi Sekhar, Riya Shergill ECE 632 – Fall 2007 University of Virginia <ms3aw>, <rs5ax>@virginia.edu ABSTRACT Sense amplifiers have an inherent offset that determines the minimum bitline differential at which the outputs can be read correctly. This paper seeks to evaluate the offset current for three topologies of current sense amplifiers and study the impact of process variation on the input referred current offset. 1. INTRODUCTION In most SRAMs, the nodes of the bit cell are connected to bit lines that are pre-charged before the read phase. When a read operation is performed a current is drawn into the bit cell which causes the bit line capacitance to discharge .In large memory arrays, the bit line capacitance is very large and hence the time taken to discharge the capacitors slows down the read process. Sense amplifiers are differential amplifiers that amplify the bitline differential to give complimentary outputs. There are two categories of sense amplifiers: - Voltage and Current sense amplifiers. Voltage sense amplifiers have been used extensively in the past. But in advanced memories, a voltage sense amplifier can result in slow read operation because of the large capacitance involved. A current sense amplifier is also a differential amplifier. Unlike voltage differential amplifiers, these amplifiers have low input impedance and high output impedance. This low input impedance causes a considerable differential in the input current to the sense amplifier even when the bit line voltage differential is very small. By sensing the difference in current and translating it into an amplified voltage difference, a bit cell can be read faster than a voltage sense amplifier. M1 M2 M3 M4 Fig 2 shows a Cascode current mode sense amplifier [1]. This circuit has increased output impedance compared to conventional current mode sense amplifier. Increased output impedance reduces the mismatch between the drain to source voltages in the mirror circuit. In this paper, we are studying the impact of threshold variation on the input referred offset current. Due to inherent variations in transistors, there exists an offset between the bit lines. This offset can result in faulty reads. So, Input Offset current is the inherent difference in current on bit lines that exists even when the sense amplifier is not enabled. 2. TOPOLOGIES The sense amplifier operates in two phases: pre-charge and evaluate. In the pre-charge phase, bit lines are charged to VDD. And in evaluate phase, the currents are sensed and the bit cell is read. Fig 1 shows a conventional current mode sense amplifier [1]. The architecture of this sense amplifier includes two current mirror circuits. In each current mirror circuit, the gate voltages are made equal and the transistors are allowed to operate in saturation. The saturation current depends on the gate to source voltage. Since the gate to source voltages for M1, M2 and M3, M4 pairs are the same, the currents on the bit lines are also equal as a result of which the outputs are complementary. Figure 3 shows an improved Wilson Sense Amplifier. It uses negative feedback. When there is a variation in the input current, the reference current source tries to equalize the current in the complimentary bit line. most probable offset of the sense amplifier is around (1uA) and the standard deviation is 1.58uA. The average offset current for the circuit is 1.06uA. For Cascode sense amplifier in Fig 5, the most probable offset of the sense amplifier is around 300nA and the standard deviation is 252nA. The average of the distribution is 358nA. For the Improved Wilson sense amplifier in Fig 6, the most probable offset of the sense amplifier is around 100nA and the standard deviation is 202nA. The average of the distribution is 31nA. Cascode Sense Amplifier # of occurences 35 The circuits mentioned above have been simulated using Cadence 2005. We used PTM 90nm technology for all the circuits. The NFET threshold voltage used was 0.397V and the PFET threshold voltage used was 0.339V.The NMOS transistors in the current mirror circuit were of equal size, W/L=180nm/90nm. Conventional Current Sense Amplifier 20 Series1 15 10 5 10 00 80 0 60 0 40 0 20 0 0 -4 00 0 Input Offset Current (nA) Fig.5. Input Offset Current distribution of Cascode Sense Amplifier Improved Wilson Sense Amplifier 30 25 20 # of occurences For the scope of this project, the current source at one bit line was kept constant and the current source at the complimentary bit line was swept over a range of values. This range varied for each sense amplifier. This experiment was performed for multiple threshold voltages using Monte Carlo simulations. For every sense amplifier a minimum differential between bit lines is required to correctly sense the bit lines. Due to the input referred offset, correct read operation may not be performed at the expected bit line differential. For each Monte Carlo iteration, the output value flips at a particular bit line differential revealing the minimum bit line current differential required to perform a correct read operation. This is the input referred offset current. 25 -2 00 3. SIMULATION RESULTS 3.1 Input Offset Current distribution 30 15 Series1 10 35 5 30 # of occurences 80 0 70 0 60 0 50 0 40 0 30 0 20 0 0 10 0 -8 00 -7 00 -6 00 -5 00 -4 00 -3 00 -2 00 -1 00 0 25 Input-Offset (nA) Series1 20 Fig.6. Input Offset Current distribution of Improved Wilson Sense Amplifier 15 10 3.2 Input Offset Current variation with threshold voltage 5 0 -5 -4 -3 -2 -1 0 1 2 3 4 5 Input-Offset Current (uA) Fig.4. Input Offset Current distribution of a Conventional Sense Amplifier Fig 4 shows simulation results of 100 Monte Carlo runs on a conventional sense amplifier. The histogram indicates that the Fig.7, 8 and 9 show the Input Offset Current variation with threshold voltages for a conventional current sense amplifier, cascade current sense amplifier and improved Wilson Current Sense amplifier respectively. In Cadence, the tool Monte Carlo varies threshold voltage of all the transistors equally for each run. 4. CONCLUSIONS For a Gaussian distribution of the threshold voltage, the offset current also varies as a Gaussian distribution. Lower values of threshold voltage could imply a larger offset current. Future work could involve evaluation of the offset current by varying the threshold voltage of the transistors individually and determining the transistors that may have the maximum impact on offset. 3.5 3 2.5 2 1.5 1 0.5 5. ACKNOWLEDGMENTS 0 0.3 0.33 0.34 0.35 0.35 0.36 0.37 0.38 0.38 0.38 0.39 0.39 0.39 0.4 0.4 0.41 0.41 0.41 0.42 0.42 0.43 0.45 0.45 0.46 0.5 Input Offs et C urrent (uA) Conventional Sense Amplifier T hre shold V ola tg e (V ) offs et Fig.7. Variation of Input Offset Current with respect to threshold voltage 1200 800 600 Offs et 400 200 0 [1] “Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM’s” by Evert Seevinck, Petrus J. van Beers, and Hans Ontrop Fig.8. Variation of Input Offset Current with respect to threshold voltage 0.29 0.34 0.37 0.37 0.38 0.38 0.39 0.4 0.4 0.4 0.41 0.41 0.41 0.42 0.42 0.43 0.43 0.44 0.46 [4] “Current Sense Amplifiers for Embedded SRAM in HighPerformance System-on-a-Chip Designs” by B.Wicht [6] “Techniques To Reduce Power In Fast Wide Memories” by Bharadwaj S. Amrutur and Mark Horowitz [7] “Comparative study of different current mode sense amplifiers in sub-micron CMOS technology” by A. Chrisanthopoulos, Y. Moisiadis, Y. Tsiatouhas and A. Arapoyanni Improved Wilson Sense Amplifier 500 400 300 200 100 0 -100 -200 -300 -400 -500 [3] “A High-Speed Clamped Bit-Line Current-Mode Sense Amplifier” by Travis N. Blalock, and Richard C. Jaeger [5] “Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nanoscale SRAM” by Saibal Mukhopadhyay, Arjit Raychowdhury, Hamid Mahmoodi, and Kaushik Roy T hre shold Volta g e (V) Input Offs et C urrent (nA) 6. REFERENCES [2] “Current Mode Sense Amplifier” by Shahab Ardalan, Doris Chen, Manoj Sachdev, and Andrew Kennings 1000 0.3 0.34 0.35 0.36 0.37 0.38 0.39 0.4 0.41 0.41 0.42 0.42 0.43 0.44 0.45 0.46 0.49 Input Offs et C urrent (nA) Cascode Sense Amplifier The authors wish to thank Prof. Benton Calhoun for his encouragement and guidance and Joseph F. Ryan, Jiajing Wang and Satyanand Vijay Nalam for their help. offs et T hre shold Volta g e (V) Fig.9. Variation of Input Offset Current with respect to threshold voltage We observed that the Input Offset Current varies with threshold voltage. For lower values of threshold voltage the offset current is higher and fluctuates over a wider range. [8] “A 6-ns 4-Mb CMOS SRAM with Offset-VoltageInsensitive Current Sense Amplifiers” by Koichiro ISHIBASHI, Kiyotsugu UEDA, Koichi TAKASUGI, Kunihiro KOMIYAJI,*Hiroshi TOYOSHMA, Toshiaki YAMANAKA, Akira FUKAMI, **Naotaka HASHIMOTO,"Nagatoshi OOKI, 'Akihiro SHIMIZU, Takashi HASHIMOTO, Takahiro NAGANO and Takashi NISHIDA [9] A 9-ns 16-Mb CMOS SRAM with Offset-Compensated Current Sense Amplifier Katsunori Seno, Kurt Knorpp, LeeLean Shu, Naoki Teshima, Hiroki Kihara, Hiroshi Sato, Fumio Miyaji, Minoru Takeda, Masayoshi Sasaki, Yoichi Tomo, Patrick T. Chuang, Member, IEEE, and Kazuyoshi Kobayash