International Journal of Electrical, Electronics and Computer Systems (IJEECS)
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Design of Carry Look-Ahead Adder Using Reversible Logic Gates
Girija S, Raghavendra G R, Manjushree B R, Nirmalraj R, Prakruthi U S
Asst. Professor ECE Dept, ECE Student
Dr. AIT
Email: sb_girija@yahoo.com, raghugr92@gmail.com, manjushree978@gmail.com, nirmalraj.rko@gmail.com,
prakrutiangel@gmail.com
Abstract---Reversible logic is a popular concept in energy
efficient computations and this will be the demand for
upcoming future computing technologies. Reversible logic
is emerging as an important research area and it will be
having wide applications in many fields such as optical
information processing, quantum computing and Low
power CMOS design. The main purpose of designing
reversible logic is to decrease quantum cost, depth of the
circuits and the number of garbage outputs. A Fault
tolerant reversible logic has gained importance as they
consume low power and less heat dissipation. The benefits
of logical reversibility can be gained only after employing
physical reversibility. Every future technology will have to
use reversible gates in order to reduce power. Under ideal
conditions, the reversible logic gates will produce zero
power dissipation. So this concept will be helpful for Low
power VLSI design. This paper proposes the design of
Look Ahead Carry Adder using fault tolerant reversible
gates. The proposed design offers less power dissipation
including the fault tolerant concept. The proposed circuits
are simulated using the Cadence tool.
Index terms---Reversible logic, power dissipation, carry
look-ahead adder, fault tolerant, garbage output
I. INTRODUCTION
Today’s new technology offers faster, smaller and
complex circuits. Moore’s law states that Performance
(speed) of an integrated circuit per unit cost increases by
a factor two for every 18 months. In order to achieve
higher speed the clock frequency must be high and for
smaller, complex circuit’s the number of transistors in
the IC must be large and they are more closely packed in
order to save area. As the IC will be faster, complex
means that will increase the power dissipation in the
circuit. Almost all conventional computers comprise of
million numbers of gates that are irreversible in nature.
During logical operations in the circuit some
information is erased or lost that will causes heatdissipation and energy loss.
operation is performed [1]. At a temperature T, for one
bit loss it will generate 2.86 X 10-21 J of energy that
will be small but we cannot neglect this value. The heat
dissipated in the circuit will gradually decrease the
performance and also life span of the circuit or device.
In order to overcome these types of problems, we
require low power consumption and less dissipation
components in the circuit. C H Bennet shown that if we
use reversible logic gates instead of irreversible
components in the circuit, we can achieve zero energy
dissipation in the circuit[2].
He proposed two conditions of reversibility.
1stcondition: For any device to be reversible if its input
and output will be uniquely retrievable from each other
called logical reversibility.
2ndcondition: A device can run actually backwards then
it is called physically reversible.
The reversible circuits are those in which reversible
logic gates are basic building blocks and there is no
energy loss. The reversible logic gates will be having ninput and n-output i.e. equal number of input and equal
number of output, and also with one-to-one mapping i.e.
inputs can be uniquely recovered from the outputs.
Reversible logic supports the process of running the
system both forward and backward. This means that we
can stop and go back to any point in the computation
history. Adder is widely used in the generic computer
because it is very important for adding data in the
processor. The simplest binary adder is ripple carry
adder. It is easy to be understood and implemented. A
more complex binary adder is carry look-ahead adder.
The speed of execution is the most important factor that
needs to be considered for appraising the quality of an
adder. Look ahead carry adder is widely used because of
its superior performance over ripple carry adder.
II. REVERSIBLE LOGIC
R Landauerhas shown that circuit with
irreversible
The reversible logic gate will generate unique output
components, during computation each bit loss generates
vector from unique input vector or vice-versa [3].In
kTln2
joules
of
energy,
where
reversible logic, Input vector is Iv=( Ii,j , Ii+1,j , Ii+2,j ,
K=1.3806505*1023m2kg2K1(joule/Kelvin-1)
is
the
…, Ik-1,j, Ik,j ) and Output vector is Ov=( Oi,j , Oi+1,j ,
Boltzmann's constant and T is the temperature at which
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ISSN (Online): 2347-2820, Volume -2, Issue-4, 2014
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International Journal of Electrical, Electronics and Computer Systems (IJEECS)
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Oi+2,j ,…, Ok-1,j, Ok,j ), For each particular vector j Iv
↔ Ov.
fault tolerant gate (NFT), 4*4 Modified IG gate are
discussed in the literature.
Fig. 1 shows a general reversible gate; the gate will be
having k inputs and k outputs and it is called ak*k
reversible gate. In reversible gates, fan-out are not
permitted. No feedback paths are allowed i.e. circuit is
acyclic. Some important factors are Garbage output,
constant input etc. Garbage output is the un-utilized
output from the reversible gate, very much essential to
achieve reversibility and it must be not used for further
computation. Constant inputs are those that will be
added to k*k function to make it reversible. For an
optimized reversible circuit, the number of garbage
outputs, the number of constant inputs and the number
of reversible gates used should be minimum.
A. Feynman Double Gate(F2G)
Feynman Double gate is a 3*3 one through reversible
gate as shown in Fig. 2. The input vector is I(A, B, C)
and the output vector is O(P, Q, R). The outputs are
defined by P=A, Q=A^B, R=A^C. Quantum cost of a
Feynman Double gate is 2.
Fig. 2. 3*3 Feynman Double gate.
TABLE I. TRUTH TABLE OF PARITY
PRESERVING FEYNMAN DOUBLE GATE
Fig. 1. General Reversible Gate
In the design of reversible logic circuits the following
points must be considered to achieve an optimized
circuit.
They are:

Fan-out is not allowed.

Loop or feedback is not permitted.

Garbage outputs should beminimum.

Minimum delay.

Minimum quantum cost.
Input
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Output
P
Q
0
0
0
0
0
1
0
1
1
1
1
1
1
0
1
0
R
0
1
0
1
1
0
1
0
B. Fredkin Gate (FRG)
Fig. 3 shows a 3*3 Fredkin gate[8]. The input vector is
I(A, B, C) and the output vector is O(P, Q, R). The
output is defined by P=A, Q=A'B ^ AC and R=A'C ^
AB. The Quantum cost of a Fredkin gate is 5.
III. PARITY PRESERVING REVERSIBLE
GATES
Fault tolerance is the property that enables a system to
continue operating properly in the event of the failure of
some its components. If the system itself made of fault
tolerant components, then the detection and correction
of faults become easier and simple. In communication
and many other systems fault tolerance is achieved by
parity. Therefore, parity preserving reversible circuits
will be the future design trends to the development of
fault tolerant reversible systems in nanotechnology. A
gating network will be parity preserving if its individual
gates are parity- preserving[5]. Thus, we need parity
preserving reversible logic gates to construct parity
preserving reversible circuits [3][4]. Parity checking is
one of the oldest, as well as one of the most widely used,
methods for error detection in digital systems.
Fig. 3. 3*3 Fredkin gate.
TABLE II. TRUTH TABLE OF PARITY
PRESERVING FREDKIN GATE
A
0
0
0
0
1
Input
B
0
0
1
1
0
C
0
1
0
1
0
P
0
0
0
0
1
Output
Q
0
0
1
1
0
R
0
1
0
1
0
A few parity preserving logic gates like3*3 Feynman
Double gate (F2G), 3*3 Fred kin gate (FRG), 3*3 New
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International Journal of Electrical, Electronics and Computer Systems (IJEECS)
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1
1
0
1
1
1
0
1
1
1
1
1
0
1
0
1
1
C. Novel Fault Tolerant Gate (NFT)
The NFT gate is a 3*3 Reversible gate with three inputs
and three outputs[8]. The input vector is I(A, B, C) and
the output vector is O(P, Q, R). The output is defined by
P=A^B, Q=BC’^ AC’, R=BC ^ AC’ and is shown in the
Fig. 4.The Quantum cost of a NFT gate is 5.
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
The power consumed by the above mentioned reversible
gates based on Cadence encounter® RTL compiler is
given in Table V.
Gate
Leakage
Dynamic
Total
power
power
power
(nW)
(nW)
(nW)
F2G
10.377
202.276
212.653
MIG
15.821
356.999
372.820
Fig. 4. 3*3 NFT gate.
TABLE III. TRUTH TABLE OF PARITY
PRESERVING NFT GATE
Inout
Output
A
B
C
P
Q
R
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
1
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
0
1
Table V.
IV. FULL ADDER
A Full Adder is a combinational circuit that performs the
arithmetic sum of three input bits. It consists of three
inputs and two outputs. Three of the input variables can
be defined as A, B, Cin and the two output variables can
be defined as ‘S’ for sum and ‘Cout’ for carry. The
output equations of full adder are as below:
D. Modified IG Gate (MIG)
S=A
The MIG gate is a 4*4 Reversible gate with four inputs
and four outputs[8]. The input vector is I(A, B, C, D)
and the output vector is O(P, Q, R, S). The output is
defined by P=A, Q=A^B, R=AB ^ C, S=AB’ ^ D and is
shown in the Fig. 5. The Quantum cost of a MIG gate is
7.
Cout = AB Cin(B A)
B
Cin
Ripple Carry Adder (RCA): The most straight forward
realization of a final stage adder for two n-bit operands
is ripple carry adder. The RCA requires n full adders
(FAs). The carry-outof the ith FA is connected to the
carry-in of the (i+1)th FA.
Carry Skip Adder (CSA): A carry-skip adder reduces the
carry-propagation time by skipping over groups of
consecutive adder stages.
Fig. 5. 4*4 MIG gate.
TABLE
IV.TRUTH
TABLE
PRESERVING MIG GATE
Input
A
B
0
0
C
0
D
0
Output
P
Q
0
0
OF
PARITY
Carry Look-Ahead Adder (CLA): The main idea behind
carry look-ahead addition is an attempt to generate all
incoming carries in parallel and avoid waiting until the
correct carry propagates from the stage (FA) of the
adder where it has been generated.
A Proposal for a 4-bit Fault Tolerant Reversible CLA
Adder: This paper proposes a high speed and low power
consumption fault tolerant 4-bit carry look ahead adder.
R
0
S
0
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International Journal of Electrical, Electronics and Computer Systems (IJEECS)
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V. DESIGN OF FAULT TOLERANT
CARRY LOOK-AHEAD ADDER
Carry look-ahead adder (CLA) is the fastest of all adders
and achieve speed through parallel carry computations.
For each bit in a binary sequence to be added, the CLA
logic determines whether that bit pair will generate a
carry or propagate a carry. This allows the circuit to preprocess the two numbers being added to determine the
carry ahead of time. Then, when the actual addition is
performed, there is no delay from waiting for the ripple
carry effect. Carry look-ahead adder actually skips this
dependency among carry bits by two modules, namely,
carry generation (Gi) and carry propagation (Pi) where,
Gi = Ai . Bi
Pi = Ai Bi
Fig. 7. Proposed 2-bit Fault Tolerant CLA circuit
Si = Pi Ci
VI. PERFORMANCE ANALYSIS
Cout = Ci+1 = Gi Pi . Ci
The Truth table of 2-bit fault tolerant carry look-ahead
adder is shown in Table VI.
Table VI. TRUTH TABLE OF 2-BIT IRREVERSIBLE
CLA
a1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
a0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Input
b1
b0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
cin
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
s1
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
Output
s0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
cout
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
In this section, we analyze the performance of the
proposed reversible fault-tolerant carry look-ahead adder
with the existing irreversible carry look-ahead adder.
Table VII shows the results of the proposed Reversible
fault tolerant reversible 2-bit and 4-bit CLA circuits.
Table VIII shows the performance analysis between the
proposed and the existing carry look-ahead adder
circuits.
TABLE VII. RESULTS OF THE PROPOSED
REVERSIBLE FAULT TOLERANT REVERSIBLE 2BIT AND 4-BIT CLA CIRCUITS
Methods
2-bit
4-bit
Quantum
Cost
43
122
Gate
count
9
26
Garbage
outputs
11
29
Constant
I/P’s
9
25
TABLE VIII. PERFORMANCE ANALYSIS
BETWEEN THE PROPOSED REVERSIBLE FAULT
TOLERANT AND THE EXISTING IRREVERSIBLE
2-BIT AND 4-BIT CLA CIRCUITS.
Performance
Improvement(%)
2-bit
4-bit
Power
Consumption
29%
32%
Area
5%
30%
The comparative results show that the proposed
reversible fault-tolerant carry look-ahead adder
performance is much better than the irreversible circuit
in terms of numbers of gates, power consumption and
area. The proposed design of a reversible fault tolerant
carrylook-ahead adder is functionally verified through
simulations using Cadence Tool on a computer. The
simulation results show that the CLA produces correct
outputs for all possible combinations of inputs. The
simulation results for 2-bit CLA are shown in Fig.
9which ensure the correctness of the functioning of the
proposed CLA circuit.
Fig 6. Existing 2-bit Irreversible CLA circuit
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ISSN (Online): 2347-2820, Volume -2, Issue-4, 2014
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International Journal of Electrical, Electronics and Computer Systems (IJEECS)
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Fig. 8. Simulation result for proposed reversible fault
tolerant 2-bit CLA
[2]
C.H. Bennett, “Logical Reversibility of
Computation”,
IBM
J.
Research
and
Development, pp. 525-532, November 1973.
[3]
Hafiz Md. Hasan babu, Md. Rafiqu Islam, Ahsan
Raja Chowdhary and Syed Mostahead Ali
Chowdhary “ Reversible logic synthesis for
minimization of full adder ckt”, IEEE conference
on Digital system design 2003, PP 50-54
[4]
Hafiz Md. Hasan babu, Md. Rafiqu Islam, Ahsan
Raja Chowdhary and Syed Mostahead Ali
Chowdhary “Synthesis of full adder ckt using
Reversible logic”.17th International Conference
on VLSI Design 2004, Mumbai, India 2004, PP
757-760.
[5]
Feynman R., 1985. Quantum
computers, Optics News, 11: 11-20.
[6]
Peres, A. 1985. Reversible logic and quantum
computers. Physical Review A, 32: 3266-3276.
[7]
E. Fredkin, T. Toffoli, “Conservative Logic”,
International Journal of Theory of Physics, 21,
1982, pp 219-253.
[8]
Toffoli T., 1980. Reversible computing, Tech
Memo MIT/LCS/TM-151, MIT Lab for
Computer Science.
[9]
B. Parhami , “Fault tolerant reversible circuits”,
in Proceedings of 40th Asimolar Conf. Signals,
Systems, and Computers, S. Chen, B. Mulgrew,
and P. M. Grant, “A clustering technique for
digital communications channel equalization
using radial basis function networks,” IEEE
Trans. on Neural Networks, vol. 4, pp. 570-578,
July 1993,CA, pp. 1726-1729,October 2006.
[10]
E. Fredkin and T. Toffoli, “Conservative logic”,
Intl. Journal of Theoretical Physics, pp. 219-253,
1982.
[11]
Islam S. and M. Mahbubur Rahman,
2009b.Efficient Approaches for Designing Fault
Tolerant Reversible Carry Look-Ahead and
Carry- Skip Adders, MASAUM Journal of Basic
and Applied Sciences, 1(3): 354-360.
[12]
Parminder Kaur & Balwinder singh Dhaliwal
“Design of Fault Tolerant Full Adder/Subtractor
Using Reversible Gates” 2012 International
Conference on Computer Communication and
Informatics (ICCCI -2012), Jan. 10 – 12, 2012
[13]
Michael P. Frank, Reversibility for efficient
computing, Ph. D. Thesis, May 1999.
http://www.cise.ufl.edu/-mpf/rc/thesis
/phdthesis.html.
[14]
Carlin Vieri, “Reversible Computing for Energy
Efficient and Trustable computation”, April-98.
VII. APPLICATIONS
The Reversible logic is having a number of applications.
Some important application areas of reversible logic
include the following:
(1)
Nano Computing
(2)
Bio Molecular Computations
(3)
Low power CMOS
(4)
Design of low power arithmetic and data path
for Digital Signal Processing (DSP)
(5)
Laptop/Handheld/Wearable Computers
(6)
Quantum Computing
(7)
Spacecraft
VIII. CONCLUSION
This paper presents an efficient approach for the design
of fault tolerant full adder. The proposed design offers
less hardware complexity, less gate count, less garbage
bits and constant inputs. The reversible computation can
be done efficiently with less number of garbage bits and
constant inputs. In future we are planning to design
more optimize Fault tolerant Adder design and other
fault tolerant circuits i.e. less garbage bits and constant
input.
REFERENCES
[1]
R. Landauer, “Irreversibility and Heat Generation
in the Computational Process”, IBM Journal of
Research and Development, 5, pp. 183-191,
1961.
mechanical

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