Page 1 of 11
EE 435
R-2R DAC Design
Li Xu & Shiya Liu
5/1/2012
Page 2 of 11
Contents:
Introduction --------------------------------------------------------------------------------------------3
Result and discussion----------------------------------------------------------------------------------3
Wide-swing current-mode R-2R DAC -------------------------------------------------------------3
OP-AMP -----------------------------------------------------------------------------------------------5
Switch --------------------------------------------------------------------------------------------------7
Latch-up-------------------------------------------------------------------------------------------------7
Testing(INL DNL etc)---------------------------------------------------------------------------------8
Conclusion---------------------------------------------------------------------------------------------11
Page 3 of 11
1. Introduction
The purpose of this project is to design an 8-bit Nyquist-rate digital to analog converter (DAC). The R2R structure is used in our design. The specifications of the DAC are shown below.
(a) Process:
(b) Supply:
(c) Vo range:
(d) Resolution:
(e) INL:
(f) DNL:
(h) Settling time:
(i) fclk:
(i) Loading:
(j) Area:
MOSIS ON 0.5 um
0V and 5V
2 Vp-p
8 bits
±0.5 LSB
±0.5 LSB
<200ns
4Mhz
1k ohms resistor, 4pF capacitor
<1mm2
2. Result and discussion
2.1 Wide-swing current-mode R-2R DAC
Figure 1 shows the schematics of the DAC which is called Wide-swing current-mode R-2R DAC and
figure 2 shows the schematics in cadence.
Figure 1
Page 4 of 11
Figure 2
Like traditional current-mode R-2R DACs, the DAC operates on currents. The current flowing in the
feedback resistor, RF, is given by:
The output voltage of the DAC is then given, assuming R = RF, by
Page 5 of 11
2.2 OP-AMP
In order to make the DAC works, the gain and gain bandwidth of the OP_AMP should be above 70dB
and 20MHz respectively. As a result, we made some changes on the OP-AMP of lab 5 to increase the
gain and bandwidth. The graph for the OP-AMP is shown below.
Figure 3
Page 6 of 11
Gain, GB and phase margin:
The graph for the gain, GB and phase margin is shown below. The gain is about 70dB. The GB and
phase margin are 20MHz and 70degree respectively.
Figure 4
Page 7 of 11
2.3 Switch
The switch we designed for the DAC is shown below.
Figure 5
2.4 Latch-up:
The schematic for latch-up is shown below.
Figure 6
Page 8 of 11
2.5 Testing
2.5.1 INL of the DAC
Figure 8 shows the INL of the DAC we designed.
Figure 7
Page 9 of 11
2.5.2 DNL of the DAC
The graph for the DNL is shown below.
Figure 8
Page 10 of 11
2.5.3 Output of the DAC
The graph for the output is shown below.
Figure 9
Page 11 of 11
2.5.4 Settling Time
The graph for settling time is shown below.
Figure 10
3. Conclusion
After this project, we get familiar with the DAC design and know how to build a DAC to meet the
specifications. Moreover, we have more understanding about the benefits and limitations of R-2R
structure. However, because of the time limiting, there are some problems we did not pay much
attention. For example, we did not consider about the power consumption of DAC.