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Projet : MOOREA
EDITION 2012
MOOREA MEMRISTORS ORGANIQUES
ACRONYME
TITRE DU PROJET
PROPOSAL TITLE
DOCUMENT SCIENTIFIQUE
ET APPRENTISSAGE
CIRCUITS A APPRENTISSAGE A BASE DE NANOMEMRISTORS ORGANIQUES
NANO-ORGANIC MEMRISTOR CIRCUITS WITH
LEARNING CAPABILITIES
COMITÉ D’ÉVALUATION
SIMI 3
X BASIC RESEARCH
TYPE OF RESEARCH  INDUSTRIAL RESEARCH
 EXPERIMENTAL DEVELOPMENT
INTERNATIONAL COOPERATION
(IF APPLICABLE)
 OUI
GRANT REQUESTED 404254 €
X
NON
PROJET DURATION
36 MONTHS
1. EXECUTIVE SUMMARY ........................................................................ 2
2. CONTEXT, POSITION AND OBJECTIVES OF THE PROPOSAL ............................... 3
2.1.
2.2.
2.3.
2.4.
Context, social and economic issues............................................................. 3
Position of the project ................................................................................ 5
State of the art ......................................................................................... 6
Objectives, originality and novelty of the project ..........................................10
3. SCIENTIFIC AND TECHNICAL PROGRAMME, PROJECT ORGANISATION ................ 13
3.1. Scientific programme, project structure .......................................................13
3.2. Project management .................................................................................13
3.3. Description by task ...................................................................................14
3.3.1
3.3.2
3.3.3
3.3.4
3.4.
Task
Task
Task
Task
1.
2.
3.
4.
Management
see part 3.2.
Fabrication of memristors and arrays of memristors
Demonstrator
Performance analysis
14
15
18
19
Tasks schedule, deliverables and milestones ................................................22
4. DISSEMINATION AND EXPLOITATION OF RESULTS. INTELLECTUAL PROPERTY ....... 23
4.1.
4.2.
4.3.
4.4.
Dissemination Communication in the scientific community .............................23
Communication beyond the scientific community ..........................................23
Industrial developpement ..........................................................................23
Intellectual property .................................................................................23
5. CONSORTIUM DESCRIPTION .............................................................. 24
5.1. Partners description & relevance, complementarity .......................................24
5.2. Qualification of the project coordinator ........................................................25
5.3. Qualification and contribution of each partner ..............................................26
5.4. Implication of partners in other projects .....................................................27
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6. SCIENTIFIC JUSTIFICATION OF REQUESTED RESSOURCES ............................. 27
6.1.
6.2.
6.3.
Partner 1 : IEF: 124.28 K€ .......................................................................27
Partner 2 : CEA-Iramis 169.7k€ ................................................................28
Partner 3 : IMS : 110.24 K€ .......................................................................28
7. REFERENCES ................................................................................ 29
7.1. References...............................................................................................29
7.2. References of the consortium members .......................................................30
1. EXECUTIVE SUMMARY
MOOREA is a 3-year ambitious project targeting as final objective the experimental
demonstration of the learning capabilities of a neuromorphic circuit composed of nano-scale
organic memristors and their prospects for predictable performance, power consumption
and scalability. It is based on the design, modeling, simulation and physical implementation
of highly innovative nano-devices and on new architectures for hybrid circuits.
Miniaturization in microelectronics drives the digital economy but also faces very strategic
challenges. In this context, long term research projects should contribute to this
miniaturization, and most importantly, to (i) the multiplication and diversification of
integrated functions and (ii) the management of power consumption. Nano-devices, thanks
to their ultimate size and original functionality, will be key elements of this evolution,
provided that technological variability inherent to the nano-scale can be handled. With their
intrinsic tolerance to defects and their auto-compensation capabilities coming from a
learning stage, neuromorphic architectures allow lifting this critical roadblock. Nanomemristors, which are programmable resistors, are ideally suited to be integrated in dense
crossbars and used as nano-scale synapses in such architectures. Moreover, beyond synaptic
function, the variety of behavior that allows the use of organic compounds gives access to
entirely new utilizations of memristors for very high density implementation of the neurons
including their learning capabilities. In addition, the non-volatile memory capabilities of the
memristors allow designing circuits with minimized standby-power consumption and thus
contribute efficiently to tackle the energy issue.
At the device level, the focus will be put on a new class of organic memristors, the active part
of which will be redox and charge separation organic complexes grafted on the bottom
electrodes of the crossbars. The top electrode will be fabricated by transfer printing. While
ambitious, MOOREA is designed to minimize risks. Indeed, the functionality and robustness
of a first type of organic memristive material have already been assessed by the consortium,
as well as its compatibility with transfer printing processes. In addition, conventional
inorganic memristors will also be fabricated to serve as a comparison in a benchmark effort.
In the more exploratory part of the project, individual carbon nanotubes will be used as
electrodes for fully organic nano-memristors. It will notably allow the evaluation of scaling
laws for energy and speed performances.
We will develop the first physics-based and compact models of memristors adapted to
circuit design and propose new architectures for adaptive circuits. The project will lead to
the conception and realization of a full demonstrator of nano-memristor based circuit with
learning capabilities.
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Figure 1 : MOOREA organization, inputs from previous project and outcomes.
2. CONTEXT, POSITION AND OBJECTIVES OF THE PROPOSAL
As CMOS technology approaches its physical and economical limits, innovative solutions
must emerge to continuously offer new functions and services in embedded systems. In this
context, experimental demonstrations of nano-devices and, more importantly, of functional
assemblies of such scaled-down devices pave the way to radically new technologies.
However, the associated system architectures must also be adapted to these new device
characteristics, notably to cope with their high variability and defect rate.
In the following, we position MOOREA relative to (i) the global economical and societal
context (part 2.1) and (ii) several related projects at the international and national levels (part
2.2).
2.1. CONTEXT, SOCIAL AND ECONOMIC ISSUES
During decades, fabrication costs and
performances in terms of speed and power “Another class of challenges is to extend
information processing substantially beyond
consumption benefited from the technology
that attainable by CMOS alone using an
scaling. As the size of devices advances further
innovative combination of new devices and
into the nanoscale era, physical limits, power architectural approaches for extending CMOS
consumption and costs issues question this and, eventually, inventing a new information
economic model.
processing platform technology.” ITRS 2009.
The ITRS Roadmap for Semiconductors has been considering for several years the topic of
Emerging Research Devices. In its 2009 Edition [1], one can notably read: “The
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semiconductor industry is facing two classes of difficult challenges related to extending
integrated circuit technology to and beyond the end of CMOS dimensional scaling. One set
relates to extending CMOS beyond its ultimately scaled density and functionality by
integrating, for example, a new high speed, dense, and low power memory technology on
the CMOS platform. Another class of challenges is to extend information processing
substantially beyond that attainable by CMOS alone using an innovative combination of
new devices and architectural approaches for extending CMOS and, eventually, inventing a
new information processing platform technology.” In addition, in the 2010 update of ITRS
the ERD/ERM working groups identified Spin Transfer Torque MRAM and Redox RRAMas
emerging memory technologies recommended for accelerated research and development. As a
long-term research project, MOOREA will definitely drive original and useful contributions
to this field.
In the present context, nano-scale crossbars could introduce a new field of innovation with
numerous attractive features. First, they pave the way of very low cost technologies with
ultra-high integration density. In addition, as they rely on non-volatile technologies, the
static and stand-by power consumption will be very limited. Most importantly, they are
based on a post-fabrication configuration or learning stage. As a first consequence, offering
new embedded functions does not require specific chips and there is an opportunity to
recoup the manufacturing costs of masks on a much larger number of units. Secondly, this
scheme opens a new business model with a high added value market in the field of
specialized post-fabrication learning and/or configuration to implement new functions like
pattern and speech recognition, associative memory and data mining.
The development of radically new devices implies radically new circuit architectures.
However, as also mentioned in [1]:”Most of the architectures that have been considered to
date in the context of new devices utilize binary logic to implement von Neumann
computing structures. In this area, CMOS implementations are difficult to supplant because
they are very competitive across the spectrum of energy, delay and area”. Only quite
recently, new paradigms of architectures specially dedicated to nano-devices have emerged
(see part 2.3). Among them adaptive ones and in particular neuro-inspired ones, are of
particular interest. Neural networks have been studied for a long time but can now bring
decisive new contributions for nano-scale computing. Indeed, in a neural network type of
circuit, a learning process makes the circuit naturally tolerant to defects and variability
among individual devices. It mainly requires as building blocks “artificial synapses”, which
in their simplest and smaller form could be 2-terminal non-volatile analog memory elements,
namely “memristors”. During a previous project (ANR-ARFU-PANINI 2008-2010) we have
developed and patented new learning rules specially adapted to arrays of such new type of
synapses [IEF8, IEF11].
Moorea will study the potential Thanks to the rich functionality provided by the use of
implementation of very high-density organic memristors, we will study the potential
neural networks based on implementation of very high-density neural networks
memristors to perform both the based on memristors to perform both the synaptic
synaptic crossbar and the neural crossbar and the neural function including on-chip
function including on-chip learning. learning. Economical issues are of paramount
importance in this field of alternative/innovative devices and architectures.
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2.2. POSITION OF THE PROJECT
MOOREA aims at addressing several “difficult challenges” outlined in the ITRS 2009 and
2010, specially to Bridge the knowledge gap that exists between materials behaviors and
device functions in the context of “redox RAM” for which ITRS recommends to “receive
additional attention in research and development to accelerate progress toward
commercialization
and, significantly,
IRC approved communication
of
these
recommendations to the research community and to funding agencies.” More precisely,
MOOREA intends to address elements in both More Moore and More than Moore directions
through 2 objectives:
- Objective 1 (More Moore): we propose to build neuronal logic blocks, based on threshold
logic benefiting of supervised learning capabilities with low overhead to enable low cost,
reliable, ultimate-scale (memristor based), reconfigurable architectures (FPGA-like) for
beyond Moore digital applications.
- Objective 2 (More than Moore): MOOREA targets neural coprocessors for data mining,
image analysis, pattern recognition in order to discover and reduce to practice new device
technologies and a primitive-level architecture to provide special purpose optimized
functional cores heterogeneously integrable with silicon CMOS [1].
As exposed in details below (see part 2.3), organic memories are attracting large interest. A
very significant part of the related research efforts concerns on one hand the materials
themselves (synthesis, stability, etc.) and on the other hand the associated low cost
processing technologies (inkjet printing, roll-to-roll printing, etc.). These are indeed
important issues. However, MOOREA is primarily addressing different aspects of the
problem: the scalability of memories toward truly nano-junctions within dense crossbars and
the development of new functionalities through unconventional circuit architectures. In this
field, we are not aware of competing projects targeting nano-scale organic memory circuits
with learning capabilities. However, large scale projects emerging worldwide show the
growing importance of “nano-computing approaches” in general.
Neuro-inspired projects (that we are aware) are summarized in table 1.
The HP-lab early worked on memristors and intends to co-integrate this technology with
CMOS to propose a universal non-volatile memory. There is currently no information about
any
project
of
memristor-based
neural
networks
at
HP-lab
(see
http://www.hpl.hp.com/research/intelligent_infrastructure.html).
TABLE 1 : PROJECTS TARGETTING NEURO-INSPIRED HARDWARE
SYNAPSE
PROJECT NAME
LONG TERM OBJECTIVE
1
COG EX MACHINA
(HP LAB)
2
FP7-FACETS
3
FP7-BRAINSCALES
COGNITIVE
NEURON
TECHNOLOGY
TECHNOLOGY
DIGITAL CMOS
DIGITAL CMOS
DIGITAL CMOS
DIGITAL CMOS
DIGITAL CMOS
DIGITAL CMOS
LEARNING METHOD
COMPUTING,
INSPIRED BY HOW THE HUMAN
BRAIN WORKS,
ACCELERATE BRAIN EMULATION
IN-VIVO
STDP
BIOLOGICAL
EXPERIMENTATION
AND
COMPUTATIONAL ANALYSIS
TABLE 1 (CONT.): PROJECTS TARGETTING NEURO-INSPIRED HARDWARE
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PROJECT NAME
LONG TERM OBJECTIVE
DOCUMENT SCIENTIFIQUE
SYNAPSE
NEURON
TECHNOLOGY
TECHNOLOGY
MEMRISTOR
(INORGANIC)
CMOS
STDP
CMOS
STDP
CMOS
STDP
OPTICALLY-GATED
CARBON
NANOTUBE FET
CMOS
SUPERVISED, INSPIRED
FROM « DELTA RULE »
SEE LIAO ET AL. TCAS
2011.
ORGANIC
ORGANIC
MEMRISTOR
MEMRISTOR
(ANALOG)
(BINARY SWITCH)
LEARNING METHOD
PORTING NEURON BEHAVIOR IN
4
FP7-BRAIN-I-NETS
5
CHISTERAPNEUMA
AUTONOMOUS
SYSTEMS.
6
ANR-MHANN
MEMRISTOR+ASIC BASED ANN
MEMRISTOR
(SPINTRONIC)
7
FP7-NABAB
(FINISHED) [3]
ADAPTIVE COMPUTING WITH
3-TERMINAL
NANODEVICES
MEMORY DEVICES
8
ANR-PANINI
(FINISHED) [4]
FPGA-LIKE
NEUROMORPHIC HARDWARE
COGNITIVE
LEARNING
ARCHITECTURE
ANN ACCELERATOR AND
MOOREA
(PROPOSAL)
Projet : MOOREA
DEFECT TOLERANT
PROGRAMMABLE NEURO
ARCHITECTURE
SUPERVISED, INSPIRED
FROM « DELTA-RULE »
SEE PATENT N °
PCT/FR2009/05094
*STDP=Spike-timing-dependent plasticity is a functional change of synapses that are sensitive to the timing of action potentials.
We can find two categories of neuro-inspired projects: The first category (project n°1 to 4) is
targeting the simulation of very important complex neural systems, typically brain-sized and
they are mostly based on standard digital hardware. Projects of the second category (n°5 to
8) do not address such complex system but are based on emerging devices, mainly inorganic
memristors to implement the synaptic array, while analog CMOS is used for neurons. FP7NABAB (with CEA-LEM) and ANR-PANINI are exceptions: they relied on 3-terminal
organic devices. Except for ANR-PANINI, the learning approach is unsupervised and based
on STDP*. Although interesting to learn more on the brain, this approach is difficult to
implement for an effective application. In contrast, supervised approaches are already
widely used in many applications (forecasting, financial, inverse problem, robotics, etc.). It is
also noticeable that we are not aware of any project where the neuron element is
implemented with a non-CMOS technology.
All together, these projects show that the emerging field of “nano-architectures” or “nanodevices based circuit architectures” is very active and is gaining momentum, in particular in
conjunction with the neuro-inspired approach. At the international and European levels,
both the investments and the ambitions are very high. We estimate that at a national scale,
the “white” ANR call is the ideal place for a multidisciplinary project bridging nano-device
physics, modeling and circuit architectures.
2.3. STATE OF THE ART
Considering the multidisciplinary nature of MOOREA, the state of the art must be
appreciated from several perspectives: unconventional circuit architectures, nano-device
modeling, organic and inorganic resistive memory devices.
Memristor-based synapses for neural networks:
After the publication in Nature by HP lab [2], memristors have attracted the interest of many
research groups and in 2011, promising results of memristor-based neural networks have
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been published. They are summarized in table 2. Again, apart from n°8 (ANR-PANINI) all of
them mimic STDP. In addition, results n°1, 2 and 3 are based on inorganic memristors.
Results 1, 2 and 4 correspond to an individual memristor with STDP like behavior. Only
result 5 corresponds to a small function with 2 inputs, but the memristors are emulated with
MCU* and ADC*. On the other hand, the results of ANR-PANINI correspond to 8 opticalgated nanotube-FETs implementing 3 logical inputs (result n°6). Although it is not yet
published the results of Panini are at the state of the art and we want to capitalize on this
advance in Moorea to go much further using organic memristors.
TABLE 2 : EXPERIMENTAL DEMONSTRATION OF SYNAPTIC BEHAVIOR WITH MEMRISTORS
NEURO
SYNAPSE
N
LEARNING
1ST AUTHOR / REF
EXPERIMENTAL RESULTS
TECHNOLOGY
TECHNO METHOD
LOGY
1
SEO [5]
INORGANIC (TIO2)
2
OHNO [6]
3
JO [7]
4
ALIBART [8]
PENTACEN FET
5
DI VENTRA [9]
MCU + ADC
6
GACEM [UNPUBLISHED, IN
PREPARATION]
OPTICAL
CNT FET
STDP
INORGANIC
STDP
(AG2S)
INORGANIC (AG/SI
MIXTURE)
GATED
MCU +
ADC
EMULAT
ED BY A
STDP BEHAVIOR OF ONE SYNAPSE
STDP BEHAVIOR OF ONE SYNAPSE +
BEHAVIOR SPECIALIZATION OF 7X7 PIXELS
(MOVING ELECTRODE)
STDP
STDP BEHAVIOR OF ONE SYNAPSE
STDP
STDP BEHAVIOR OF ONE SYNAPSE
EMULATION MEMRISTOR TO REPRODUCE
PAVLOV'S DOG CONDITIONING : 2 INPUTS
(BELL/FOOD) 1 OUTPUTS (SALIVA)
STDP
SUPERVISED
« DELTA
RULE » SEE
[LEM5].
AUTOMATIC
LEARNING
OF
3-INPUT
FUNCTION WITH 1X8 CROSSBAR
NOTES
*MCU : “Micro-Controller Unit.
*CNT-FET: Carbon NanoTube Field-Effect Transitor
*ADC: “Analog to Digital Converter”
Organic memory devices: Organic memories are attracting very significant scientific interest
due to several key properties, in particular: rich structure flexibility through chemical
synthesis, low cost, solution processability, low-power operation, multi-level memory, and
mechanical flexibility. Among organic memories, non-volatile devices with switchable
resistive materials are the most promising due to the simplicity of their design and the
associated scalability. Recently, the 3D organization of organic resistive memory devices was
initiated [10]. A wide range of materials, including polymers, oligomers, small organic
compounds, or blends of nanoparticles in organic hosts have been reported for electrical
switching and non volatile memory effects [11,12]. Several mechanisms were proposed to
account for the electric-field assisted conductivity switching in resistive memories: reversible
filamentary conduction, trap-charge and space-charge effects, charge separation effect in
donor-acceptor (D-A) systems, conformational change and ionic conduction [11,12].
Nevertheless, despite a large number of experimental realizations of macro-scale organic
memories, still very few of them present convincing studies of the physical mechanisms. One
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reason is that the details of sample preparation and morphology, electrode materials,
interfacial properties, device structures, testing methods, environment, and the nature of the
peripheral measuring circuits can have profound effects on performances. Still, with the
improvement of transport models and the help of variable temperature measurements
steady progress is made at the physics level. In MOOREA, we will consider devices in which
the memory phenomena arise from the bulk properties of the organic materials. We will
consider redox complexes, the conductivity of which differs from the oxidized to the reduced
state and charge-separation complexes. Few examples of such memory devices exist which
show: non volatility, ON/OFF current ratio superior to 103 [13,14], switching times shorter
than 20µs [13], no obvious degradation during retention and stress tests [13,14], no
degradation observed over 106 write-read-erase-read cycles [13]. The retention ability tested
under ambient conditions is presently between few hours and several months [13]. We
notably describe below our preliminary results showing robust and stable memory effects
with a redox complex.
Memristor modeling: One of MOOREA’s challenges is the proper description of the device
within the learning circuit design. Therefore, compact models (SPICE-like) of organic nanomemristors are mandatory. This type of model allows designers to simulate logical and/or
analogical functions within complex integrated circuits. At present, very few studies on
memristor compact models have been published and most importantly, none of them
concern organic nano-memristors. In 2008, a significant modeling result was published by
the HP-Labs [2]. A key feature of this memristor compact model consists in a physics-based
description of the microscopic nature of resistance switching and charge transport in the
device. They assume that the semiconductor thin film has a region of low resistance RON
(high dopant concentration) and one of much higher resistance ROFF (low dopant
concentration). The application of an external bias across the device moves the boundary
between the two regions by causing the drift of the charged dopants. This compact model
will serve as starting point for MOOREA.
Compact and physics-based models of organic devices were principally constructed for
organic field-effect transistors. In this case, various specific mobility laws in organic
materials were derived (see examples in Ref. [15-21]). In MOOREA, physics-based models of
organic nano-memristors will be constructed, based on existing laws of conductivity in
organic materials, recent work on mechanisms at play in organic macro-scale memristors
and experiments conducted in the project, among which cyclic voltammetry and
temperature dependant transport measurements.
In addition, in the case of memristors addressed by carbon nanotubes, the impact of these 1D
nano-electrodes will be considered at the modeling level. Considering a system of parallel
metallic CNTs, one can describe the interconnect behavior of the nanotube in accordance
with a simple transmission line model [22]. Also, under high bias and/or long-interconnect
lengths, electron-phonon interactions start to play an important role and the effects of
scattering have to be taken into account.
PRELIMINARY RESULTS WITHIN THE CONSORTIUM
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(1) At the device level: Recently, we showed that the proposed iron-based redox complex
(Task 2.1a) does show very strong and robust resistance switching effects associated with
non-volatile memory capabilities (see figure 2). These preliminary tests included the electrografting step but were done in macroscopic junctions not produced by micro-contact
printing. Several control experiments were performed to exclude parasitic effects (metal
filament formation, mechanical movement of the top electrode…). This result shows that the
proposed memristive material is promising. Yet its use in functional circuits requires
extensive work to consolidate and extend the preliminary results.
Top electrode: Al / PEDOT:PSS
ERASE
2
-4
V (V)
10
WRITE
-2
READ
200
READ
ON
I (A)
-4
-6
10
-6
WRITE
-7
10
ERASE
0
-8
I (µA)
-5
10
400
0
READ
OFF
-10
-8
Bottom electrode: ITO
10
-200
-12
-3
-2
-1
0
V (V)
1
2
3
0
50
100
150
200
time (s)
Figure 2: principle of an organic memory device based on electro-grafted iron complexes. I(V) curves showing the bias-induced
conductivity switching at reproducible thresholds. I(t) curve showing the stability of the maximal and minimal conductivity
states.
(2) At the crossbar fabrication level: The micro-contact printing technique (µCP) is under
development at CEA-Iramis LCSI (see Task T2.1b). Presently, we are able to transfer, with
nearly ideal yield, macroscopic scale gold electrodes (width 100 µm) on predefined bottom
electrode arrays (see figure). We also
verified that the technique preserve the
quality of organic layers (including ironcomplex films) grafted on the bottom
Transferred
top electrodes
electrodes. The down-scaling of the
Grafted bottom
technique (by increasing the lithography
electrodes
resolution of the master mold) will not be
an issue, at least down to the 1 µm scale.
(3) At the architecture level: During the project ANR-Arfu PANINI, principally devoted to
3-terminal devices, we also studied learning methods, architectures and circuits based on
generic memristors models with various characteristics [23]. The resulting architectures
served as basis during all the duration of the project to develop robust learning methods and
explore their applications in the context of image processing. We specially addressed four
difficult challenges (1) we demonstrated the possibility to learn non-linearly separable
functions without any complex hardware associated to the back-propagation algorithm, (2)
we propose an original implementation of the neuron circuit suppressing the usual CMOS
overhead dedicated to the learning step (3) we proposed an efficient competitive learning
method in order to avoid defects and learn without the need to detect them, (4) we proposed
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an architecture inspired from FPGA1 to target complex digital systems while benefiting from
the existing framework in the field of synthesize tools and we explored its application to
arithmetic operators and image processing. Some key results, notably learning methods,
have been patented during the PANINI project but not yet implemented. All these outputs
provide an important advance to our consortium in the field of integration of neural
networks based on memristors.
(4) At the integration level: During the PANINI project, we develop an experimental setup
specifically dedicated to the rapid prototyping of learning methods based on nanoscale
components (see Figure 3). While the devices targeted were not memristors but nanotubeFETs, the experimental setup based on nanodevices connected in a standard dual-in-line
package, mounted on dedicated circuit board and controlled with a FPGA proved to be very
efficient and will be quite similar for memristors. As far as we know, this setup developed in
collaboration between CEA-LEM and IEF allowed the first learning demonstration of logic
functions based on nano-components worldwide (see table 2).
Programmable nanotube FETs
Interface board
X1+
X1- X2+ X2X3+ X3- Bias+
BiasFunction
output
Rij
VG
C.(/A+/
B)B)
C.(/A+/
Control circuit (FPGA)
MAJ(/A,
B,B,
C)C)
MAJ(/A,
Micro-chip
0 00 0 0 00 01 11 11 10 0
Instruments
0 00 0 1 10 01 10 01 11 1
/A.B.C
/A.B.C
NAND(A,
B,B,
C)C)
NAND(A,
3-input
function learning
Figure 3: Experimental setup dedicated to the prototyping of nanodevices and learning results.
2.4. OBJECTIVES, ORIGINALITY AND NOVELTY OF THE PROJECT
1 11 11 11 11 11 11 10 0
0 00 00 00 00 00 01 10 0
A majority of the studied memristors consists in simple metal-oxide-metal junctions (for
example Pt-TiO2-Pt). In this case, the electrodes are crossed metal wires fabricated by
conventional lithography or transfer printing. To date, in the field of neuromorphic
electronic, this approach has led to limited experimental results almost restricted to the
demonstrations of some functional similarities between individual memristors and biological
synapses. In order to scale to complex systems and consider real applications, it is necessary
to go well beyond and at first to smartly integrate the functions of neurons. The most
commonly proposed solution is to provide a CMOS implementation for the neurons. This
solution is not satisfactory. It constrains to operate a large number of synapses per neuron to
retain an advantage in terms of density, which leads to enormous problems of reliability. On
the other hand, the integration of neurons composed of memristors used as binary switches
is possible (see figure 4). This concept is based on the behavior demonstrated in [24] where
binary switches operate as conditional operators depending on the state of one terminal and
the amplitude of the pulses applied to the other. It only requires the availability of different
types of memristors, with different thresholds for writing pulses. This warrants that learning
1
Field Programmable Gate Array
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pulses dedicated to synapses will not reprogram the connections of memristors switches in
the neurons.
Organic materials have many advantages in this context among which one can note:
- the extraordinary diversity of structures and associated properties that arise from
chemical synthesis
- the existence of self-assembly and grafting processes capable of ordering molecules at
the nano-scale
- their low cost
- large substrate compatibility (including plastic substrates and above-IC
environments)
- the demonstrated existence of several physical mechanisms yielding very large
conductivity change in thin organic films
- the possibility to tune the switching threshold (i.e. the programming biases) through
synthesis
- the possibility to mix molecules (and their properties) into hybrid materials.
Fig. 4.a: Nano Cross-bar including a compact memristor-based neuron compatible with
on-chip-learning sequences for bipolar devices described in [IEF11].
Fig 4.b : Principle of operation of a
neuron
based
on
conditional
switches that performs on-chiplearning [23].
Stability and robustness can be critical issues for single molecule
In such case, the overhead of electronics, but progresses in chemical synthesis and processing
CMOS neuron circuit is are such that very thin films of covalently bonded molecules
totally suppressed, leading have very promising properties down to the nano-scale. In
to an amazing increase of particular, our preliminary results briefly described in part 2.3
the integration density.
show that robust and stable memristors can be built from such
materials. In addition, in the organic approach, the possibility to tune the write and erase
biases through chemical synthesis will permit to perform both neuron decision steps and onchip learning with local hardware limited to two transistors and two memristors operating
like "conditional switches" with higher thresholds than those used as synapses (see figure 4).
In such case, the overhead of CMOS neuron circuit (usually critical but mandatory to
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implement the learning step) is totally suppressed, leading to an amazing increase of the
integration density.
The global objective of MOOREA is to design, model, simulate and physically implement
a full adaptive circuit in which both the array of synapses and the neurons are based on
organic nano-scale memristors. This nano-scale circuit will be interfaced to an external
circuit made of conventional electronics to control the learning function. In more details, this
objective can be decomposed as follows:
1. Design, fabricate and characterize organic memristor arrays. The resistive material will
be a thin (5-20 nm) and robust (covalently bounded) organic film. Switching thresholds will
be adjustable through the choice of the organic materials and different materials could be
used for synapses and neuron functions.
2. Acquire a comprehensive understanding of the physical mechanisms of memristive
switching. Available redox molecules with clear memristive properties will first be used.
Then, new donor-acceptor complexes with anchoring groups will be synthesized and
studied. We will use electrochemical, Raman and transport measurements (including
variable temperature and controlled environment) to identify in depth the physics at play.
3. Develop memristor models. Today, no efficient compact model of organic memristors
exists. This is however a key requirement for circuit design activities. We will develop two
classes of models: (i) Behavioral models (optimized for their speed and small number of
parameters). (ii) Physics-based models capturing the details of the mechanism. Both types of
models will represent highly original and useful contributions to the field.
4. Physically implement and fully characterize functional arrays of memristors. At the
single device level the important properties are speed, stability, cyclability, etc. Arrays
include new issues: controlled device-to-device variability, reduced crosstalk between
neighboring devices. Independently of the type of memristors, very few studies have
reported functional arrays of memristors and even less showing either scalability or
independent programmability. MOOREA thus has a real opportunity to make particularly
significant contributions to the field.
5. Aggregate all the above-described efforts to build a full circuit demonstrator with
learning capabilities composed of an array of memristive devices and a control silicon-based
circuit. This objective is the logic concluding step of the proposed work program.
In addition, constant and precise benchmarking of our achievements will be performed at
several levels: individual devices, models, architectures, arrays of coupled devices and
demonstrators. This work will notably be helpful (in complement with the traditional
indicators, in particular, the quality and visibility of the publications, filed patents and
conferences) for the evaluation of the project. We will propose figures of merit to compare
MOOREA’s outcomes within the international competitive context. They will notably
include performances, power consumption, scalability, originality (in the intellectual
property context) and CMOS-compatibility.
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3. SCIENTIFIC AND TECHNICAL PROGRAMME, PROJECT
ORGANISATION
3.1. SCIENTIFIC PROGRAMME, PROJECT STRUCTURE
The main purpose of each task is described briefly here and in full details in Part 3.3. A
graphic on the next page highlights the interplay between tasks and a Gantt chart
summarizes the schedule.
Task 1: Coordination. Leader: Prof. Jacques-Olivier Klein, IEF, UMR CNRS 8622, Université
Paris-Sud, See part 3.2.
Task 2. Fabrication of memristors and arrays of memristors. Leader: Bruno Jousselme
(CEA-Lcsi). This task is dedicated to the complete fabrication of memristors arrays: synthesis
and grafting of memristive organic material, realization of crossbars using micro- and nanocontact printing.
Task 3. Demonstrator. Leader: Vincent Derycke (CEA-Lem). This task gathers all the
partners around a central objective: building the final demonstrator. It starts with the design
of a learning control board to host the memristor chip and finishes with the experimental
demonstration of the learning capabilities.
Task 4. Performance analysis. Leader: Cristell Maneux (IMS). Based on characterization, this
task aims to identify by modeling, calculation and simulation, the perspectives memristor
crossbars, especially in terms of scalability performances and power consumption. This
includes the collective study of arrays of memristors from circuit design to simulation.
Performances and scability evaluation of nanoscale neuro crossbar will be analyzed and
compared with others devices and architectures. It involves the 3 partners.
3.2. PROJECT MANAGEMENT
We have dedicated Task 1 to the coordination of MOOREA in order to organize, lead and
plan the project objectives.
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The project coordinator is responsible for task 1. In addition, the coordinator will organize
and animate two types of meetings: Executive Committee and Plenary meetings.
Executive Committee:
Each coordinator of task will be involved in the Executive Committee with the coordinator of
the project. Thus executive committee will be composed of:
•
Jacques-Olivier Klein, IEF, project coordinator,
•
Bruno Jousselme, CEA-Iramis (LCSI), coordinator of Task 2,
•
Vincent Derycke, CEA-Iramis (LEM), coordinator of Task 3,
•
Cristell Maneux, IMS, coordinator of Task 4.
The executive committee will supervise the progress of the project and its consistency with
the objectives. It is mainly in charge of coordinating and planning to optimize the efficiency
of the exchanges between the partners.
Plenary meeting: The whole consortium will meet to review the project status and scientific
results. In conjunction with the project coordinator, task coordinators are responsible for
coordinating meetings and tasks to summarize the results in plenary meetings, plan
objectives and work throughout the project.
Finally, the project coordinator will prepare the minutes of both types of meeting. He will
manage the interaction with ANR and the website of the project.
3.3. DESCRIPTION BY TASK
3.3.1 TASK 1. MANAGEMENT
TASK N°
1
DURATION
LEADER
PARTNERS
RESOURCES ( H.MOIS )
SEE PART
36 MONTHS
3.2.
START
JACQUES-OLIVIER KLEIN, UPS-IEF
UPS-IEF
CEA-IRAMIS
9
3
T0
TOTAL
HXM
15
IMS
3
• OBJECTIVES:
Task 1 is transverse to the whole project and implements the coordination activities.
• WORK DESCRIPTION:
Task 1 implements the following coordination activities:
For the project coordinator:




Interact with ANR,
Maintain the web site,
Encourage the dissemination of our results. Details on dissemination and intellectual
property management are exposed in Part 4,
Organize the executing committee meetings (by conference call or video conference)
at least once every three months,
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

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Organize the plenary meetings every 6 months,
Write minutes of the meetings.
For the Executive Committee:




Prepare and follow the consortium agreement,
Coordinate the scientific activities, manage the interaction between the tasks,
Coordinate the dissemination,
Provide report and deliverables.
Annual activity reports will be delivered. They will include all required
administrative, financial, scientific and dissemination assessments.
While it is not mandatory, the partners decided to provide MOOREA with a formal
Consortium Agreement to be signed at the earliest.
CONTRIBUTION FROM PARTNERS
IEF
PROJECT COORDINATION.
CEA
COORDINATION OF TASK 2 AND 3.
IMS
COORDINATION OF TASK 4.
3.3.2 TASK 2. FABRICATION OF MEMRISTORS AND ARRAYS OF MEMRISTORS
TASK N° 2
DURATION
18 MONTHS
START
T0
TOTAL
HXM
LEADER
BRUNO JOUSSELME, CEA-IRAMIS
PARTNERS
UPS-IEF
CEA-IRAMIS
IMS
6
18
3
RESOURCES ( H.MOIS )
27
• OBJECTIVES:
This task aims at providing the project with arrays of organic memristors with appropriate
properties to be used as synaptic array and neuron elements.
• WORK DESCRIPTION:
T2.1 Synthesis and grafting of memristive organic materials (M0-M15)
This task aims at providing the project with organic compounds with appropriate properties,
in particular: (i) the possibility of forming thin, dense, robust and homogeneous films by
electrochemical grafting on conducting electrodes, (ii) the existence of multiple states of very
different conductivity, (iii) the possibility to switch between these states at low electric field,
(iv) a good stability of the programmed states, (v) a good robustness upon multiple cycles. It
also includes the electro-grafting activities to provide the project with arrays of
functionalized bottom electrodes of the crossbar arrays.
• T2.1.a Synthesis of bistable compounds with anchoring functions :
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Tris(bipyridine) transition metal complexes present the ability to be
X
X
N
oxidized and reduced reversibly leading to bistable memory characteristics
N
N
Y
[25-27]. Changing the metal center or the ligands allows tuning the redox
N
N
N
properties of the complexes and thus the electronic characteristics of the
memory device. The CEA-LCSI has the leadership on the synthesis of metal
X
complex derivatives bearing diazonium functions (see figure). These
N or -H
X=
chemical functions allow the electrochemical grafting of the complexes on
Y = Ru, Fe, Co, Os
conducting substrates using soft conditions [LCSI6]. Iron complex giving
non-volatile memory characteristics will be first produced at gram scale and use in testdevices to help optimize all the other aspects of the device preparation and analysis. Then,
complexes with other metal centers like Ru, Co or Os and different ligands will be
investigated to achieve compounds with different redox properties so as to establish the
mechanism of the memory effect and to improve the performances.
2+
2
+
• T2.1.b Grafting of molecular complexes :
Diazonium salts are increasingly used to electro-functionalize conducting surfaces [28]
and/or nano-objects [29]. This grafting method involves (i) a strong link (covalent) between
the substrate and the radicals obtained after reduction of the diazonium salts and (ii) the
polymerization of the diazonium monomers on the electrodes. This electrochemical process
enables the localization of the functionalization on surfaces [30,31] and the control of the film
parameters. This powerful technique will be applied to locally deposit the specific organic
compounds from T2.1a. Thin, homogeneous and smooth films in the 15-30 nm or 5-10 nm
range will be targeted respectively for electrodes with micrometer or nanometer width size.
The organic compounds will be first electro-grafted on metallic lines using potentio-dynamic
or potentio-static conditions to study the thickness and morphology of the polymers films
formed on the electrodes. The better conditions will be used to functionalize the different
circuit topologies from Task 3.
Local electrochemical grafting allows using different molecules on different
electrodes within the same circuit. This strategy will be studied in particular to differentiate
the thresholds of synapse and neuron devices.
Risk management: T2.1a is purposely designed as a low risk task since one organic complex
that presents good properties is already available and tested. T2.1b is also a low risk task as
electro-deposition via the diazonium salts on metallic electrodes is well mastered at LCSI.
T2.2 Memristors Fabrication (M3-M18)
T2.2.a Arrays of organic memristors by micro-contact printing
For organic memristors, the impact of the top contact fabrication method is an important
issue. Conventional deposition of metal on top of organic layers deteriorates the quality of
molecular films. Thus, a soft transfer method called micro-contact printing (µCP) will be
used for the deposition of the top electrodes of the crossbar. This process uses a master
Polydimethylsiloxane (PDMS) stamp to form patterns of metallic electrodes on the surface of
a substrate through conformal contact. It has potentially very high resolution since the
master wafer is fabricated by conventional lithography. It is yet a low cost, large area
technique since the high resolution lithography is performed only once. The master wafer
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can then be re-used. For another project, we have developed µCP adapted to the deposition
of macroscopic gold electrodes (100 m width) [LCSI1]. In Moorea, the aim is to decrease the
width of the electrodes by three orders of magnitude. The use of small size memory elements
with thin memristive films will allow to target both speed and low power consumption. This
part will be developed by the Post-doc in the LCSI group (CEA) through the use of the
nanofabrication facility of CEA-Iramis SPEC.
Metals with different work functions will be studied to elucidate the mechanism responsible
for the resistance switching. Thus, µCP of silver and aluminum electrodes will also be
developed in this task.
Risk management: Our experience with µCP let us estimate that down scaling of the
crossbars to the µm scale (width and pitch) will not be an issue. Going toward the 100 nm
scale with µCP is more risky (not intrinsically but based on our equipment and time
constraints) but cannot endanger the realization of the demonstrator that can be realized
with larger electrodes. The highest achieved resolution will be beneficial for the scaling study
(speed, energy) and is thus worth the efforts and risk.
T2.2.b Arrays of inorganic memristors
Inorganic memristors based on oxides are intensively studied and their fabrication in
medium-scale crossbar arrays is not an issue. In 2010, the CEA-Lem fabricated for the
purpose of comparison with organic memory devices, small arrays of Pt-TiO2-Pt junctions.
While easy to fabricate by conventional lithography, these conventional junctions suffer from
severe limitations when used in real circuits. Among them, one can cite: the necessity of a
‘forming step’ (a preparation step that must be cautiously performed for each device
individually) and the usual requirement for a protection (compliance) on the current drive
during the write step of the memory bits. In addition, most oxide formation requires a high
temperature step, not ideally compatible with a CMOS co-integration at the back-end step.
In Moorea, we will pursue this work for two reasons: allowing a detailed comparison of the
pro/cons of the organic vs inorganic strategies and allowing the test of some parts of the
demonstrator (interface board with equipment) before organic memristors have been
optimized. For that purpose, we will not focused on TiO2 as memristive materials since
recent studies show the superiority of HfO2 and TaOx.
Risk management: no risk. CEA-Lem already has protocols for the fabrication of inorganic
memristors. On the contrary, this task was added to limit risks of delays of T4 during the
study of more interesting / more original organic memristors.
CONTRIBUTION FROM PARTNERS
IEF
EXPECTED BEHAVIOUR OF MEMRISTORS FOR NEURAL NETWORK APPLICATIONS.
CEA
SYNTHESIZE, GRAFTING AND FABRICATION.
IMS
EVALUATION OF TECHNOLOGICAL FEATURES TO BE INCLUDED INTO THE PHYSICAL COMPACT MODEL
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3.3.3 TASK 3. DEMONSTRATOR
TASK N° 3
DURATION
24 MONTHS
LEADER
PARTNERS
RESOURCES ( H.MOIS )
START
T0+12
TOTAL
HXM
42
VINCENT DERYCKE, CEA-IRAMIS
UPS-IEF
CEA-IRAMIS
IMS
30
9
3
• OBJECTIVES:
This task aims to demonstrate experimentally the learning capabilities of crossbars of
memristors.
• WORK DESCRIPTION:
The learning stage will require applying voltage pulses to pre-synaptic and / or post synaptic
conductors depending on the neuron response. Learning techniques will be mainly based on
methods patented by IEF for ideal memristors. Nevertheless, as long as the learning methods
are subject to adaptations depending on the actual characteristics, it is much more efficient to
separate the digital control circuit, synthesized in a commercial FPGA with a hardware
description language. An analog board will interface the FPGA and the memristor crossbar,
mainly to operate the switching of the required voltages during programming pulses and to
operate analog comparisons corresponding to the neurons threshold.
T3.1 Design of learning control board (M12-M24)
• T3.1.a Design of an electronic control board based on FPGA :
Based on our patented learning methods [IEF11] and on the electrical characterization results
of T4.1, we will specify and design the analog part of the control board. This module would
be dedicated mainly to adapt the voltage between the binary levels of the controller (FPGA)
and the reading and programming pulses send to or received from the memristor array. The
interface module will be a printed circuit board with discrete components. Nevertheless,
particular attention will be paid to the compatibility of the design with an integrated
implementation.
There is no high risk associated with this task as this PCB is principally made of standard
components (voltage regulators, analog switches, operational amplifier, current to voltage
converters,...). The main difficulty consists in protecting the memristor array from
electrostatic discharge and manages low current with low noise and well-controlled offset.
• T3.1.b Realization of the FPGA based control circuit :
In this task, we will realize the interface board and program the FPGA using a hardware
description language. We rely on the FPGA to be the main controller of the system as a
digital control would certainly minimize the global overhead for learning in an integrated
implementation. On contrary, the function of neurons, including the local computation of
the output error and the connection to the appropriate learning pulse, will be performed
locally with the architecture and the method described in [23]. As this method is completely
new and risky we shall provide an alternative method based on a neuron without
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memristors to be able to test the learning of the synaptic crossbar even in the case of failure
of neuron-based memristors.
T3.2 Final demonstrator fabrication and characterization (M18-36)
This task represents the global aggregation of the building blocks of a full functional circuit.
The best performing type of memristor array will be connected to the interface board. The
most efficient learning algorithm, tested on the basis of the memristor models, will be
implemented in the control board. Electrical characterization will demonstrate multiple
functions learning through the physical reconfiguration of the memristor array.
Risk management: If memristors can only be used as binary switch (without intermediate
conductance state) continuous synapses will be emulated with parallel set of binary
memristors.
CONTRIBUTION FROM PARTNERS
IEF
DESIGN OF THE ELECTRONIC CONTROL BOARD AND FPGA CONTROLER.
CEA
PACKAGING AND INTEGRATION OF MEMRISTOR ARRAYS TO BE MOUNTED ON THE CONTROL BOARD.
IMS
ELECTRICAL CARACTERISATION OF MEMRISTOR ARRAYS
3.3.4 TASK 4. PERFORMANCE ANALYSIS
TASK N° 4
DURATION
33 MONTHS
LEADER
PARTNERS
RESOURCES ( H.MOIS )
START
T0+3
TOTAL
HXM
47
CRISTELL MANEUX, IMS
UPS-IEF
CEA-IRAMIS
IMS
9
6
32
• OBJECTIVES:
Based on characterization, this task aims to identify by modeling, calculation and simulation,
the perspectives of organic memristor crossbars in terms of scalability, performances and
power consumption.
• WORK DESCRIPTION:
T4.1. Electrical characterizations (M3-M24)
• 4.1.A. Electrical characterization of individual organic memristors: We will perform full
static and dynamic electric characterization measurements to evaluate in particular: (i) the
current levels and their relation with area and thickness of the active part, (ii) the thresholds
for programming and their relation with molecule type, film morphology and film thickness,
(iii) the stability and robustness. These characterizations will be performed in a controlled
environment (vacuum or controlled atmosphere) so as to evaluate the impact of water and
oxygen (notably on aging). Fine electrical characterization will be performed as a function of
temperature to discriminate between physical mechanisms. Dispersion in performances will
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also be characterized since one of the main reasons for targeting adaptive architectures is to
become tolerant to variability at the device level.
• 4.1.B. Electrical characterization of assemblies of coupled memristors: One of the
drawbacks of crossbars of 2-terminal resistive devices concerns the sneak-path issues, i.e. the
possible existence of parasitic current pathways through multiple junctions when measuring
one particular device. Crosstalk could also be present in large arrays in the form of
unwanted modification of neighboring devices during the programming of a targeted
device. This task will evaluate issues related to the interactions between devices in arrays.
Characterizations of increasing difficulties will be performed from simple DC ones to more
demanding low temperature and frequency dependent ones.
T4.2. Compact model of organic-memristor (M3-M24)
A compact model is defined by an equivalent circuit in which each element is accurately
described as a function of several variables. Useful compact models describe the
characteristics of a device as a function of bias, temperature, frequency, structure, and
process variability in a computationally efficient, numerically stable and accurate way. These
stringent requirements can only be met through a physics-based modeling strategy as
opposed to curve fitting models. This sub-task aims at implementing into circuit simulators,
compact models of organic-memristors which will accurately predict their behavior at the
circuit level. The results of this sub-task will be used in the sub-task 4.3.A.
• 4.2.A. Behavioral modeling of organo-memristor: The 2008 HP Nature paper [2] is
the most significant result demonstrating a memristor compact model. It describes the
microscopic nature of resistance switching and charge transport in the memristor assuming
that the hysteresis requires some atomic (or molecular) rearrangement that modulates the
current. This compact model has the advantage to be scalable and, thus will serve as a
starting point within MOOREA, notably useful for an early start of sub-task 4.3.
• 4.2.B. Physics-based modeling of organic memristor: For the organic complexes
used in the project, important information on the mechanism will come from sub-task 4.1.
Complementary results from the literature will also provide additional insight on the specific
laws of transport/mobility and switching within the organic materials [32]. The final
objective is to describe the steady states as well as the hysteretic switching. Intrinsic changes
of conductivity of the grafted film will be considered as well as the drift of charged
molecular species [33-37]. The role of the internal thermal resistance has also been pointed
out as a key parameter for the switching mechanism [38].
• 4.2.C. Parameter extraction of organic memristor models: IMS will handle the
parameter extraction of the memristor models for both the behavioral organic memristor
model (BOM model) and for the Physics-based organic memristor model (POM model). The
parameter extraction will be performed using the results of sub-task 4.1. For the parameter
extractions, special care will be taken on the technological dispersion: if relevant and/or
possible statistical equations will be implemented in the model to enable circuit designers to
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evaluate the impact of the dispersion on their circuits and possibly the tolerance of the
learning methods to this statistical spread. Two different approaches will be carried out:
typical worst-case models and full Monte-Carlo statistical models. IMS will deliver these
model libraries to IEF for sub-task 4.3.
Task 4.2. is conceived to minimize the global task risk since the simplest version of a
behavioral model could be a curve fitting based model. Sub-task 4.2.B is a very challenging /
high risk (and thus high added value) task. It is balanced by the presence of Sub-task 4.2.A as
back-up option.
T4.3. Learning circuit design, simulation and benchmarking (M18-M36)
4.3.A. Circuit design and simulation of learning functions based on organic
memristor crossbar: Starting from compact models developed in the task T4.2 and learning
methods patented [IEF11] or submitted [23], we will design the circuits to perform
supervised learning. The objective of this task is to demonstrate by simulation the efficiency
of the proposed learning methods and the consistency of the simulations with the actual
behavior observed in the task T3 and T4.1. The need for inhibitory synapses (negative
weight) leads to consider differential architectures of synaptic arrays. Moreover, to
implement the neurons we shall consider initially a conventional CMOS circuit (see fig. 4 in
[IEF11]), that we will finally replace by a memristor-based neuron circuit ( see fig. 4 of this
document) operating memristor as conditional switches as demonstrated (in another context)
by [24].
4.3.B. Performance analysis: In this task, we will study the ultimate performance of
neural architecture based on physical compact models corresponding to nanoscopic devices,
like memristor build at the junction of carbon nanotubes. First we shall make sure it will
continue to be effective to perform a learning application. Then simulations will quantify the
ultimate performance that can be achieved with this technology including speed, power
consumption and tolerance to dispersion. Comparisons will be made with different neural
cells architectures validated in task 4.3.a.
4.3.C. Benchmarking : Based on comparisons with others devices and/or architecture a
precise benchmarking of our achievements will be performed at several levels:
- individual devices: performances in terms of speed, scalability, robustness, stability
- arrays of coupled devices: density of integration, complexity, programmability
- device models: accuracy, computational efficiency
- architectures: originality (in the intellectual property context), capacity to address relevant
problems, expected power consumption
- demonstrator: comparison with the most complex circuits from other groups worldwide
This work will notably be helpful for the evaluation of the project. We will propose figures of
merit to compare MOOREA’s outcomes within the international competitive context.
Risk management: If no physic-based compact model of organic memristor is usable for
circuit design, a behavioral model will be delivered.
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CONTRIBUTION FROM PARTNERS
IEF
DESIGN AND SIMULATION OF LEARNING CIRCUIT.
CEA
CHARACTERISATION OF MEMRISTORS
IMS
MEMRISTOR MODELING AND INTEGRATION IN CIRCUIT. PERFORMANCE ANALYSIS AND COMPARISON.
3.4. TASKS SCHEDULE, DELIVERABLES AND MILESTONES
DELIVERABLES
N°
DATES
D1.1
T0+1
D1.2
T0+3
D1.3
T0+12
D1.3
T0+12
D1.3
T0+24
D1.4
T0+26
D2.1
T0+3
D2.2
T0+6
D2.3
D2.4
T0+12
T0+9
D2.5
D3.1
T0+18
T0+24
D3.2
T0+36
D4.1
D4.2
D4.2
D4.3
T0+18
T0+24
T0+24
T0+36
DESCRIPTION
MINUTES OF THE KICKOFF MEETING
WEB SITE
DELIVERY OF THE CONSORTIUM AGREEMENT
ANNUAL REPORT
ANNUAL REPORT
FINAL REPORT
GRAM SCALE SYNTHESIS OF MEMRISTIVE IRON COMPLEX.
METALLIC ELECTRODES FUNCTIONALIZED WITH DENSE IRON COMPLEXES FILMS OF ADJUSTED
THICKNESSES AND MORPHOLOGY.
SYNTHESIS OF NEW REDOX COMPLEXES WITH IMPROVED PROPERTIES.
SOFT DEPOSITION OF MICROMETER SIZE (1-5 M IN WIDTH) ELECTRODES.
NANO-CONTACT PRINTING OF SUB-100 NM WIDE CROSSBAR ELECTRODES
SPECIFICATION AND REALIZATION OF AN ELECTRONIC CONTROL BOARD. DESCRIPTION OF THE
FPGA CONFIGURATION (HARDWARE DESCRIPTION LANGUAGE).
DEMONSTRATOR OF A FULL CIRCUIT COMPRISING AN ARRAY OF MEMRISTORS AND A CONTROL
CIRCUIT FOR FUNCTION LEARNING.
REPORT ON ELECTRICAL CHARACTERIZATIONS
REPORT ON COMPACT MODELING ORGANO-MEMRISTOR
TRANSFER OF ORGANO-MEMRISTOR MODEL TO CIRCUIT DESIGNERS TEAM
REPORT ON LEARNING ORGANO-MEMRISTOR-BASED CIRCUIT AND BENCHMARKING
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4. DISSEMINATION AND EXPLOITATION OF RESULTS. INTELLECTUAL
PROPERTY
4.1. DISSEMINATION COMMUNICATION IN THE SCIENTIFIC COMMUNITY
MOOREA is an ambitious project for which we expect outcomes of the first order that we
will communicate to the scientific community by the usual channel of publications and
conferences. The highlight results and the corresponding list of publications will be
published on the MOOREA website.
4.2. COMMUNICATION BEYOND THE SCIENTIFIC COMMUNITY
In addition, through the use of emerging technologies and neuronal inspiration Moorea
covers an exciting topic for general audience. The stakes are accessible to non-specialists.
Consequently, it may help to attract future students to scientific careers. We will
communicate on this project for the general public. We shall post on our website short video,
didactic materials and animations. The support of the communication service of the
University Paris-Sud SCAVO (www.scavo.u-psud.fr/) will be required for this purpose and
we have provisioned the necessary funding for it (see 6.1). In addition, the highlights will be
the subject of press releases based on communications services of our institutions.
4.3. INDUSTRIAL DEVELOPPEMENT
The field of applications of the project is extremely promising so that it may result in real
financial impact. As a typical example, the development of a new compact model constitutes
a very valuable result on both the scientific and the economical levels. One can also cite new
process flow for crossbar of memristors, new learning rules for nano-devices, etc.
The integration of new devices featuring behavior very different from that of the transistors
(switching abruptly with hysteresis and strong non-linearity,…) will lead to the development
of new methodologies for characterization and modeling that constitute future challenges of
instrumentation industry and CAD tools developer. We will be proactive in identifying with
industrial partners (e.g. Cadence, Mentors graphics, Agilent…) from the methodological
advances of the project MOOREA those that may be subject to an industrial development.
4.4. INTELLECTUAL PROPERTY
Most of the participants have already a considerable background in the different fields.
Therefore, it appears of paramount importance that each participant is able:
- to valorise its background through the results of the project,
- to identify contractually its background,
- to benefit of the generated intellectual property (foreground) for any future
development beyond the project.
The regulation of the intellectual property will be based on the following usual principles:
1) Each partner retains the ownership of his own knowledge.
2) Obtained results during the project belong to the partner that is at its origin.
3) Condominium patents will be a co-ownership agreement determining the rights and
obligations of each co-owner.
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4) Any project or publication of scientific results should be subject to the prior consent of
other partners.
5) The specific knowledge of a partner and its results may be used freely by the other
partners for the project if the knowledge and results are required to carry out their duties.
6) After the end of the project and for a period of 18 months, a non-exclusive right to exploit
the results of any other partner, and possibly on his own knowledge, if they are necessary for
using the results of a partner, may be granted on preferential terms and/or market, at his
request.
As stated in Part 4.2, all aspects related to the management of intellectual property will be
settled in a Consortium Agreement which will be signed at the earliest.
5. CONSORTIUM DESCRIPTION
5.1. PARTNERS DESCRIPTION & RELEVANCE, COMPLEMENTARITY
The consortium is composed of the 3 following partners:
1. IEF (Nanoarchitecture group of the department Nanoelectronics), Orsay.
2. CEA-Iramis (Institut Rayonnement Matière de Saclay) from which 2 groups will be
involved: the Laboratoire d’Electronique Moléculaire (LEM) and the Laboratoire de
Chimie des Surfaces et Interfaces (LCSI).
3. IMS (Laboratoire d’Intégration du Matériau au Système), Bordeaux.
These 3 partners have advanced expertise in the fields of importance for MOOREA and bring
to the consortium complementary type of knowhow, the details of which are presented in
the description of the laboratories activity below. This expertise covers fields from device
physics, nano-fabrication, chemistry, device modeling and circuit design up to system
architectures. Since the coordination of the ACI-Nanosys “Architectures pour l'intégration
des nanocomposants” (E. Belhaire, 2006-2008, >12 partners) and within the ANR Panini
(2008-2010), the Nanoarchi group of IEF has developed strong collaborations with IMSBordeaux in the field of nanodevice compact modeling and circuit design, and with CEAIramis in the field of neuro-inspired circuit architectures based on nanodevices. This fruitful
collaboration [LEM5] bridging nanodevices physics to circuit architecture and having the
capacity to go all the way to functional demonstrators of circuits with learning capabilities is
extremely rare in France.
1. IEF : The Architecture for Nanoelectronics group of the department Nanoelectronics in the
IEF lab is specialized in the integration of future nanodevices in System on Chip and
integrated circuits. After a long experience on the mixed analog/digital integrated circuits
namely image sensors, neural based pattern recognition circuits and artificial retinas, the
group is currently attached to the NanoSpinTronic department where it study the integration
of nanodevices, either magnetic (MRAM) or non-magnetic (CNT, RRAM), in future
integrated systems, notably in neuro-inspired circuits. Pr. Jacques-Olivier Klein, the group
leader, was the coordinator of the PANINI project (Programme Architecture
Nanoélectronique Intégrée Neuro-Inspirée) whose goal was to demonstrate the potential of
neuro-inspired approach for nanocomponent based on real word (non-ideal) characteristics.
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2. CEA-Iramis: involves 2 groups from the IRAMIS Institute (CEA Saclay):
- CEA-Iramis LEM: The Laboratoire d’Electronique Moléculaire is a research group of
14 members lead by V. Derycke. It belongs to the Service de Physique de l'Etat Condensé
(SPEC). Its activity focuses on (i) the understanding of the transport properties of nanoobjects, (ii) the study of chemistry of nano-objects, and self-assembly processes, (iii) the
development and study of nanoscale devices (in particular HF transistors, optoelectronic
memory devices and NEMS ) and (iv) the study of future circuit architectures based on nanodevices. The LEM's expertise, which is directly relevant for the MOOREA project includes:
organic/molecular electronics, physics of nano-devices and circuits. For some representative
publications, see: [LEM1-5].
- CEA-Iramis LCSI: The Chemistry of Surfaces and Interfaces Lab (LCSI) is a 20
member group (10 permanents) which belongs to the Service de Physique et Chimie des
Surface et Interfaces (SPCSI). It studies organic-inorganic interfaces, and more particularly
the controlled surface functionalization of metals, semiconductors and insulating materials.
Several functionalization processes leading to covalently grafted coatings on these materials
were developed. LCSI is also involved in applying these grafted coatings to different
domains such as depollution, metal deposition for microelectronics, biocompatible surfaces,
electrocatalytic materials, nano-objects engineering, hybrid-photovoltaic and molecular
electronics. For MOOREA, the LCSI has advanced skills (i) in the synthesis of the diazonium
salts of metal complexes (ii) in electrochemistry and electrochemical grafting respectively
used in the project to determine the redox properties of the memory active compounds and
modify conducting electrodes. (iii) in micro-contact printing for the soft deposition of the top
electrodes. For some representative publications, see: [SPCSI1-6].
3. IMS: MOOREA will take benefit of skills and expertise of the ’’electrical characterisation
and compact modeling’’ team. The IMS MODEL team has a 15 years experience in device
modeling. The two aspects, advanced device research and industrial application are driven
in parallel. Today, the compact modeling and device characterisation activities are one of the
two pillars of the “laboratoire commun ST-IXL” founded in 2003. Since 2005, the activities of
the team move towards advanced nanoscale devices and especially to Carbon Nanotube
Field Effect Transistor (CNTFET). In2012, within MOOREA research project, the MODEL
team will develop the first compact model of the advanced organic nanoscale memristor in
Verilog-A to design new generation of ICs.
5.2. QUALIFICATION OF THE PROJECT COORDINATOR
Jacques-Olivier Klein (M’90) received the Ph.D. degree and the Habilitation in electronic
engineering from Université Paris-Sud, Orsay, France, in 1995 and 2009 respectively. He is
currently Full Professor in Institut d'Electronique Fondamentale, in charge of the
"NanoArchi" research group focused on architecture of circuits and systems based on
emerging nanocomponents in the field of nanomagnetism and bio-inspired
nanonoelectronics. He teaches embedded system design in Institut Universitaire de
Technologie de Cachan.
J.O. Klein is author of 70+ technical papers including 7 invited communications. He served
on the program Committee of conferences DTIS 2010-2011 and GLSVLSI 2010-2011, he
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served as reviewer for International Journal of Reconfigurable Computing, IEEE
Transactions on Magnetics, Solid State Electronics and conferences DCIS-2007-2008-2010,
ISCAS 2004-2011. Since 2008, J.O. Klein animates with C. Maneux the topic “emerging
technologies” in CNRS GDR SOC SIP and organized many workshops in this context.
The proposed coordinator already collaborated with most partners and benefits from the
confidence of the consortium. He notably coordinated the ANR-ARFU project PANINI
(2008-2010) that constitutes the premise of MOOREA.
5.3. QUALIFICATION AND CONTRIBUTION OF EACH PARTNER
Partner
Name
First name
Position
Field of research
PM
Contribution to the project
4 lignes max
IEF
KLEIN
JacquesOlivier
Professeur
des
universités
Signal processing,
architectures for
nano-components
16
IEF
ZHAO
Weisheng
Chargé de
recherché
CNRS
Electrical
engineering, hybrid
design
4
Design and electrical simulation of learning
circuits, benchmarking.
IEF
QUERLIOZ
Damien
Chargé de
recherché
CNRS
Device physics and
model, unsupervised
learning
8
Design and electrical simulation of
lunsupervised earning circuits,
benchmarking.
IEF
To be hired
Post-doc
Neural processing
and digital circuits
18
Design of learning circuits, design of the
FPGA for the control board.
CEA-Iramis
(LEM)
DERYCKE
Vincent
Chercheur
CEA
Physics,
nanoelectronics
12
Design of memristor devices, Micro-nano
fabrication of memristor devices and
circuits, Electrical characterization, Device
physics
CEA-Iramis
(LCSI)
JOUSSELME
Bruno
Chercheur
CEA
Chemistry
7.2
Molecule synthesis and characterization,
grafting, electrochemistry
CEA-Iramis
(LEM)
DAVID
Thomas
Technicien
Clean-room process
6
Clean-room process and maintenance
CEA-Iramis
(LCSI)
DEBOU
Nabila
Technicienn
e
Chemistry
4.8
Molecule synthesis and characterization
CEA-IRAMIS
(LEM)
CABARET
Théo
Thésard
NON
financé par
l'ANR
Physics
18
Micro-nano fabrication of memristor
devices and circuits, Electrical
characterization, Device physics
CEA-Iramis
(LCSI)
To be hired
postdoc
Chemistry
18
Micro-contact printing, grafting,
electrochemistry.
IMS
MANEUX
Cristell
Maître de
conférences
Electronic
Engineering
9
Compact modeling
IMS
MARC
François
Maître de
conférences
Electronic
Engineering
6
Compact modeling
IMS
HAINAUT
Cyril
Technicien
Electrical
Measurement
4
Electrical measurements
IMS
DEVREESE
Régis
Ingénieur
informatique
Software System
manager
4
Computing resources
18
Design, electrical simulation and
realization of learning circuits,
benchmarking
COORDINATEUR
Learning method, design of learning
circuits.
Compact modeling
IMS
To be hired
Post Doc
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5.4. IMPLICATION OF PARTNERS IN OTHER PROJECTS
Name
PM
Project name, financing
institution, grant allocated
Project title
Coordinator
name
Start and end
dates
1
V. Derycke
9
ANR Arfu
Panini
J-O. Klein
2008-2010
2
V. Derycke
10
FP7-Nano-ICT
NABAB
C.Gamrat
2008-2010
3
T. Cabaret
36
Thèse C'Nano
Cinamon
V. Derycke
2011-2014
4
B. Jousselme
14.4
Blanc 2011
Sage III-V
B. Jousselme
01/2012-12/2014
5
B. Jousselme
7.2
Pan’H 2008
Enzhyd
P. Chenevier
01/2009-12/2012
6
N. Debou
6
Blanc 2011
Sage III-V
B. Jousselme
01/2012-12/2014
7
N. Debou
6
Pan’H 2008
Enzhyd
P. Chenevier
01/2009-12/2012
8
J.O.KLein
18
ANR Arfu
Panini
J-O. Klein
2008-2010
9
J.O.KLein
3.5
ANR Nano-Innov RT
SPIN
C. Chappert
2009-2011
10
J.O.KLein
3
FP7 FET
MAGWIRE
D. Ravelosona
2009-2011
11
J.O.KLein
9
ANR-INS
MARS
L. Torres
2011-2014
12
C.Maneux
16.2
ANR Arfu
Panini
J-O. Klein
2008-2010
13
C.Maneux
20
ANR VERSO
ROBUST
C.Maneux
2009-2012
14
F. Marc
10
ANR VERSO
ROBUST
C.Maneux
2009-2012
15
C.Maneux
15
ANR ARPEGE
Nanograin
F. Clermidy
2009-2011
16
Weisheng Zhao
6
FP7 FET
MAGWIRE
D. Ravelosona
2010-2013
17
Weisheng Zhao
9
ANR-INS
MARS
L. Torres
2011-2014
18
Weisheng Zhao
9
ANR Nano-Innov RT
SPIN
C. Chappert
2009-2011
19
Weisheng Zhao
6
ANR-PNANO
CILOMAG
C. Chappert
2007-2010
6. SCIENTIFIC JUSTIFICATION OF REQUESTED RESSOURCES
The majority of resources will be devoted to the recruitment of three post-doctoral students
whose contributions are detailed in the following section. In addition, CEA-LEM and IEF cosupervised the work of a PhD student funded by the Région Ile-de-France. He will work
until T21 on organic memristors. This non-ANR funded hxm are important to fulfill the
proposed ambitious objectives while keeping the overall budget low.
6.1. PARTNER 1 : IEF: 124.28 K€
Equipment: 12 k€
- 1 Workstation will be required for CAD tools (notably cadence-Spectre) for analog
simulation to simulate the learning methods and to estimate the ultimate
performances of memristor based architectures (5k€). In addition a mixed signal
oscilloscope (7k€) will be used firstly to debug the control board and the FPGA
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controller, secondly to analyse the result during the learning stage of the final
demonstrator.
Personnel costs : 73.8k€
Postdoc, 18 months. We shall recruit for 18 months a post-doc with a good skill in
electrical engineering, signal processing and digital circuits design to design,
implement and operate the control board and its FPGA controller.
Travel : 9.5k€
10 meetings and travels in France (2k€), 3 international conferences (7.5k€).
Other working costs : 24.2k€
Simulation CAD (Cadence / Euro-practice, 3 years x 2.5k€ /year), PCB CAD licence
(2k€), PCB Manufacturing of the control board (0.3k€), electronic components and
devices, including the FPGA Board (2.4€), payment of student internship (2 x 5
months x 0.5k€/month), laptop (2k€), office software licences (1k€), Communication
to a non-specialist public (4k€).
Management fees (4%) : 4.78 k€
6.2. PARTNER 2 : CEA-IRAMIS 169.7K€
Equipment : 12 k€
LCSI: Upgrade of the glove-box based electro-functionalization setup
Personnel costs: 86206 €
Post-doc 18 months, mainly in charge of the development of high resolution
µCP and electrochemical grafting of organic complexes.
Travel : 6k€
Expenses for inward billing : 25 k€
- Clean room facility costs (3 years x 8k€/year)
- Iramis broad-audience communication material 1k€
Other working costs : 34 k€
- Chemical products, reactants, solvents, catalysts, electrolytes, gases (12 k€)
- Maintenance and consumable parts of characterization equipments (AFM, MEB, IR,
UV-Vis, chromatography, Electrochemistry, glove-box) (15 k€)
- Characterization of molecules (Mass spectroscopy, elemental analysis) (1.5 k€)
- Electrochemical cells, specific glassware (1.5 k€)
- Removal and reprocessing of chemical wastes (1k€)
- Measurements associated costs (probes, AFM tips, Helium…) (3k€)
Management fees (4%) : 6.5k€
6.3. PARTNER 3 : IMS : 110.24 K€
Equipment : 11k€
- The required funds will make possible to finance: Upgrade of the ICCAP software
11k€
Personnel costs: 75k€
- Post-doc 18 months. This person will have to deal with the compact model of
organic memristor. The numerical implementation will be done with ICCAP software
integrating the Verilog-A framework. She or he will help to develop compact models
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for organo-memristor in Verilog-A language, to contribute to the learning circuit
design with IEF, and to the benchmarking. Obviously, she or he would have strong
interest in interdisciplinary researches.
Travel : 6K€
Other working costs : 14k€
- Participation to the maintenance of electrical characterization equipments (network
analyser, parameter analyser) (11 k€)
- Measurements associated costs (TTP6 probes, etc.) (3k€)
7. REFERENCES
7.1. REFERENCES
[1] Emerging Research Devices, 2009 Edition. International technology roadmap for
semiconductors (ITRS).
[2] D. B. Strukov, et al. Nature 453, 80 (2008).
[3] http://www.nabab-ict.org/
[4] http://www.anr-panini.u-psud.fr
[5] K. Seo, et al. Nanotechnology 22, 254023 (2011).
[6] T. Ohno, et al. Nature Materials 10, 591 (2011).
[7] S. H. Jo, et al. Nano Letters 10, 1297 (2010).
[8] F. Alibart, et al. Adv. Funct. Mater. 20, 330 (2010).
[9] Y. V. Pershin, et al. Neural Networks 23, 881 (2010).
[10] Song, et al. Adv. Mat. 22, 5048 (2010).
[11] Q.-D. Ling, et al. Progress in Polymer Science 33, 917 (2008).
[12] Heremans, et al. Chem. Mater. 23, 341 (2011).
[13] Q. Ling, et al. Adv. Mater. 17, 455 (2005).
[14] You, et al. Macromolecules 42, 4456 (2009).
[15] A.R. Brown, et al. Synthetic Metals 68, 65 (1994).
[16] H.L. Kwok, et al. Appl. Phys. B 94, 279 (2009).
[17] V. Kazukauskas, et al. Eur. Phys. J. Appl. Phys. 37, 247 (2007).
[18] M. Fadlallah, et al. JAP 99, 104504 (2006).
[19] M. Fadlallah, et al. Solid-State Electronics 51, 1047 (2007).
[20] R. R. Schliewe, et al. APL 88, 233514 (2006).
[21] V. Vaidya, et al. IEEE TED, 56, 1 (2009).
[22] A. Raychowdhury, et al. IEEE Tr. CAD of Int. Circ. & Syst. 25, 58 (2006).
[23] J-O. Klein, et al. Submitted to IEEE TNANO.
[24] Kuekes, et al. J. Appl. Phys. 97, 034301 (2005).
[25] K. Seo, et al. Chem. Mater. 19, 7617 (2009).
[26] J. Lee, et al. Angew. Chem.-Int. Edit. 48, 8501 (2009).
[27] Pradhan, B. et al. Chem. Mat. 20, 1209 (2008).
[28] J. Pinson, et al. Chem. Soc. Rev. 34, 429 (2005).
[29] J. L. Bahr, et al. J. Am. Chem. Soc. 123, 6536 (2001).
[30] J. Charlier, et al. ChemPhysChem 6, 70 (2005).
[31] K. Balasubramanian, et al. Nano Lett. 2, 827 (2004).
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[32] J. Lee, et al. Angew. Chem. Int. Ed. 48, 8501 (2009) and associated supporting
information.
[33] J. C Scott, et al. Adv. Mater. 19, 1452 (2007).
[34] C. P Collier, et al. Science 289, 1172 (2000).
[35] N. B. Zhitenev, et al. Nature Nanotechnol. 2, 237 (2007).
[36] J. H. A Smits, et al. , Adv. Mater. 17, 1169 (2005).
[37] Q. X. Lai, et al. Appl. Phys. Lett. 88, 133515 (2006).
[38]. J. Borghetti, et al. , J. Apl. Phys. 106, 124504, (2009).
7.2. REFERENCES OF THE CONSORTIUM MEMBERS
[IEF1] H. Pujol, et al. MicroNeuro94, 26-28 Sept. 1994, Italie, pp. 449—455.
[IEF2] J.-O. Klein et al. Electronics-Letters. 8 June 1995; 31(12): 986-988
[IEF3] J.-O. Klein et al. Traitement-du-Signal. 1999; 16(5): 361-370
[IEF4] M. Hé et al. IEEE Nanotechnology, Cincinnati, Ohio (USA)17-20 july, 2006.
[IEF5] M. He et al. IEEE Nanotechnology, Hong-Kong, August 2-5, 2007.
[IEF6] M. HE et al Electronics letters Vol. 44, N°9 p. 575-576, 2008.
[IEF7] M. He et al. IEEE DTIS 2008, 25-28 Mars 2008, Tozeur (Tunisie), Pages: 1 - 5, 2008.
[IEF8] J-O. Klein, E. Belhaire PCT/FR2008/051389.
[IEF9] D Chabi, J.O. Klein, IEEE DTIS 2010, . Hammamet (Tunisia), 23-25 march 2010.
[IEF10] J.M. Retrouvey, IEEE DTIS 2010, Hammamet (Tunisia), 23-25 march 2010.
[IEF11] J. J-O. Klein, E. Belhaire “IB2009053528 WO Patent WO/2010/133,925, 2010.
[LEM1] V. Derycke et al, C. R. Phys. 10, 330 (2009).
[LEM2] D. Dulic et al, Angew. Chem. Int. Ed. 48, 8273 (2009)
[LEM3] Anghel at al, Nano Letters 8, 3619 (2008).
[LEM4] Agnus et al, Small 6, 2659 (2010) and Adv. Mater. 22, 702 (2010).
[LEM5] Liao et al, IEEE Trans. Circ. Syst. 58, 2172 (2011).
[LCSI1] D. Aldakov et al, ACS Appl. Mater. & Interfaces. 3, 740 (2011).
[LCSI2] F. Grisotto et al, Chem. Mater. 23, 1396 (2011).
[LCSI3] A. Le Goff et al, J. Electroanal. Chem. 641, 57 (2010).
[LCSI4] A. Le Goff et al, Science 326, 1384, (2009).
[LCSI5] D. K. Aswal et al, Physica E, 41, 325 (2009).
[LCSI6] B. Jousselme et al, J. Electroanal. Chem. 621, 277 (2008).
[IMS1] C. Maneux et al, Solid-State Electronics, 49, 956 (2005).
[IMS2] S. Fregonese et al, IEEE TED 53, 296 (2006).
[IMS3] C. Maneux et al, IEEE DTIS Tunis, 4-7 Septembre 2006.
[IMS4] C. Adessi et al, Compte Rendu de Physique 10, 305319 (2009).
[IMS5] S. Fregonese S et al, IEEE TED 56, 1184 (2009).
[IMS6] C. Bestory, Microelectronics Reliability 49, 946 (2009).
[IMS7] S. Fregonese S et al, IEEE TED 56, 2224 (2009).
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