I
Abstract
Digital Lock-in Amplifier design characteristics:
Dev. Board: FPGA, Spartan 3E (XC3S500)
Language: VHDL (VHSIC Hardware Description Language). No Picoblaze
assembler code use and transition complexity.
Onboard chips and components used: - LTC 6912 Inverting amplifier, LTC
1407A Analog to Digital Converter, built-in LCD display
Processing core: Lock-in amplifier
External chips and components: AD620 Inst amplifier, passives: axial
resistors.
FPGA based design of Lock-in amplifier was implemented on Spartan 3E
(XC3S500) development board. To make it possible to reconstruct suggested design,
Master Thesis is done by way of highly detailed explanation parts. It consist of 4 main
chapters: Literature review – revision of some previously done work that resembles
similar concepts, Digital Interface, Digital Design, Analog Design (In addition,
AD630 modulator/demodulator based Analog-to-digital Lock-in Amplifier prototype
was implemented).
All Digital implementation of Phase Locked Loop (ADPLL) allows
simplifying of frequency tracking mechanism from phase sensitive detection to direct
frequency extraction from input signal. This simplification was discussed and
exploited in the design. Limitations here are sampling rate resolution of analog
signals. Bitwise division algorithm starts consuming increasing space percentage
when bit length of clock counter - used to estimate period of input signal - exceeds
second decade. Eventually, recovered/extracted frequency signal was connected
through feedback to ADC (analog to digital converter) and was used there to adjust
sampling rate which in turn decreased or increased counter limit.
Exponential Moving Average and Simple Periodic Average algorithms were
both deployed for Low Pass Filter and related parallel Lock-in amplifier
implementations were compared for better performance.
I
II
Acknowledgements
First of all, I want to express my gratitude and say great thanks to my main
supervisor, James Green. I met him only this year and he turned out to be great
person. I wish there were more people like him... He gave me freedom that I needed
and never pushed me to do something in the way that he saw it. Instead he gave me
theoretical and practical advices allowing me to gain my own experience, and most
importantly he believed in me, even when I did not. He was always there when urgent
help was needed and solutions that he gave me were often most practical ones.
Secondly, I want to say big thanks to my second supervisor, Neil Powell. He
also motivated me, but in different way. He challenged me when said that I will not be
able to do both designs in time left. He was very concerned by the progress of my
work, which I highly appreciate.
I also want to admire Xilinx forum, which I literally terrorized during search
for available solutions. I learned a lot from there and from VHDL examples available
on the Internet. Especially I want to say thanks and sorry to Ken Chapman from
whom I persistently demanded KCSPCM3.exe file.
I want to say thank you to all EEE department and stuff. I never saw such
polite and helpful people before, who were willing to open doors of the project room
when I left keys there even at early morning.
And finally, I cannot finish not mentioning Nick, Alex, Anne and Sushma
with whom I was working and sitting side by side soldering and sharing ideas,
thoughts and knowledge. They are great people.
Thank you to all!
II
III
Contents
Abstract
Acknowledgements
Contents
Introduction
Chapter 1: Review of some previously done Lock-in amplifiers
1.1 Digital Lock-in Amplifier by Gaspar et al.
1.2 Microcontroller based Lock-in amplifier by Bengtsson
1.3 8 bit Microcontroller based Lock-in amplifier by Dorrington et al
Chapter 2: Digital Interface
2.1 Square root of 32 bit value
2.2 Binary into Binary Coded Decimal (BCD) conversion
2.3 Character display realization
2.4 Inverting amplifier and analog to digital converter
2.4.1
Amplifier gain setting
2.4.2
ADC conversion
2.4.3
ADC signals interpretations
Chapter 3: Digital Design of Lock-in amplifier
3.1 Zero Crossing Detector
3.2 Phase Locked Loop
3.2.1
Signal generator
3.2.1.1 Sine Look-Up table
3.2.1.2 Direct Digital Synthesis (DDS) block
3.2.2
Phase Sensitive Detector (PSD)
3.2.3
Loop Filter Question
3.3 Signed Multiplication block
3.4 Low Pass Filter
3.4.1
Low pass filter via Exponential smoothing
3.4.2
Low pass filter via Simple Periodic Average
3.5 Process of synthesizing and design optimisation
3.6 Simulation and testing
Chapter 4: Analog Design of Lock-in amplifier
Conclusion
References
Abstract I
Abstract II
Abstract III
I
II
III
1
4
4
5
6
8
8
9
10
12
13
15
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27
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31
31
33
34
36
42
51
52
53
54
55
III
IV
Department of Electronic & Electrical Engineering
MSc Project Receipt
University of Sheffield
Department of Electronic and Electrical Engineering
M.Sc. Dissertation Hand-in Form
Please complete all parts of this form and hand it in with two bound copies of your
dissertation to the Student Office (E133).
Name: Timur Ishuov
Reg.No: 130137155
Sheffield address:
Flat 46, Ventnor Court 25, Wostenholm Rd.
S7 1LB
Phone number: 07871591115
Date when expect to leave Sheffield: 26.09.2014
Address where you can be contacted after leaving Sheffield:
Flat 36, Kurmangazi 180/96
050009, Almaty, Republic of Kazakhstan
Phone number: +107 705 18 98 256
Course: Electrical and electronic engineering
Supervisor: James Green
Title of Dissertation: Building a Lock-in Amplifier
Date handed in: 01.09.2014
This portion must be date stamped and signed and retained by the receiving staff
member - proof that two full copies of the dissertation have been handed in.
---------------------------------------------------------------------------------------------------------------The student should retain this portion date stamped and signed as proof of handing in
two copies of the dissertation.
Name:
Reg. No:
Course:
Date of entry to course (month/year):
Title of Dissertation:
Date handed in:
IV
1
Introduction
Lock-in amplifier is used to retrieve low level signals in presence of obscuring noise.
And the way it does it is not related to conventional measurement. First, it is necessary to
understand main ideas.
When two arbitrary sine waves (with different frequencies and phases) are multiplied
with each other they produce a resulting signal that when averaged appears to be equal to
zero. This is explained by a orthogonal rule of sinusoidal signals. A ∙ sin(ω1 x + θ1 ) ∗ B ∙
1
2
1
2
sin(ω2 x + θ2 ) = (cos(ω1 x − ω2 x + θ1 − θ2 ) + cos(ω1 x + ω2 x + θ1 + θ2 ) = A ∙ B ∙
(cos α − cos β). There is no DC offset in this equation. A and B only affects amplitude of the
resulting signal:
Sine_2
1000
1000
0
0
-2000
-1000
-2000
Sine_1*Cosine_2
Sine_1*Sine_2
2000000
2000000
1000000
1000000
0
1
87
173
259
345
431
517
603
689
775
861
947
-1000000
0
-1000000
-2000000
1
104
207
310
413
516
619
722
825
928
-1000
1
87
173
259
345
431
517
603
689
775
861
947
2000
1
95
189
283
377
471
565
659
753
847
941
Sine_1
2000
-2000000
Figure Int.1. Arbitrary sine waves multiplication with zero average
Situation changes, when frequencies become equal to each other, i.e. 𝜔1 =
𝜔2 = 𝜔:
1
A ∙ sin(ωx + θ1 ) ∗ B ∙ sin(ωx + θ2 ) = 2 (cos(ωx − ωx + θ1 − θ2 ) −
1
cos(ωx + ωx + θ1 + θ2 ) = 2 A ∙ B ∙ (cos(θ1 − θ2 ) − cos(2ωx + θ1 + θ2 ))
1
2
𝐴 ∙ 𝐵 ∙ cos(𝜃1 − 𝜃2 ) - is DC offset, since cos(𝜃1 − 𝜃2 ) is some constant value
between 0 and 1.
1
2
Sine_2
Sine_1
2000
1000
-1000
1
104
207
310
413
516
619
722
825
928
0
1
95
189
283
377
471
565
659
753
847
941
1500
1000
500
0
-500
-1000
-1500
-2000
Sine_1*Sine_2
1500000
1500000
Sine_1*Cosine_2
1000000
1000000
500000
500000
0
-500000
1
104
207
310
413
516
619
722
825
928
-500000
1
95
189
283
377
471
565
659
753
847
941
0
Figure Int.2 Same frequency sine waves multiplication
Let us consider ideal sine wave signal as input signal and ideal sine wave
signal as reference signal with same known frequency. The result will be the same as
was the case with two same frequency sine waves multiplication besides given
amplitudes:
1
Vsignal ∙ sin(ωx + θ1 ) ∗ Vreference ∙ sin(ωx + θ2 ) = 2 Vsignal ∙ Vreference ∙
(cos(θ1 − θ2 ) − cos(2ωx + θ1 + θ2 )).
Lock-in amplifier, essentially, is simple modulator that multiplies two signals
(input signal and known reference) and averages obtained result, producing DC offset
as an output signal
1
V
2 signal
∙ cos(θ1 − θ2 ) proportional to the measured signal.
(Vreference or reference amplitude was omitted since it can be derived from reference
signal and result can be divided by it).
However produced DC offset has some error caused by cos(θ1 − θ2 ) value.
Dependence on (θ1 − θ2 ) can be avoided using multiplication by quadrature
(90 ) shifted reference or 𝑉reference ∙ cos(𝜔𝑥 + 𝜃2 ).
o
1
Vsignal ∙ sin(ωx + θ1 ) ∗ Vreference ∙ cos(ωx + θ2 ) = 2 Vsignal ∙ Vreference ∙
(sin(θ1 − θ2 ) + sin(2ωx + θ1 + θ2 )) =>
1
V
2 signal
∙ sin(θ1 − θ2 ) .
(It should be noticed that in practise Low Pass filter is often used for signal
averaging because it has ability to cut-off frequency containing components from the
intermediate result).
Finally, more precise value is estimated as:
2
3
1
1
1
Z = √(2 Vsignal ∙ cos(θ1 − θ2 ))2 + (2 Vsignal ∙ sin(θ1 − θ2 ))2 = 2 ∙ Vsignal ∙
1
√cos(θ1 − θ2 )2 + sin(θ1 − θ2 )2 = 2 ∙ Vsignal
Vsignal here is amplitude of the input signal, 0.707* Vsignal gives RMS value.
Last point to mention, real-life signal is not ideal sine wave, but contain
combination of sine and/or cosine waves (according to Fourier series), not to mention
prevailing noise when amplifying low level signals. Example below shows signal that
contains Sine_2 from the Figure Int.1 and some higher frequency/different phase sine
waves.
4000
Signal containing Sine_2
2000
-2000
1
80
159
238
317
396
475
554
633
712
791
870
949
0
4000000
3000000
2000000
1000000
-1000000
1
104
207
310
413
516
619
722
825
928
0
3000000
2000000
1000000
0
-1000000
-2000000
-3000000
1
104
207
310
413
516
619
722
825
928
-4000
Signal*Sine_2
Average
Figure Int.3 Vsignal retrieval process
Signal*Cosine_2
Average
An average of Signal and reference sine wave multiplication Xinit = 780104.9
An average of Signal and reference cosine wave multiplication Yinit = -420.967
Amplitude of reference voltage used Vref = 1250:
X=
Xinit
Vref
=
780104.9
1250
= 624.08 ;
Y=
Yinit
Vref
=
−420.967
1250
= −0.337
Z = √624.08 2 + 0.3372 = 624.084
Vsignal = 2 ∙ Z = 2 ∙ 624.084 = 1248.17
The result calculated in Excel is 1.83 less than 1250 of Sine_2 amplitude.
Digital design can suffer roughly from the same average value discrepancy, but
objectives for both analog and digital design are the same: multiply measured signal
by 2 quadrature shifted signals with given frequency that is same to which measure
signal is driven and derive amplitude (or RMS) value of original signal in the form of
DC offset.
3
4
Chapter 1: Review of some previously done Lock-in amplifiers
1.1 Digital Lock-in Amplifier by Gaspar et al.
Digital Lock-in Amplifier article that was presented by Gaspar et al. [1]
demonstrates top level of Lock-in amplifier, digital diagrams for Digital Phase
Locked Loop, Digitally Controlled Sine Wave Oscillator, Low Pass Filter etc:
*
DSP
DAC
sin
cos
External
System
X
Low Pass
Filter
ADC
Y
Low Pass
Filter
Figure 1.1 Basic digital lock-in amplifier scheme of Gaspar et al [1]
-
+
+
ka
+
+
+
z-1
sin
k1
cos
DCO
Accumulator
ka
+
+
Exponential Low
Pass Filter
+
+
+
+
z-1
sin
sin
cos
cos
z-1
Figure 1.2 Digital Phase Locked Loop by Gaspar et al [1]
integer
fractional
+1
AND
Interpolator
sin
Index2
Index 1
ω0
Iner
z-1
Figure 1.3 Digitally Controlled Oscillator (DCO) for sine wave generating by Gaspar et al [1]
4
5
K1
Input
signal
+
Accumulator for
Previous signals
output
+
K2
+
Z-1
Figure 1.4 Exponential Low Pass Filter Gaspar et al
Overall, the work provides essential examples of discrete units, and ideas behind them
can be used as possible solutions.
1.2 Microcontroller based Lock-in amplifier by Bengtsson
I/O 1
+Vdd
R0
R2
+
Rx
R3
ADC_in
-
R4
R1
I/O 2
Figure 1.5 .Simple digital lock-in amplifier that was introduced by Bengtsson [2]
Next interesting work is presented by Bengtsson [2]. Scheme with R2, R3, R4
interconnection is used after an instrumentation amplifier to change voltage limits
from {-10; 10} to {0; 5}. This limits suits analog input of the microcontroller. But to
return then to negative values, 512 (defined by digital representation) is subtracted
from the “converted” input value. This approach can be useful for converting analog
signals to suit voltage limits of input pins, and it also provides insight of processing
digital values in ADC (analog to digital converter).
Main principle in the Bengtsson solution [2] is to send sent 1 bit (which
correspond to 5V) periodically (each half cycle) through inputs 1 and 2. As result, this
affects voltage sign across resistor Rx when it passes through amplifier each half
cycle. This voltage after being amplified and converted is measured in
microcontroller’s input. And as Bengtsson states if then subtract positive part from
negative, signal will be increased, i.e. U(t1)-(-U(t2))=2U, whereas noise will be
discriminated[2]. Doing so for example for 500 time cycles and accumulating values
for voltage each time, we can then obtain average voltage, dividing accumulated sum
by 500. And this method exactly was used in his work.
5
6
V
+5V
+1
+1
t
+1
-1
-1
-1
Figure 1.6 Basic concept of phase sensitive detection (Bengttson 2012)
1.3 8 bit Microcontroller based Lock-in amplifier by Dorrington et al.
Even though Bengston published his work in 2012, the basic principles for it
were developed by Wang in 1990 [3] in his PC based approach of sensitive lock-in
measurements. Furthermore, calculating difference between two values of the signal
for each half cycle were criticized by Dorrington et al [4] for acceptance of low
frequency noise and for having limitations considering high frequency signals
applications.
Dorrington et al [4] proposed exploiting another side of the Wang’s work,
namely an advantage of increasing sampling frequency two times higher than the
reference signal frequency. He noted that, signal measurement each ½ period, makes
modulated signal to correspond to the Nyquist frequency1 of the reference signal. As
consequence, technique used in analog implementation of lock-in method can be
employed, that is “spectral inversion” of the signal after it was modified. If follow this
process by Low Pass Filter, then inverted noise component can be removed.
V
V
Low Pass Filter
f
f
Niquest frequency
Niquest frequency
a
b
Figure 1.7s a – noise level and modified signal spectrum representation, b – spectral inversion [4]
For ADC step, DDC112 unit was chosen since having 1 bit resolution which
supports sampling low level signals. Drawback is 2kHz maximum sampling rate and
“mismatched” capacitors [4].
1
Sampling twice as highest frequency harmonic of the original signal in the digitization process is a
minimal requirement to be able to recover all Fourier components. For more information see Kester
(2009).
6
7
Most interesting aspect in the design is that, filtering process is integrated with
“spectral inversion” process in 8 bit AT 89c8252 microcontroller.
Butterworth low-pass filter software realisation algorithm given in the report:
1
1
1
1
𝑦 = − 256 xn + 256 xn−1 + yn−1 − 256 yn−1 − 256 yn−1
and
1
1
1
1
𝑦 = 256 xn − 256 xn−1 + yn−1 − 256 yn−1 − 256 yn−1
Where y and xn are generated output and current input, yn-1 and xn-1 are
previous output and previous input respectively.
Filter coefficients are all 1/256, which has benefits when realizing on
microcontroller. To divide by 256 (28), one need to bitwise shift right numerator value
in memory.
7
8
Chapter 2: Digital Interface
Figure 2.1 Spartan 3E FPGA Developer Board
Digital Design of Lock-in amplifier consist of fully digital VHDL based
configuration of Lock-in amplifier built on Spartan 3E XC35C500 FPGA board, with
use of onboard LTC 6912 amplifier, LTC 1407A Analog to Digital convertor (ADC)
and built-in LCD display.
In order to provide Analog Lock-in amplifier with data processing
mechanism and to have ability to show signals on LCD display analog Lock-in
amplifier was connected to Spartan board through Bipolar to Unipolar voltage
conversion resistors (-15-+15 into 0.4..2.9. see Abstract II).
Since different VHDL cores can be used for common interface, basic
principles behind this interface will be explained first.
2.1 Square root of 32 bit value.
A finding square root process is based on algorithm proposed by [5]. It is
reasonably complex to grasp, but has extremely small hardware formation and
implements addition or subtraction between left and right parts (showed as 17..0 and
17..0 registers in ADD/SUB block in figure 2.2) based on sign value ‘1’ or ‘0’ (high
order bit, 17) of remainder R (remainder of addition or subtraction).
8
9
Figure 2.2 Square root producing process [5]
Left part is formed from 15 to 0 bits of Remainder R shifted left by 2 bits
(becoming 17 to 2 bits in the Left part) and 2 leftmost bits of INPUT D (square root of
which we should find). After being downloaded for the first time, INPUT D is shifted
2 positions (bits) left at each iteration, allowing Left part to get 2 new bits from the
input.
Right part is formed from 15 to 0 bits of Q which is a Quotient or Answer
register and it turns into 17 to 2 bits of Right part. As you can notice it is to some
extent similar to processing of the Left part. But, instead of taking 2 bits from the
Input, it places ‘1’ at right most bit and value of sign bit of Remainder at second bit.
At each iteration Answer Q, is shifted left for 1 position, taking inverted sign
value of Remainder at right most bit.
One more thing worth noticing is that Input D and Answer Q in the design
have 31 to 0 and 15 to 0 length, composing 32 and 16 bits width since when
multiplying two 16 bit values, you need to allocate 32 bits for the answer. Thus, we
have 32 bit input for squared value, 16 bit for root squared. This algorithm can be
easily converted into 16 – 8 or 8 – 4 bit versions. Left and right parts would need 2
more bits comparing to the answer, 10 and 6 respectively.
This process is called “Non inverting square root algorithm”, related theory
behind it is given in [5].
2.2 Binary into Binary Coded Decimal (BCD) conversion
To convert binary value (10010binary = 18dec = 12hex) into BCD representation
of decimal value (0001 1000 = “1 8”) for LCD input, “Double Dabble” converting
mechanism was used. [6]
It uses bitwise shift and add, and relatively easy to understand and implement.
For example, considering mentioned 18dec, we have “10010” binary. It can be
9
10
expanded to “00010010” to form 8 bit for convenience or left as it is. Theory says that
4*(n/3) equation for BCD length should be used, where n stands for bit length of
binary input and result of n/3 division is rounded up, e.g. 4*(8/3) = 4 * (2.66) = 4 * 3
= 12.
First, considering 8 bit input, 12 bit register divided into three 4-bit words is
prepared. At each iteration input shifted one position to this register. If the value of
shift inside 4-bit part is equal or more than 5, 3 value is added to it followed by next
one bit shift. n time shift should be executed (which is 8 in our case) before process
stops.
Register: 0000 0000 0000 Input: 00010010
Register: 0000 0000 0000 Input: 00100100
Register: 0000 0000 0000 Input: 01001000
Register: 0000 0000 0000 Input: 10010000
Register: 0000 0000 0001 Input: 00100000
Register: 0000 0000 0010 Input: 01000000
Register: 0000 0000 0100 Input: 10000000
Register: 0000 0000 1001 Input: 00000000
Register: 0000 0000 1100 Input: 00000000
Register: 0000 0001 1000 Input: 00000000
Initialization
shift 1
shift 2
shift 3
shift 4
shift 5
shift 6
shift 7
+3 operation, since 1001 = 9.
shift 8
(One can notice that, there was no point of carrying out 3 consecutive shift
operations before first ‘1’ bit reached border of BCD Register and he would be right.
This process can be successfully implemented same with 5 bit input and with 5
iterations. We just expanded input to 8 bit to provide input range of 255dec, 2^8 - 1. In
the design of Lock-in amplifier 16 bit binary input and 20 bit BCD or 5 words for
LCD are used)
2.3 Character display realization.
2 lines 16 byte (16 characters) LCD display is mounted on Spartan 3E Starter
Kit board. According to datasheet of Spartan 3E, it has 4 bits data input, 1 unused bit
and 3 bit to control LCD state – Enable, Register Select RS State, Read/Write R/W
State (LCD itself can be used in 8 bit mode to accept byte at a time, but to make it
compatible with other devices Spartan Starter kit exploits 4 data and 3 state bit
version [7]:
Figure 2.3 Spartan FPGA to LCD interface [7]
10
11
However one LCD command or character consists of 8 bits. So, two 4 bit
words (called upper and lower nibble) are send consecutively one after another.
When RS and R/W are both 0, such commands as clear display (0000 0001),
set display on/off (0000 0DCB), return home (0000 001X), set address (01AA
AAAA) and others defined are used (D, C, B bits are different options: to retrieve
data from DD RAM, to show cursor, or to make cursor blink when display is set on;
A is address bits).
There is two RAM memory used: DD RAM and CG RAM. One is used for
addressing purposes, and second contains preloaded Characters.
Figure 2.4. DD RAM address values for LCD screen. First line, first position: 0000 0000;
second line, second position: 0100(which is 4) 0000 (which is 0).
For example, to clear LCD, 2 nibbles “0000” and “0001” should be sent
consecutively. Then if someone needs to set position he needs to send address of DD
RAM also in 2 nibbles, the whole operation, in simplified form, would look like this:
Full_command <= “000000”; -- Notice that full command here is 6 bit instead of 4. First 2
bits are for RS and R/W bits
Delay
Full_command <= “000001”; -- RS and R/W with second nibble
Delay
Full_command <= “001100”; -- Notice that 1100 instead of 0100, since command line for
setting DD RAM address was 1AAA AAAA, 100 is 4.
Delay
Full_command <= “000000”; -- RS and R/W with second nibble
As can be seen, the above algorithm should be implemented in successive
order regarding full_comands. However, each bit of full_command can be assigned to
LCD inputs (RS, R/W, DB7, DB6, DB5, DB4) to change at the same moment as
full_command value changes.
Delay has to be higher than 1.6ms. Datasheet stresses that different commands
has to have different delays from lowest 40us up to 1.6ms for maximum. To secure all
the commands operations, and since Lock-in amplifier has DC (not varying) signals
as output results (after being filtered or averaged) 10 ms was chosen as standard
delay.
It was challenge to realize such delay in VHDL due to main board clock’s
20ns period. Simple clock divider would not well suit to such purposes. Better
solution was found in reading 7 highest bits (25 to 19) of 26 bit vector which
increments by one bit each 20 ns.
To achieve “0000001” in 25 to 19 bits, value of bit vector should be
incremented 2^19 = 524288 times reaching “00000010000000000000000000” after
11
12
524288*20ns ≈ 10.48 ms, thus providing enough time for the LCD commands to
execute.
In the design used LCD display part first launches
start commands, then takes BCD value from the
input and assigns upper and lower nibble for this
character to be set to LCD. It so turned out that
this upper and lower nibble comprises 8bit
ACSCII value from 48 to 58 (ie 0011 0000 for 0
or 0011 1001 for 9). There is two way to assign
ASCII value to BCD (0011 0000 for 0000). First
is to add 48. Second is to pre-set upper nibble to
0011. As you can see from the Fig 10, lower
Figure 2.5 RAM memory for characters
nibble exactly corresponds to BCD representation.
LCD input for Lock-in amplifier was chosen as 5 BCD characters (or 20 bits). Input
was expanded to have two more inputs for Y, Z apart from X values with 5 BCD
characters as well. Values are updated in successive way. One round takes
15+15+15=45 10ms cycles. To first result appear it takes 65 (start commands) + 45 =
110 cycles and the 45 cycles for 3 new values each time.
2.4. Inverting amplifier and analog to digital converter.
Analog to digital converting process includes two slave digital integrated chips
- LTC 6912 inverting amplifier and LTC 1407A ADC - network, driven by Spartan
3E FPGA master controllers [7].
There are 2 different ways to work with analog input of Spartan-3E 500 board.
First is to write everything in picoblaze assembler code and send it to ROM memory
of the chip. KSCPM3.exe (KSCPM3.exe for Windows 64 version is provided in
private manner) converts pre-written picoblaze assembler file *.psf in *.vhdl file with
binary array representing *.psf to be sent into ROM. Xilinx provides analog digital
control adc_ctrl.psf file with KSCPM3 VHDL library. Even though mentioned
assembler code and commands for adc_ctrl.psf file was well described and
documentation was available for it, it was a challenge to join it to work with lock-in
amplifier core written in VHDL. Instead some techniques were derived from
assembler code to implement all VHDL based amplifier gain setting and analog-todigital converter sample reading procedure, which represent second way.
Spartan Starter Kit User Guide provides interface and timing information to control
LTC 6912 amplifier and LTC 1407A ADC devices.
12
13
2.4.1 Amplifier gain setting
First, before signal is to be transformed into digital form, it goes through
inverting amplifier LTC 6912. Since there are two analog inputs VINA and VINB on
this chip, two gains should to be set serially (bit by bit) for the amplifier by controller
LTC 2624-1. Although second analog input can be left unread and unset with gain
and, both analog inputs are used in the design for signal and reference, and for X and
Y.
Figure 2.6 Analog signal capture diagram [7]
SPI_MOSI, AMP_CS, SPI_SCK, AMP_SHDN, AD_CONV,
API_MISO are control and data signals with 1 bit resolution each.
AMP_DOUT,
Value of gain is sent through SPI_MOSI, 1 bit at a time. Full gain has 8 bits
resolution, 4 bits for the first gain and 4 bits for the second.
Figure 2.7 FPGA to on board LTC 2624-1 interface [7]
AMP_CS bit acts as a launcher for LTC 2624-1 controller, but operates
inversely - when it is 1, controller is switched off, whereas when it is set to ‘0’, LTC
2624-1 turns into gain waiting position (waits for gain bits to be received).
13
14
Figure 2.8 Timing diagram for communication with LTC 6912 [7]
SPI_SCK is clock that is used for both amplifier’s and analog-to-digital
converter’s controllers. One needs to understand that SPI_SCK is not clock that drives
VHDL program; instead it is clock that is sent from VHDL program to both devices.
And amplifier and converter react to this clock, receiving or producing data
synchronously to it.
What is clock in FPGA domain actually? It is not clock in our comprehension
of it, for instance 1, 2, 3, 4, 5, but it is varying (alternating) 1 and 0. For example,
main clock (that is for program to be driven in this case) which comes from Spartan
3E XC3S500 processor has 20ns period. It has ‘1’ value during 10ns and ‘0’ value
during similar 10ns. But how we could now when to do something according to this
clock? We need to use internal COUNTER in our program for these purposes.
Now, we sent alternating 1 and 0 inside SPI_SCK to IC chips and setting and
reading data from them at each period. Counter that is used by devices is not of our
concern: they should “somehow” receive/produce values reacting on SPI_SCK clock.
But we need counter in our program to know which bit is to be sent and which bit is
to be received at each moment.
AMP_DOUT returns previous values of gain, but is not used, since it can be
ignored according to documentation.
It can be noticed from the Figure 2.8, that recommended SPI_SCK clock
period for amplifier is quite big - 100ns, and should have delay of minimum 30 ns,
before starting.
Internal amp_clock to drive gain setting process was realized using clock
divider: Simple XOR operation can alternate signal value from 0 to 1 and from 1 back
to 0 at each Spartan board clock cycle. If count rising edges of Spartan board clock, it
is possible to link XOR operation to certain counter value, e.g. 10, followed by setting
counter back to 0 (nullifying counter). And then to start counting again and continue
doing so until counter reaches next 10 value. Each ten counts takes 20*10ns=200ns.
But it is only for one XOR when alternation happens between 0 and 1. To reach next
1 or next 0 again, 2*200=400ns should pass. Thereby, it is 400ns clock.
Amp_clock is so set that at rising edge of it, gain bit is sent to Amplifier. ‘1’
signal of SPI_SCK is sent on falling edge of amp_clock, and ‘0’ signal on rising edge.
14
15
Figure 2.9 Original LTC 6912 timing diagram with amp_clock inserted
2.4.2 ADC conversion
LTC 1407A-1 ADC converter has slightly different interface consisting of 3
control signals. AD_CONV is a launcher bit. It has to be set to ‘1’ and back to ‘0’
before sampling process starts (with minimum 4 ns delay at ‘1’ state) to inform ADC
that data is to be read. SPI_SCK is the same clock pin for the ADC controller
interface as was used for Amplifier controller. SPI_MISO is serial data channel it
returns each digital data bit synchronously with SPI_SCK clock. There is “HighImpedance states” in SPI_MISO channel that corresponds to no data transfer periods.
For this reason, there is 2 SPI_SCK cycles delay before data bits are read, 2 SPI_SCK
cycles delay between two digitalized values, and 2 SPI_SCK cycles delay after them.
Figure 2.10 Interface an timing diagram for communication with LTC 1407A []
According to figure 2.10, samples are read with one sample latency, which means
signals that are converted at current moment, will be available for reading at next
sampling cycle, and those that are read now is from previous sampling cycle.
One sample here composed by two digital signals, each having 14 bits, and two of
them constitute 28 bits. Each bit is read during one SPI_SCK cycle forming 28
SPI_SCK cycles. Adding 6 delay cycles, full sampling cycles becomes 34 SPI_SCK
periods.
Apart from that AD_CONV bit should be set to ‘1’ and ‘0’, before sending SPI-SCK
bits, which implies that SPI_SCK should be linked to VHDL program internal clock
only at certain moments. There is interesting clock feature that is presented on the
figure 2.11:
15
16
Figure 2.11 Timing Borders for ADC samples reading
If look close at rising edge (transition from 0 to 1) of SCK_SPI clock and
starting point where each bit are transferred they are not match to each other (it is
especially clear from bottom diagram). Thus for safety reasons, bits should be read at
falling edge (transition from 1 to 0) of SPI_SCK clock.
Because of that, two internal clocks with two related processes were used for
ADC conversion.
adc_clock is clock that was synchronised to drive SPI_SCK, whereas (–
adc_clock) is clock that was set to run inversely in comparison with adc_clock. Since
rising and falling edge of main Spartan board clock cannot be detected within one
process, to avoid creating 2 processes for each mentioned clock and avoid error
related to creating 2 different sources to drive one signal, clock generating process
was reacting only on rising edge of Spartan 50 MHz clock. Since 50MHz corresponds
to 20ns period, high bit was generated during 20ns (period between two rising edges
of Spartan clock), and low bit during another 20ns, making full period to be equal to
40ns, which is sufficient to meet all the timing restrictions.
As (–adc_clock) operates inversely to adc_clock, its rising edge relates to
falling edge of SPI_SCK signal:
16
17
Figure 2.12 LTC 1407A-1 timing diagram with plotted ADC clocks
AD_CONV signal was set to 1 during one adc_clock period, and back to zero
during another. And at the beginning of third period SPI_SCK has to start operate
already. –adc_clock was linked to another process, where at rising edge of this clock,
data bits were read (see figure 2.12). Counter was used to assign each bit that was
read to correct index number of adc buffer (intermediate temporary container):
adc_buffer(15–counter_index) <=SPI_MISO, where counter_index increments
by 1. For instance, if make such assignment while counter_index is between 2 and 15,
adc_buffer (13 downto 0) can be fully filled.
Another point to mention regarding ADC timing, according to the diagram
AD_CONV should be set using adc_clock (2.12), then data bits should be read in
conjunction with -adc_clock. Since there are different processes for 2 clocks, to
realize such transition and join 2 processes together simple state machine was used, so
that process becomes infinite:
If adc_clock_counter=2 => B = 1, A=0
A (AD_CONV_set_state) = ‘1’
B (Data_read_state) = ‘0’
B (Data_read_state) = ‘1’
A (AD_CONV_set_state) = ‘0’
If -adc_clock_counter=36 => A=1, B = 0
Figure 2.13 State machine for continuously operating process
Finally, full sample cycle to read 2 inputs takes 2 more cycles for AD_CONV
to be set to 1 and back to 0 in the separate process and 2 additional cycles to
determine state machine position forming 38 adc_clock cycles for full sample cycle
(or 38 counter values) which is equal to 38*40=1520ns. It was useful at this stage to
create output clock that can drive some sample dependent VHDL blocks in Lock-in
amplifier design. This clock has rising edge at 38th clock cycle and falling edge at
19th. (Rising edge of the clock is synchronised with the moment when 2 inputs are
already read).
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18
2.4.3 ADC signals interpretations.
According to Spartan 3E datasheet, and Picoblaze reference, LTC 6912 is inverting
amplifier which has 1.65V at positive input and has ±1.25V input range at negative
input. Minimum edges are ±1.25mV from 1.65V.
Amplifier produces difference between 1.65V and analog input multiplied by Gain.
For instance, if +1.85V is applied to one of the inputs, then 1.65 – 1.2 = -0.2 * Gain is
sent to A/D channel. Gain is said to be negative. But it is negative from Spartan board
user’s point of view as he does not know that analog input is sent to negative input of
LTC 6912. Let us assume that Gain is 1. Then -0.2 should go to positive input of
ADC converter. However, the output of amplifier has +1.65V offset if measured by
voltmeter. Thus, -0.2+1.65 gives 1.45V. And finally, since negative input of ADC
converter takes 1.65V from power rail (
3.3V
2
), its difference input becomes 1.45 – 1.65
= -0.2V. This is 1.85 and 1.65 difference with inverting gain -1.
Another example with 1.64 V input and Gain 10. 1.65-1.64V=0.01 => 0.01*10=0.1
=> 0.1 + 1.65 = 1.75 => 1.75 – 1.65 = +0.1V. (1.64 and 1.65 difference with inverting
gain -10).
But since user does not know that inverting amplifier is used, equation given is
simplified to (𝑉𝑖𝑛 − 1.65) ∗ G, where Gain, G, is negative from -1 to -100.
Figure 2.13 Diagram provided by Picoblaze documentation [8]
So, Amplifier takes voltage value in range from 0.4V to 2.9V (through inputs VINA
and VINB), to produce difference between this value and a midpoint, 1.65V.
Difference ranges from +1.25V to -1.25V regarding 0.4V and 2.9V. Hence difference
value should be inverted in the program.
Now, analog to digital converter operation: ADC converter assigns digital value for
difference voltage ranging from +8192 to –8192 (for 0.4V to 2.9 V input or +1.25V to
-1.25V difference). Picture shown below is half true and designed for user (difference
value +1.25V and -1.25V is shown in right way to not confuse user), but it still can be
seen from it, that +8192 corresponds to 0.4V and -8192 to 2.9V.
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19
Figure 2.14 Digital representation for voltage values in Picoblaze documentation [8]
So that the equation responsible for digital conversion in ADC is:
𝑉𝑑𝑖𝑔𝑖𝑡𝑎𝑙 ′ =
(𝑉𝑖𝑛 − 1.65) ∗ G
∙ 8192
1.25
But, ADC digital output is far from ideal. To retrieve original voltage difference we
need multiply it by 1.25 and divide by 8192 and finally divide by -Gain.
(𝑉𝑖𝑛 − 1.65) ∙ G =
𝑉𝑑𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑐𝑒
1.25
′
∙𝑉
8192 𝑑𝑖𝑔𝑖𝑡𝑎𝑙
1.25
∙ 𝑉𝑑𝑖𝑔𝑖𝑡𝑎𝑙 ′
8192
=
−G
First, 1.25 can be converted into 1250 with assumption that floating point is after 1.
However signed 8192 is 15 bit value and if used as divisor directly can quite easily
level difference voltage to 0 point. Hence, if expression is multiplied by 2^16 first,
and then divided by 8192, the pre-kept result can be eventually retrieved.
But the result will be 16 bit shifted left (multiplication by 2^16 is 16 bit shift left). So
it should be divided back by 2^16 or shifted right by 16 bits. If more precise values
are needed the result can be left as it is. (But to be able to show 6 digit long, 5 digit
plus sign, X, Y, Z values on screen simultaneously, result was cut by 16 bits).
After estimation is done, whole operation can be reduced to simple multiplication by
1250∙216
8192
= 10000. And then if the result is set to be 32 bits long, upper 16 bits is the
desired value.
Volts applied
BCD Number retrieved
19
20
Figure 2.15 Analog to digital conversion
2.4.4 Gain settings
Spartan 3E Datasheet provide information on Gain settings for LTC 6912 amplifier
and related voltage limits:
Figure 2.16 Input voltage ranges for different gains [7]
If Gain value increases, accepted voltage range decreases depending on the
gain value. So that, it (to some degree) allows us to use more conventional
instrumentation amplifier instead of logarithmic amplifier for external measurements
by accepting flexible ranges proportional to the gain. Recalculated values for
multiplication coefficient:
2
5
10
25
50
100
625 ∙ 216
8192
250 ∙ 216
8192
125 ∙ 216
8192
50 ∙ 216
8192
25 ∙ 216
8192
125 216
∙
10 8192
5000
2000
1000
400
200
100
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21
Chapter 3: Digital Design of Lock-in amplifier
Digital Lock-in amplifier design, written on VHDL language, has a structure
illustrated in Figure 3.1, which is to some extent close to Stanford Research SR830
implementation.
Signed Mult.
VINA
ADC
VINB
Low pass
filter
Signal
Reference
√𝑋 2 + 𝑌 2
Signed Mult.
Low pass
filter
Zero Cross
Detector
X
Z
Y
Asinθ
PLL
Acosθ
cos
Figure 3.1 Implemented digital Lock-in amplifier diagram
The digitalized measured signal from ADC VINA output goes directly to 2
parallel Signed Multiplication blocks.
Digital Reference signal in turn, is converted in Square Wave, which is then
bounded to the output of PLL. The latter produce 2 quadrature shifted signals for
Signed Multiplicaiton blocks. Each result of Signed Multiplication goes to its own
Low Pass filter which generates corresponding output X or Y. Value of Z is found
almost simultaneously with X and Y.
3.1 Zero Crossing Detector
Zero Crossing Detector takes digitalized analog signal from input VINB
(reference) and looks for the moment when signal is crossing zero. If previous signal
(before crossing) was positive and new is negative it produces 0, otherwise, if
previous was negative and new signal is positive it produces 1. It is necessarily for
two reasons. First, it is more convenient to work with square wave in the next step,
which is Phase Locked Loop. Second, raw digitalized signal can suffer from noise and
hence may appear as not ideal sine wave.
FPGA signal flow features inside one executing process were utilized when
designing Zero Cross Detector. The whole point is that when primary signal derives
(or when affected by) assigned secondary signal (a <=b), the changes happens not
immediately, but at the end of process. Besides the fact that this characteristic of
FPGA avoids uncontrolled domino effect of signals changing each other
simultaneously, it also provides ability of acquiring value of previously changed
signal. Look at the simple example below, where signal a is input:
21
22
Process(clk)
begin
If rising_edge(clk) then
b <= a;
out_1 <= b;
out_2 <= a;
end if;
end process;
Figure 3.2 Example simulation
It does not look like something unusual or extraordinary here: b assigned to a,
and both a and b goes to the output. But wait, why we have different values as a result
at each clock cycle. The main point is, when signal a changes, it affects values of b
and out_2 at the end of the process at the same time. But, value of b acquired by out_1
at the same moment is not new. More precisely it is new, but it contains value of a
acquired in previous process. Thus, out_1 has value of b that contains previously
changed value of a at the considered end of the process. So, if we instead of sending a
and b to the output compare them to be more or less 0, we can eventually find out
when signal crosses 0 level. Though, we compare to 0 in indirect way checking sign
bit to be 1 or 0.
If a(15)=1 and
b(15)=0
b
a
Figure 3.3 Zero cross and falling edge detecting process illustration.
Apart from this comparison, we have to secure ourselves that signal crossed 0
not by accident, if so we will have to deal with uncontrolled square wave signals
changing every time at the output. Control of this behaviour is called hysteresis check
(or check on previous behaviour). In simple terms, we check how long or how many
increments of counter past after signal crossed zero point. If put border level for it,
say 64 increments (or 1.28us), we can compare this predefined value to actual number
of counter increments, thus providing stable signal at the output.
3.2 Phase Locked Loop
Initially, Phase Locked Loop consisted of 3 blocks - Phase Sensitive Detector,
Proportional Loop filter and Signal Generator:
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23
Asinθ
+
Phase Sensitive
Detector
∫
Proportional Loop
Filter
Signal generator
-
Acosθ
Figure 3.4 Design of originally implemented Phase Locked Loop
But in final variant of digital version, Phase Sensetive Detector and Propotional Loop
Filter steps underwent modifications.
3.2.1 Signal generator.
Signal generator has two parts: Direct Digital Synthesis block and 2 Sine
Look-Up Tables.
3.2.1.1 Sine Look-Up table
Sine Look Up table has 10 bit input (9 downto 0) and provides signed values
from 0 to 2^10-1=1023 with broad 16 bit output. To have less space occupied and to
provide bigger than 512 range values, realization of Sine LUT was quite tricky. 0 to
1023 is range of unsigned 10 bit, whereas -512 to 511 - is for signed 10 bit.
As for unsigned-signed example showed below, first bit in VHDL is used as
sign value (similar to the most cases of other signed value representations). The value
itself is complement (or bitwise-not) of positive value plus 1, e.g 011 becomes 100 +
001 = 101, 010 => 101 + 001 =110. This technique is called two’s compliment [3]
and was enhancement and step forward from one’s compliment which was based just
on bitwise-not.
VHDL signed-unsigned. Two’s compliment
011
3
3
010
2
2
001
1
1
000
0
0
111
7
-1
110
6
-2
101
5
-3
100
4
-4
011
010
001
000
111
110
101
100
One’s compliment
3
3
2
2
1
1
0
0
7
0
6
-1
5
-2
4
-3
Though one’s compliment had better visual recognition - if invert ones and
zeros, we will have same but reversed values for negative and positive examples – it
needed 2 representations of zero and had far less benefits from algebraic or logical
computations for signed values.
23
24
Whereas for two’s compliment: 3(011) + 4(100) =7(111) and 3(011)-4(100) =
-1(111). It is possible to see, that results obtained are exactly the same, and this means
that from binary standpoint there is no difference for processor how to work with
positive and negative values. It is how you interpret data themselves that matters.
Now, returning to our signal generator, standard sine LUT is so designed, that
it takes unsigned counter input (e.g. from 0 to 1023) and produces alternating signed
value for sine wave output. The simplest way but most space consuming is to write
down every 1024 values from 0 to 1023 for each increment of the counter. But since
there is a circulating characteristic in sine wave trend, it is possible to determine only
256 increments (from 0o to 90o) and manipulate their behaviour inside sine LUT
block. It was achieved by 2 pre-conditions: 1) checking value of (8 downto 0) bits of
the input index to be 256 or less for correct order, and if it is more than 256 to
subtract (7 downto 0) bits of input value from 256 for reverse order.
Bit index
Decimal value
when ‘1’
8
256
7
128
6
64
5
32
4
16
3
8
2
4
1
2
0
1
10000000 = 256 -> still correct order
10000001= 257 -> reached maximum. 7 to 0 bits gives = 0000001 => 256 – 1 = 255.
10000010= 258 -> reached maximum. 7 to 0 bits gives = 0000010 => 256 – 2 = 254.
2) If input index value is from 512 to 1023, then sine wave output (attention:
not index value) should be converted to negative. The key point here is that index
values for sine LUT are declared from 0 to 255 by unity-step increment (others are
generated as was shown above), but sine output-range for each index can be any from
0 up to 2output length-1. In the design 0 to 1024 values were generated in matlab for 0 to
255 index values with average increment 1024*sin(90/index range)
=1024*sin(90/256)= 6.277:
When 0 => sine_out <= 0
When 1 => sine_out <= 6
When 2 => sine_out <= 13
...
When 255 => sine_out <= 1024
Negative conversion is done by previously mentioned operation: invert all bits
within output length and add one:
1023: 00000001111111111 => 11111110000000001: -1023
One question still can arise of how LUT block could know what frequency
input signal has: should we increment by +1 or +2 or +3. The fact that it does not
control step change, makes it universal. Frequency is controlled outside LUT block.
Moreover, shifted signal, cosine function for instance, can be implemented simply by
starting counting from shifted index, e.g. from 256 for 90o shift, outside LUT and
sending counter index to LUT.
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25
3.2.1.2 Direct Digital Synthesis (DDS) block.
This is a core of signal generator. The main purpose of it is to take “frequency
component” of Phase Sensitive Detector after it went through Loop filter and produce
2 counters (for sine and cosine), incrementing with step that depends on received
“frequency component”. Both of these counters have 10 bit length and sent to the Sine
LUT block that was described in previous section. So that Signal generator ends up
taking samples from predefined values according to accumulated value of the counter,
and this is the main feature of DDS block which distinguishes it from Arbitrary Wave
Form generator (AWG) [9]. Apart from 2 counters for sine and cosine, it also
produces alternating square wave linked to high order bit (left most bit) of the
counter. Peak of 10bit counter value corresponds to decimal 1023 (11111 11111), a
half of this value equals to 512 which is 1000000000. Thus, square wave changes
exactly with the same frequency as sinusoidal signals at the output of the LUT.
0..1023
DDS (or frequency to
phase-accumulation )
256..256
Sine LUT 1
Sine LUT 2
Asinθ
Acosθ
Figure 3.5 Signal Generator Diagram
Now, the most interesting part is how frequency input of DDS is going
produce counter output. If counter was incrementing by 1 bit at a time it would reach
360o after 1024 clock periods or 1024*20ns = 20.48us it is about 48.8 kHz. What if
we need lower frequency? We actually need lower frequency: as low as 1Hz, since
having default 1Hz, we can produce 50Hz simply by multiplying it by 50 (or for 10
MHz, by 106).
The solution for that could be utilization of counter that we already used for
LCD display clock. In the case of display clock it gave us extra time before highest
bits would increment by 1. The same is with frequency, it can give us extra precision
by which counter would increment at each 20ns. We already defined that counter is
10 bit length for sine LUT table. We can improve situation by using 50 bits counter
and reading highest 10 bits of it. It will give us 2^40 clock periods before 1 bit would
appear in highest 10 bits “0000000001”, and another 2^40 for second increment by 1
and so on. Eventually we would need 2^40*20ns = 21990s for 1 increment. It is
excessive of course, but we have 2^22-1 (22 bit) limit = 4194303 gain as proportional
part of Loop filter, and we need to set exact step by which counter would increment
reaching 1023 in 1s or 1Hz.
If work in frequency domain: 1*1024 (Hz in 1s) gives us frequency for 1
increment (considering highest 10 bits). We need to multiply it further by 2^40 to
determine frequency of 1 increment considering full 2^50 counter and divide result by
clock frequency 50*10^6 (or multiply it by clock period 20ns. 20ns for each Hz),
which will give us a step by which we need to increase our counter (or phase
25
26
accumulator now) at each clock period to reach 1Hz for whole sine wave. This step
turns to be 22517998.
4194303 limit frequency from Loop Filter gives as 41.94 ≈42 MHz which
almost close to the clock limit of 50Mhz.
Eventually, phase step is equal to 22517998 (for 1Hz) * input frequency; and
now use of big (2^50 bit) length phase accumulator becomes clear advantage.
Last few things to review here is that phase output for sine LUT takes 49 to 40
bits of phase accumulator as was said before. Whereas cosine takes same 49 to 40 bits
but adds 256 value to it, which corresponds to 90o phase shift. Square wave for PSD
block is produced by inverting 49th bit of phase accumulator, which responsible for
sign bit or values from 512 (1000000000) to 1023 (1111111111). When phase
accumulator reaches its maximum, it turns to 0 at next count and counting process
starts all over again.`
3.2.2 Phase Sensitive Detector (PSD)
Phase sensitive detector (or PSD) was initially based on the work presented in
[10]. Instead of operating with sinusoidal waves as its counterparts usually do, it
operates with 2 square wave inputs, which makes it simpler in realization. The design
of PSD “edge triggered D flip flop” that was exploited in [5] is one of the most simple
and reliable, and thus most commonly used digital phase detectors. It contains 2 flipflops, that acts like this: when reference square wave input equals to DDS input, i.e.
both equals to ‘1’ or ‘0’, reset is set to ‘1’ by virtue of AND block, and reset nullifies
both flip flops outputs, i.e. sets to ‘0’; when reference input is ‘1’ but DDS input is
‘0’, reference flip-flop’s output is ‘1’, in the same manner, when DDS input is ‘1’ but
reference input is ‘0’, DDS flip-flop’s output is ‘1’.
Phase Sensitive Detector
Reference
+ve
output
𝑄
> ref
reset
𝑄̅
A=+1
∫
∫=∫+A
reset
DDS feedback
𝑄̅
> dds
𝑄
DDS
A=-1
-ve
output
Figure 3.6 Phase Sensitive Detector with Up and Down counters
There was one intrinsic feature in flip-flops that is worth noticing, which is called
glitch. It appears due to propagation delays (approximately 10ns) typical for FPGA
signals. Although we should not be worried about it since we have 20ns clock, it is
safe to assign flip-flops outputs to intermediate signals outside the process bonded to
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27
clock and use this intermediate signals for addition or subtraction (not showed on
diagram)
Second part of the Phase Sensitive Detector is Integrating block. Each clock cycle it
sums up by +1, -1 or 0 depending on flip-flops outputs. And result of this integration
together with positive and negative outputs of flip-flops goes to Loop Filter.
3.2.3 Loop Filter Question
It was step, where serious stagnation happened for a while and at the same
time crucial progress was achieved. Different sources were using different solutions
for Loop filter, from simple UP and DOWN counter loop filter producing square
wave signals to integration of digital PSD-analog Loop FIlter conversion [?], or first
and second order digital systems. The main purpose of having an intermediate block
in between PSD and DDS was to remove high frequency components and to establish
“smother” feedback approach to required phase difference and thus produce same
frequency.
Originally proportional filter which simply adds much bigger proportional part
(depending on positive and negative input) to integral part was chosen to work with
mentioned PSD. However reference signal was not perfectly locked and this caused a
search for better solutions. At some point, a big question arose as to whether digital
Lock-in design needs feedback at all. Yes, it should be Locked, but in digital Lock-in
design it can be locked directly to frequency component, and not necessarily to phase
difference as is the case in most PLL designs. In PLL design phase difference gives us
frequency by estimating 2 phase differences of 2 inputs signals between adjacent
periods (see interim report).
Furthermore, in conventional PLL design, you should have feedback since at
starting point phase difference between input signal and oscillator output signal is
varying all the time and it should be stabilized. However we can estimate only
frequency of reference signal as we produce sine and cosine components that
eventually give us results needed no matter what phase difference component is, as
soon as frequency of sine and cosine is linked to the reference signal’s frequency.
And last point. Why feedback control is needed in automated systems? When
we feed some external physical system, e.g. gas turbine, with some control signal,
pressure value for instance, we have to read feedback output of the system all the
time. This output can have different physical measures, temperature for example, or
be the same pressure output as well. The major point is we do not set this output by
ourselves. A physical system undergoes transformations the knowledge of which we
usually can only predict. So we need continuous feedback to use an error or difference
component to set new control signal.
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28
But why we need loop that controls something to what we can link directly?
Moreover we have ability to set input and consequently output frequency of DDS “by
ourselves”. (What is meant here DDS oscillator is not “external physical system”,
output of which we do not know or cannot set. Of course, it is not set by user. We can
link it to any signal we need).
To derive frequency information from square wave reference (produced by
zero cross detector), first step is to find period of this signal by calculating how many
clock cycles past from when ‘0’ turned to ‘1’ till when ‘0’ turned to ‘1’ next time.
VHDL does not allow to use two clocks (clock events) in one process, e.g.
rising_edge(clock), rising_edge(reference). But FPGA signal propagation mechanism
inside a process can give us information about previous and current signals. See an
illustrative example below (signals are marked with navy blue):
Process(clk_in) – processing at each clock cycle
variable ref_frequency_integer:integer;
begin
if rising_edge (clk_in) then
previous_ref_signal <= reference_input; -- signal will be assigned only at the end of the process,
thus previous_ref_signal does not contain current value right now;
if ((reference_input = '1') and (previous_ref_signal = '0')) then -- This condition will use
current input and signal that was assigned in a previous process. So we use current reference and
previous, to determine when reference pulse goes high.
ref_frequency_integer:=1000000000/(20*to_integer(unsigned(ref_period_counter))); ---?
ref_frequency <= std_logic_vector(to_unsigned(ref_period_integer, 24)); -- frequency
calculation and conversion at rising edge of reference signal
ref_period_counter <= (others =>'0'); -- sets 32 bit counter to 0;
else -- if reference is continuously high or low, count.
ref_period_counter <= std_logic_vector(unsigned(ref_period_counter) + 1); -- it counts
(counter=counter+1) during both positive and negative periods
end if;
end if;
end process;
Frequency calculation:
Reference frequency is inversely proportional to its period (f=1/T). Period
equals to numbers of clock cycles past between 2 rising edges of reference signal
multiplied by clock period. But since clock period is 20ns, reference period can be
much less than 0 and reference period was not used directly in code. Instead,
straightforward frequency calculation was done using multiplication by 10^9 and
division by 20 on the inverted counter magnitude.
Figure 3.7 Frequency tracing example. f=157.2 kHz
28
29
Figure 3.8 Frequency change from 24.4 kHz to 12.23 kHz with one reference period delay to retrieve
altered frequency.
Asinθ
Frequency Extraction
Block
reference
f
Signal generator
Acosθ
Figure 3.9 Final Frequency Locked Loop.
“ref_frequency_integer:=1000000000/(20*to_integer(unsigned(ref_period_count
er)))” line was perfectly simulated, but could not be synthesized to produce
configuration file since the default “/” operator was waiting for constant parameters
with 2 base (2, 21 ,23, 24 etc). So, 1000000000/20 was converted into 50000000 then
into binary representation "10111110101111000010000000". At first, simple subtract
and count algorithm (repeated subtraction) was used for dividing it by variable
counter, since division process is n times subtracted divisor from dividend before
remainder becomes less than divisor. 72=n*6. 6 can be subtracted 12 times before
remainder becomes 0<6. So 12 is an answer. But this method suffered from high
calculation time for big dividend values, especially, in case of small counter divisor.
Finally, rather tricky but highly productive bitwise shift and subtract based “restoring
division algorithm” was used:
To realize this division:
Create 3 registers for dividend (2n+1 size), divisor (n size) and additional register,
which has the same size as dividend (2n+1). 1 additional bit is used for sign value
during subtraction.
For 72:6=12
A: 72: 0 0100 1000
B: 6:
0110
C: 0:
0 0000 0000
Before iteration process starts, divisor B is loaded in additional register C and shifted
n bits left.
C: 0 0110 0000
Further, additional register C will be containing two’s compliment of divisor or
simply (–divisor) shifted n bit left. Sign bit will take high order bit value.
C: 1 1010 0000 (for two’s compliment: invert all bits and add 1).
Dividend A is used as a final result register. And after being shifted 1 bit left,
additional register (-divisor) is added to it at each iteration. So that shift and
subtraction operations are performed for n times, where n is bit length of divisor B.
29
30
If after subtraction (or addition of –divisor), sign bit of dividend A contains 1 value
(which takes high order bit of register and does not participate in addition or
subtraction), Last Significant Bit is set to 0 and previous value is restored by addition
of original divisor, otherwise Last Significant Bit is set to 1. Detailed process:
0 0100 1000
0 1001 0000
0 1001 0000
1 1010 0000 (-divisor)
0 0011 0000
0 0011 0001
0 0110 0010
0 0110 0010
1 1010 0000 (-divisor)
0 0000 0010
0 0000 0011
0 0000 0110
0 0000 0110
1 1010 0000 (-divisor)
1 1010 0110
1 1010 0110
1 1010 0110
0 0110 0000 (divisor)
0 0000 0110
0 0000 1100
0 0000 1100
1 1010 0000 (-divisor)
1 1010 1100
1 1010 1100
1 1010 1100
0 0110 0000 (divisor)
0 0000 1100
Load dividend A
Shit left (1st time)
+
Result contains 0 in sign bit.
LSB is set to 1
Shit left (2nd time)
+
Result contains 0 in sign bit
LSB is set to 1
Shift left (3rd time)
+
Result contains 1 in sign bit.
LSB is set to 0. Original divisor is added then
+
Previous value is restored
Shift left (4th time)
+
Result contains 1 in sign bit
LSB is set to 0. Original divisor is added then
+
Previous value is restored
Answer: 12
3.3 Signed Multiplication block
Signed multiplication blocks and Low Pass Filters are driven not by Spartan
50MHz clock, but by sample 1520ns clock generated in ADC converter.
Signed Multiplication is the simplest block in the design. It benefits from
VHDL packages and was realised using default function “*” of VHDL Numeric
library for two signed parameters. The idea behind it was similar to unsigned values
multiplication except for keeping in mind sign bits.
Procedure description: Initially “remove” the highest bit from one of the
parameters and shift second resized 2 times parameter (by filling with its high order
bit to save sign value) left by one bit for each iteration depending on bit length of the
first parameter. Check whether each following bit of the first parameter is ‘1’ during
each iteration: if yes, add shifted value to accumulating sum, if not do nothing. The
last process resembles multiplication by 1 and 0. Example below illustrates
multiplication 3 by -7, and -5 by -7:
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31
0011 * 1001
*
1
+
result
1
1
1
1011 * 1001
X
0
1
1
X
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
1
1
1
0
1
0
1
1
+
-
2
1
result
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
1
1
1
0
1
0
1
1
1
0
0
0
0
1
0
1
3
5
1
0
1
0
0
1
0
0
If the highest bit (X) of the first parameter is ‘1’, shifted value that belongs to
it is subtracted from the intermediate result instead of being added.
3.4 Low Pass Filter
3.4.1 Low pass filter via Exponential smoothing
Exponential moving average or exponential smoothing technique was used to
cut-off high frequency components.
Exponential moving average is extension of simple and weighted moving
average techniques. These methods were first proposed in statistical research for
predicting demand trend. But they perfectly suit us, since was introduced to smooth
sampled data varying in “real-time” domain. The simple moving average takes n
previous samples, adds them together and divides by n producing mean value each
time. Weighted average multiplies each value by weight before finding mean, later
values by higher weights, earlier by lower weights which makes later values to be
more important for better tracing. But why these techniques are called moving
averages? Because they make a step forward each time, taking new n values with last
derived as latest one.
Exponential moving average was introduced by Robert G. Brown [5], since
two other mentioned algorithms suffered from need to retrieve or to save k previous
values in memory. If there is feedback loop, so that 𝑠0 = 𝑥0 (where s0 is first output, x0
first input), then next estimated output can be found as:
𝑠𝑡 = 𝛼𝑥𝑡−1 + (1 − 𝛼)𝑠𝑡−1 , 𝑡 > 0
Where α is factor of smoothing. 𝑥𝑡−1 – is current input, 𝑠𝑡 - is smoothed
output, 𝑠𝑡−1 is previous output that was already smoothed. α should be between 1 and
0. In statistics there is no strict rule of choosing α factor. If it is close to 1, then the
output is raw and close to original data. Whole equation works similar to weight
31
32
parameter with time. For example: 𝑠𝑡 = 𝛼𝑥𝑡−1 + (1 − 𝛼)𝑠𝑡−1 , but previous output is
𝑠𝑡−1 = 𝛼𝑥𝑡−2 + (1 − 𝛼)𝑠𝑡−2 ; And if substitute 𝑠𝑡−1 in 𝑠𝑡 , it gives: 𝑠𝑡 = 𝛼𝑥𝑡−1 +
𝛼𝑥𝑡−2 (1 − 𝛼) + (1 − 𝛼)2 𝑠𝑡−2 . And if continue substituting 𝑠𝑡−2 = 𝛼𝑥𝑡−3 +
(1 − 𝛼)𝑠𝑡−3 into last obtained 𝑠𝑡 , it gives further 𝑠𝑡 = 𝛼𝑥𝑡−1 + 𝛼𝑥𝑡−2 (1 − 𝛼) +
𝛼𝑥𝑡−3 (1 − 𝛼)2 + (1 − 𝛼)3 𝑠𝑡−3 and so on.
Since 0< 1-α <1 then α> α(1- α) > α (1- α)2>...> α (1- α)k=t-1. Values close to
current input are less smoothed than older values. Moreover element weights decrease
(again since 0< 1-α <1) with geometric progression (α, αr, αr2, αr3...) at each iteration,
which is exponential decay function y= αrk with r=1-α and 0<r<1.
r determines direct proportion at which function decays each time, and α, since
r=1-α, is a decrease rate. Let r=1/4, then α=0.75 or 75%
1) 𝑦0 = α = 0.75
1
2) 𝑦1 = 4 α = 0.1875
1 1
3) 𝑦2 = 4 ∙ 4 α = 0.0468
Brown’s equation can be illustrated us:
𝑘=𝑡−1
k
𝑠𝑡 = ∑𝑘=𝑡−1
𝑘=0 yk 𝑥𝑡−(𝑘+1) = ∑𝑘=0 αr 𝑥𝑡−(𝑘+1) , α, r ∈ [0, 1].
As theory says, Exponential decay function decreases with rate proportional to
current magnitude:
𝑑𝑦
𝑑𝑡
= −𝜆𝑦 . Thus λ here has the same meaning as α. 0.1875 −
0.75 = − 𝜆 ∙ 0.75, which gives λ= α=0.75. Hence we see that α is exponential decay
constant and determines zero approaching rate in exponential decay function.
1.2
1
0.8
0.6
α=0.5
0.4
α=0.001
0.2
0
0
2
4
6
8
10 12 14 16 18
Figure 3.10 y=(1-α)x function with different α.
If the rate of approaching is rather fast, then latest values will have more
meaning (or higher weight) than older values within considered function and output
will be close to the original data and will be less smoothed. Whereas, if an
approaching rate is slow, then weights of the previous values will be levelled and
output will be smoothed. Since we need to let only DC signal go after signed
multiplication of sin(ωx+θ1)*sin(ωx+θ2) and sin(ωx+θ1)*cos(ωx+θ2), the α should be
32
33
close to 0 which aligns adjacent values drastically. Original Brown’s equation joined
with available ports takes the form:
𝑜𝑢𝑝𝑢𝑡 = 𝛼 ∙ 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑖𝑛𝑝𝑢𝑡 + (1 − 𝛼) ∙ 𝑝𝑟𝑒𝑣𝑖𝑜𝑢𝑠 𝑜𝑢𝑡𝑝𝑢𝑡,
α was assigned to 0.01 through division by 100 considering current input, and through
1
multiplication by 99 and division by 100 regarding previous output or (1 − 100).
1
𝛼
or
100 is time constant of exponential function.
1
Output that has to be levelled is two DC offsets: 2 Vsignal ∙ 𝑉𝑟𝑒𝑓𝑒𝑟𝑒𝑛𝑐𝑒 ∙ sin(𝜃1 − 𝜃2 )
and
1
V
2 signal
∙ 𝑉𝑟𝑒𝑓𝑒𝑟𝑒𝑛𝑐𝑒 ∙ cos(𝜃1 − 𝜃2 ). To retrieve pure Vsignal sin(𝜃1 − 𝜃2 )
and
Vsignal cos(𝜃1 − 𝜃2 ), output of Low Pass filter should be divided by 𝑉𝑟𝑒𝑓𝑒𝑟𝑒𝑛𝑐𝑒 and
multiplied by 2 in the next 𝑍 = |Vsignal | estimation block.
3.4.2 Low pass filter via Simple Periodic Average
There is another method however available for us to retrieve DC offset from
two multiplied signals. And it stems from the benefit of adding direct Frequency
Extraction block in the PLL.
Since we can estimate how many samples cycles past between 2 periods of
reference and when rising edge of reference signal is (actually we even have square
wave signal from Zero Crossing Detector block), we can process this information
inside Low Pass Filter.
After that, Low Pass Filter turns into simple accumulator with averaging
function. It starts accumulating output of Signed Multiplication block at rising edge of
reference signal and continues doing so for each clock cycle until next rising edge of
reference turns up. This is where number of clock cycles between two periods from
Frequency Extraction block can help. Simply divide accumulator on this counter. We
can further divide obtained result by 1024 and multiply by 2 to produce
𝑉𝑠𝑖𝑔𝑛𝑎𝑙 sin(𝜃1 − 𝜃2 ) and 𝑉𝑠𝑖𝑔𝑛𝑎𝑙 cos(𝜃1 − 𝜃2 ) and finally get 𝑉𝑠𝑖𝑔𝑛𝑎𝑙 from Z <=
√X 2 + Y 2 without additional entities or processes.
Until this point the process seems to be straightforward and simple. But
whether there are limitations? Negative aspects of space occupation by bitwise (shift
and subtract) division algorithms, restoring division or any other, during synthesis
process will be considered in next part.
33
34
3.5 Process of synthesizing and design optimisation
Process of synthesizing is crucial part of the FPGA programming, a logic
simulator (part of Xilinx ISE design software) read VHDL code and produces logic
slices (e.g. and gates, flip-flops) or “physical implementation” of the VHDL code.
At this step some space consuming steps was revealed. As it turned out, most
of them were caused by “restoring division algorithm”, or bitwise division process
including shift and subtract operations. Algorithm itself was fast and much more
productive than repeated subtraction (the latter caused crash during simulation), but
the number of slices occupied increased exponentially with increasing bit length of
the dividend or divisor. The figure below shows two examples for one block tested,
one with 8 bit dividend and divisor, and the other with 16 bit values.
Figure 3.11 Synthesized block summary with different resolution for a restoring division function.
In the design 32 (current input) and 64(output) bit signals were used for
“restoring division algorithm” in Exponential Decay function and utilization was
close to Spartan 3E XC3S500 limits or exceeding all the limits with 64 bit case.
Decision was made to set divisor (1/α) to 128 (27) with α becoming 0.0078125
(1/128) instead of 0.01 and use default “/” operator instead of restoring division. 1-α =
0.9921875 (or 1 −
previous_output
128
=
127∗(previous_output)
128
). In this way, “/” is equivalent
to right shift and does not depends on input or output bit resolution.
Big values division was also used in Averaging Filter:
𝐴𝑣𝑒𝑟𝑎𝑔𝑒 (𝑓𝑜𝑟 𝑎𝑣𝑒𝑟𝑎𝑔𝑖𝑛𝑔 𝑓𝑖𝑙𝑡𝑒𝑟) =
𝑎𝑐𝑐𝑢𝑚𝑢𝑙𝑎𝑡𝑒𝑑 𝑠𝑢𝑚
512
𝑐𝑜𝑢𝑛𝑡𝑒𝑟
Division by 512 (2/1024 equals to 1/512) can be employed again by “/” operator
or by simple signed right shift. 512 is 2 to the power of 9, 29. Thereby, to divide by
512 a binary value should be shifted 9 times right (9 bits right).
34
35
It works with constant having 2 as its base (for example, to divide by 4=22 =>
shift original value 2 times right, by 16 = 24 => 4 times). However, a counter and
accumulator are arbitrarily varying signals. And bitwise division algorithm has to be
used for them after 9 bit shift was done.
First, what bit size accumulator should have? To read two analog inputs (they
are read together) 38 clock cycles are needed or 1520ns. If assume that reference
frequency is 1hz, 109 ns will pass between 2 rising edges of reference and
109 ns
1520 ns
=
657985 samples would be read during one period of 1hz reference. As we know edge
value of reference signal is set in Signal Generator to be 1024 and because generator
produces ideal sine wave we can pre-calculate sum for half of the reference period
(sum for full period will be 0 with respect to ideal sine wave) to find maximum
accumulated sum ∑𝑥=328992
1024 ∙ 𝑠𝑖𝑛(
𝑥=1
180
328992
∙ 𝑥) value by simple C++ program:
#include <iostream>
#include <math.h>
int main ()
{
int sum=0;
for( int a = 1; a <= 328992; a = a + 1 )
{
sum=sum+1024*sin((3.14*a)/328992);
}
cout << "value of sum: " << sum << endl;
}
Value of sum is 214411681. Since Loop Filter takes multiplication of signal
and reference, and assuming that edge value of signal cannot exceed digitalized 1250,
1250*214411681 gives 268 014 601 250, which has resolution of 39 bits for signed
accumulator. Even when shifted by 9 bits, it is still 30 bits signed or 29 bits unsigned.
Such size would not be acceptable for bitwise. What can be done to reduce size of
division parameters is to increase sample reading period for instance from 1520ns to
15200ns. However, then frequency bandwidth of the input signal will be 1Hz ÷ 5 kHz
(14 samples for 5 kHz). Other way is to put 50Hz as lower limit. New recalculated
sum for 50Hz will be 4287679 and 1250* 4287679 gives limit 5 359 598 750, which
has 34 bit resolution for signed accumulator representation. If shifted 9 bits right, it
becomes 24 bit resolution for unsigned result (restoring division uses unsigned
values). While both cases were considered separately for Averaging filter, it was
apparent that lower frequencies needed bigger sampling delay, whereas higher
frequencies worked well with lowest delay. Finally, flexible sampling time was set for
reading of analog values. It was possible since we constantly estimate reference
frequency inside frequency extraction block and this frequency can be sent to ADC
block to control adc_clock. 152000 ns sample reading period will be set when
reference frequency is lower than 10Hz, 15200 ns when it is between 10 and 100Hz,
and default 1520 ns when it is higher than 100Hz.
Restoring division algorithm was also used in Frequency Extraction process.
But, the numerator had 16 bits and logic slices occupied were acceptable for it:
35
36
Figure 3.12 Reference frequency extraction block
The whole design including ADC converter and LCD display parts with
Exponential Filter took approximately 63% of the slices available for Spartan 3E:
Figure 3.13 Design Utilization 1
And with Averaging Filter - 71% of the slices available for Spartan 3E:
Figure 3.14 Design Utilization 2
3.6 Simulation and testing
Lock-in amplifier with Averaging filters for X and Y.
Simulation results:
DDS square wave output which is linked to Reference frequency was used in
final code, instead of using Reference square wave directly. SignalI2 and SignalQ2
are X = Vsignal ∙ cos(θ1 − θ2 ) and Y = Vsignal ∙ sin(θ1 − θ2 ) results. Sum1 and Sum2
accumulated sum during each DDS periods. Quantity1 and Quantity2 are quantity of
samples between 2 rising edges of DDS signal for two quadrature shifted signals. It
takes only 2-3 DDS_square_wave cycles to start producing stable average values.
36
37
Figure 3.15 Xilinx Simulation
As can be seen, sample number is the same 658 but accumulated sum is
different for X and Y. Signal_in in this simulation, had DC offset initially, but result Z
was equal to ~1250V, namely amplitude of Signal_in.
3000
Signal_in of testbench LUT
Rereference_in of testbench LUT
2000
2000
0
0
-1000
1
61
121
181
241
301
361
421
481
541
601
1000
1
104
207
310
413
516
619
722
825
928
1000
-2000
|Vsignal | = 1250
|Vreference | = 1024
Figure 3.16 Signal and reference graphs for testbench values Simulation with different
amplitudes
Below is an example for Signal_in without DC offset:
Figure 3.17 Xilinx Simulation
Signal_in of testbench LUT
2000
2000
1000
1000
-2000
0
-1000
1
104
207
310
413
516
619
722
825
928
1
61
121
181
241
301
361
421
481
541
601
0
-1000
Rereference_in of testbench LUT
-2000
|Vsignal | = 1250
|Vreference | = 1024
Figure 3.18 Signal and reference graphs for testbench values Simulation with different
amplitudes
37
38
Result 𝑍 = √12482 + 362 ≈ 1250 again corresponds to amplitude of Signal_in
After optimization of the digital design, the design was tested on FPGA.
Input signal with Gain=-1; DS offset 1.64V of external signal generator corresponds
to middle point of ADC converter or 0V. 2.51 is peak to peak, hence signal amplitude
is
2.51
2
= 1.255V. FPGA recognises it as signal varying from -1255 to 1255 with 0000
offset.
Figure 3.18 Input signal from Signal Generator
Reference signal had same 1.64 offset and peak-to-peak voltage 1.05V, which
is 0.525V amplitude. FPGA recognises it as 0000 offset with 0525 amplitude.
Figure 3.19 Reference signal from Signal Generator
38
39
Bear in mind that original reference signal is not used; instead sine wave with
1024 is generated with respect to reference frequency value. Results taken from two
separate probes:
Figure 3.20 Amplitude estimated by FPGA
For X and Y to be equal in both cases(X1=X2, Y1=Y2) it is required that phase
difference between signal and reference is the same or equal to 0° for two different
experiments.
Exponential Decay filter showed almost similar results. But it is necessary to adjust α
parameter each time when reference frequency changes; or values can diverge from
average level (due to different sample number for one period) and good smoothing
result will not be achieved.
1
Example below is for 320Hz reference frequency with picked α = 64 = 0.0156. Input
signal has amplitude 200mV (400 peak-to-peak).
Figure 3.21 Xilinx Simulation
√1902 + (−73)2 = 203
FPGA test. Signal has amplitude 200mV, frequency 320Hz:
Figure 3.22 Input signal with from signal generator
39
40
Reference has same frequency:
Figure 3.23 Reference from signal generator
Results:
Figure 3.24 Amplitude estimated by FPGA
It is recommended to use Averaging filter for more stable and fixed results.
Additionally, realization of it is much simpler. However, Averaging filter block
suffers from external space occupation due to big sample accumulator in the
numerator of the restoring division. Exponential Filter does not have this drawback,
but realization of it is much more sophisticated and need of constant adjusts for
different frequencies makes it less flexible. One can notice, that we have frequency
information and can use this information to adjust time constant, but in this case much
closer and careful approach is needed, compared to the case of rough sample rate
controlling for averaging filter. And it was not considered in the design proposed.
Final experiment with prevailing noise (averaged filter design used):
Figure 3.25 Signal and noise characteristics connected to common pin
40
41
Figure 3.26 Noise plus signal on oscilloscope
Final results: Amplitude is ~25mV.
Figure 3.27 Amplitude estimated by FPGA
41
42
Chapter 4: Analog design of Lock-in Amplifier
The analog design implemented is following the work done by Sengupta et.
al.[1]. They utilized AD630 flexible modulator/demodulator IC (integrated circuit) to
create phase dependent Lock-in amplifier, which implies that the reference and
measured signal should be always in phase (0o phase shift). Apart from AD630, they
used INA114 Instrumentation amplifier for signal amplification and suggested to use
AD620 as possible replacement (both are non inverting amplifiers). In addition, RC
Low Pass filter followed by op-07 operational amplifier which can embed further
negative feedback gain is used for filtering purposes.
Figure 4.1 In phase (phase dependent) Lock-in amplifier.[12]
AD 620 Instrumentation Amplifier
Instrumentation amplifier is often used for measuring devices since there is no need to
match impedances between measured and measuring instruments.
V1
R3
R2
+
R1
R1
V2
+
Vout
+
Rgain
R3
R2
Figure 4.2 General Instrumentation amplifier scheme and AD620 pin connections in Proteus ISIS.
42
43
It is achieved by use of additional operational amplifiers (op amp) that is installed in
series with two inputs. It is just op amps have very high impedance input and very
low impedance output. Op amps used in this way are called amplifier buffers. In the
figure below 2 left op amps are used as amplifier buffers and third right op amp is
𝑅
used as negative feedback amplifier with - 𝑅3 gain.
2
According to Kirchhoff’s voltage law, amplification level for instrumentation
amplifier is derived as:
𝑉𝑜𝑢𝑡
𝑉2 −𝑉1
=
Rgain +2R1 𝑅3
Rgain
R1
∙ 𝑅 = (1 + 2 R
2
gain
𝑅
) 𝑅3
2
As can be seen gain is inversely proportional output voltage. Hence by increasing gain
resistance, voltage level on the contrary will decrease and vice versa. Rounded values
of Gains and related resistance are given in documentation of AD620 [13].
AD 630 Modulator/Demodulator
As was said, AD630 is flexible modulator and demodulator IC (integrated circuit). If
connected in specific ways, it can play different roles, but the one we are interested in
is a modulation of two signals.
AD630 IC chip was available in the library of Proteus 8 software. It was driven by
two in phase sinusoidal signals and modulated response was read then in simulation
mode.
Figure 4.3 Proteus simulation for AD630. Input signals are in phase.
43
44
However, internal behaviour for AD630 is rather unclear at this point. If it was simple
multiplication of signal and reference peak would be equal to 4*5=20 and graph
would take smoother form:
Sine by Sine in Phase multiplication
300000
200000
100000
0
1 5 9 13172125293337414549535761
Figure 4.4 A multiplication of two sine waves with zero phase difference
For this reason, revision of the AD630 modulator is needed.
The main diagram of AD630 that are presented in documentation in Figure 4.5a can
be converted into more recognisable version of Figure 4.5b [14]:
a)
b)
Figure 4.5 a) Main and b) simplified diagrams of AD630 from Datasheet [14]
But, one thing to mention from Figure 4.5a, is that comparator that takes
inputs 9 and 10 produces high and low signals regarding sign of the difference
voltage. And comparator is connected to switch A and B. Thereby, it is not direct
multiplication between reference and signal, but rather switch between input signals
of pin 1 and pin 17, more precisely between amplified signals.
Look at both figures 4.5a (or 4.5b), and try to connect 19, 20 with 15 pin,
while 14 pin to the ground. 19 and 20 pins are responsible for negative inputs of
amplifiers A and B. If connected to 15 pins, they will be also joined with 16 pin
across 5kΩ, feedback of operational amplifier, and through 14 pin to the ground via
10kΩ resistor.
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Now, if look at the figure 4.6 below, which is also given in documentation, it
can be seen that it is simple operational amplifier diagram with
10𝑘Ω
5𝑘Ω
= 2 gain, where
19, 20, 15 connected the input Vin. 2 and 18 pins are similar to 1 and 17 pins, but
without high current protection resistors.
Figure 4.6 AD 630 Interconnection
Channel A and Channel B work in dependence of comparator. If comparator
output is 1, then Channel A is selected, if 0 then channel B. Figure can be cleared
(remember that black points are joints, i.e. for channel A, negative input 20 is
connected to 15 - creating single chain - and to the input Vin through 5kΩ; likewise
negative input 20 is connected to output 13 through 10kΩ) from unused pins, and
Channel A and Channel B becomes:
a
b
Figure 4.7 Channel A (a) and Channel B(b)
𝑅
Channel A is inverting amplifier with 𝑉𝑜𝑢𝑡𝑝𝑢𝑡 = − 𝑅𝐹 ∙ 𝑉𝑖𝑛𝑝𝑢𝑡 = −2 ∙ 𝑉𝑖𝑛𝑝𝑢𝑡
𝐴
𝑅
Channel B is non-inverting amplifier with 𝑉𝑜𝑢𝑡𝑝𝑢𝑡 = (1 + 𝑅𝐹 ) ∙ 𝑉𝑖𝑛𝑝𝑢𝑡 =
𝐵
(1 + 1) ∙ 𝑉𝑖𝑛𝑝𝑢𝑡 = +2 ∙ 𝑉𝑖𝑛𝑝𝑢𝑡
11 and 8 are power supply pins.
If returning back to Sengupta et al diagram in figure 4.1, everything is
connected in correct way, apart from pin 12 which is connected to pin 13. There
seems to be no apparent reason for that.
The logic can be following: Pin 12 is comparator square wave output with the
same signal that drives A and B switch and hence synchronized high and low. The
whole point is that pin 13 output without comparator output 12 has amplitude which is
2 times bigger (due to internal gain) than Vin amplitude. For this reason, we had 8V
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in Proteus simulation with 4V input and 5V reference. So connecting 13 pin to 12, we
theoretically can eliminate second half, and consequently avoid 2 times gain.
1200
1200
1000
1000
800
800
600
600
400
400
200
200
0
0
1 5 9 13172125293337414549535761
1 5 9 13172125293337414549535761
Output pin 13
Average
Output pin 13 with comparator's Square Wave
Average
Figure 4.8 Example of y=±2x multiplied by in phase same frequency square wave
But, in practise frequency was 2 times of original reference frequency
(Nyquist frequency) or second period was not eliminated. Peak to peak voltage was
3.82 which was 1.91 times bigger of input signal.
Signal
Reference
Figure 4.9 10Hz Signal and reference
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Output
Figure 4.10 Reading responses from AD630. 20Hz output signal
Since it was unlikely that signal and reference would be in phase during testing,
output signal had mirrored periods corresponded to ±2.
However, phase of signal and reference can almost accidently coincide after several
probing.
Example below is for amplitude 305 mV sine wave input (peak to peak 611mV).
Signal
Figure 4.11 100Hz Input signal with 305mV amplitude
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Output
Figure 4.12 Close to in phase example
What can be noticed from the last graph, output response has peak to peak voltage of
680mV. It was halved by means of ±2 ∙ Vinput being almost in phase. But still
positive amplitude is 2 times bigger than input signal amplitude. Apart from that
output has DC offset of 276-(-6) =282V (where –6 is an offset of original input). But
whether we can treat this offset as input signal amplitude? No, we cannot, since it is
not sine by sine multiplication, but comparator’s square wave output and sine wave
input multiplication. (Unfortunately, it was initially assumed that quadrature shifted
signals could produce DC offset for X and Y, and resulting Z can be estimated then.
So phase shift or parallel shifted signal path was implemented. See Abstract III).
However what we know is that when input signal and reference are in phase
amplitude of the output signal is rectified and corresponds to 2 times amplitude of the
original signal. And if output signal is smoothed by simple RC low pass filter with cut
1
off frequency 𝑓 = 2𝜋𝑅𝐶 then original value of Vinput can be eventually derived. For
200Hz, RC ≈ 0.0008, for instance R=800, C=1uF.
Vin
R
Vin
Vout
C
R
Frequencies
higher than
200Hz
0
Vout
C
Frequencies
lower than
200Hz
0
Figure 4.11 Simple RC filter
Filtering is achieved by the reason of charge and discharge time of capacitor.
Figure 4.11b is a converted form of RC filter on Figure 4.11a where ground is
replaced by 0 power rails. In this form, it is apparent that RC filter is a simple voltage
divider with output voltage taken from the capacitor. And it takes time for capacitor to
gain voltage and give it back. So it just does not have enough time for capacitor to
gain full potential when frequency rises to certain level and, as consequence, voltage
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value across it starts decreasing exponentially. But how to determine edge frequency
1
at which a significant decrease happens? We have capacitor impedance 𝑍𝐶 = 𝑗𝜔𝐶 and
𝑍𝐶
output voltage from divider: 𝑉𝑜𝑢𝑡 (𝑡) = 𝑅+𝑍 𝑉𝑖𝑛 (𝑡) =
𝐶
1
𝑗𝜔𝐶
1
𝑅+
𝑗𝜔𝐶
1
𝑉𝑖𝑛 (𝑡) = 1+𝑗𝜔𝑅𝐶 𝑉𝑖𝑛 (𝑡).
As can be seen the value of Vout (t) decreases with increasing frequency. If
1
frequency is less than f = 2πRC, the decrease is insignificant and Vout (t) is close to
1
Vin (t), if more than f = 2πRC, then jωRC part starts dominating and equation takes
exponential form.
In the Analog design, 10kΩ is used for filtering as reference resistor and
switchable capacitors from 100uF to 1pF are used to smooth input voltage.
Eventually, the Lock-in amplifier that was shown on Figure 4.1 takes distinct
form:
x2
Vsignal
++G1
Vout
x(-2)
-G2
Vreference
Figure 4.13
Experiment with low signal and prevailing noise:
15mV amplitude signal
incorporated with 20mv
amplitude noise. Original
signal frequency is 180Hz.
(much higher 360 kHz due to
noise)
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Increased ~9.5 times with 5.6
kΩ resistor gain (for 9.98
times 5.49 kΩ should be used)
Output frequency - 360Hz (2
times of original signal).
Almost in phase scenario, but
has decent negative offset.
960mv is ~2 times increased
positive amplitude plus
negative offset incorporated
with noise.
271mV recovered after RC
filter. High frequency noise
eliminated
Second series RC filter applied
to have clearer DC offset.
271
≈ 28.5𝑚𝑉
9.5
30
= 14.25mV
2
The error in final result is most
likely caused by initial phase
difference.
Figure 4.12 A final experiment with prevailing noise for Analog Lock-in Amplifier
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CONCLUSION
Throughout all the research work done on building Lock-in amplifier, it has
been becoming clearer and clearer that Lock-in amplification is essentially a simple
technique, however, which embraces and utilizes all the basic characteristics of
sinusoidal signals. In fact an Implementation of digital Lock-in amplifier can be
considered as cornerstone for processing digitalized sine waves. It includes signal
generating techniques, calculation of input phase, frequency, sine wave digitizing
features, analysis of modulating and filtering methods, creation of special clocks and
counters for producing arbitrary frequency signals and etc. This list can be well
expanded depending on design goals.
In concern of FPGA, designer experience is relevant. FPGA’s low level logic
programming methods can be helpful especially concerning optimization of
calculation speed and fast signals propagation, but in the same time can slow down
design process as a whole. Obstacles that can arise sometimes from elementary
operations are capable of consuming most of the production time. Thus, experience is
important factor.
Eventually, Digital FPGA Lock-in amplifier design solution was developed.
Even though space occupation was relatively high, but sufficient reserve still
remained.
To compare similar but slightly different way of signal and reference
modulating Analog design was implemented
As can be noticed for the Thesis, both Analog and Digital designs never faced
real life signals, but were fed by 10-20mV limits from Signal Generator incorporated
with 10mV noise from same source. So, it is too early to say something about real-life
experiments.
Further Improvements:
Digital Design can be improved by adding second order or third order
approach to the time constant in the case of Exponential Decay filter realization.
VGA or Ethernet data channel can be used further for connecting FPGA board
to Personal Computer, to draw graphs and collect results. Spartan 3E XC3S500 board
has the entire interface needed.
Regarding Analog desing, less improvements can be made. Phase shift for
quadrature shifted signal that was embedded to the design (see abstract III) without
good reason can be potentially used to adjust signal and reference to be in phase, if
they are not.
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REFERENCES
[1] J. Gaspar, C.F. Chen, A. Gordillo, M. Hepp, P. Ferreira & C. Marquez, "Digital Lock-in Amplifier:
study, design and development with a digital signal processor," Microprocessors and Microsystems,
vol. 28, no. 4, p. 157–162, May 20, 2004.
[2] L.E. Bengtsson, &, "A microcontroller-based lock-in amplifier for sub-milliohm resistance
measurements," Rev. Scientific Instruments, vol. 83, pp. 7–103, Jul 6, 2004.
[3] X. Wang, "Sensitive digital lock-in amplifier using a personal computer," Rev. Scientific
Instruments, vol. 61, no. 7, p. 1999, Jul. 2006.
[4] A.A. Dorrington & R. Künnemeyer, "A simple microcontroller based digital lock-in amplifier for
the detection of low level optical signals," in Proceedings of the First IEEE International Workshop on
Electronic Design, Test and Applications (DELTA ‘02), Christchurch, New Zealand,, Washington, DC,
USA: IEEE computer society, pp. 486–488, Jan 29-31, 2002.
[5] Y. Li & W. Chu, "A New Non-Restoring Square Root Algorithm and Its VLSI Implementations,"
in Proceedings: IEEE International Conference on Computer Design: VLSI in Computers and
Processors,, Austin, Texas: IEEE Computer Society Press, pp. 538 – 544, Oct 7-9, 1996.
[6] G. Shuli, D. Al-khalili & N.Chabini, "An improved BCD adder using 6-LUT FPGAs," in New
Circuits and Systems Conference (NEWCAS), 2012 IEEE 10th International, IEEE, pp. 13 – 16, Jun
17-20, 2012.
[7] Xilinx LTD, “Spartan 3E FPGA Starter Kit Board User Guide” UG230 (v1.2) datasheet, Jan 20,
2011 [Revised May, 2014].
[8] Xilinx LTD, “Picoblaze Amplifier and Converter Control for Spartan-3E Starter Kit”, datasheet,
Feb 23, 2006.[Revised June, 2014]
[9] http://www.ni.com/white-paper/5516/en/ Understanding Direct Digital Synthesis (DDS). Publish
Date: Nov 21, 2013
[10] M.G. Gayathri, "Design of All Digital Phase Locked Loop in VHDL," Int. J. Eng. Research
Applications, vol. 3, no. 4, pp. 1074–1076, Jul-Aug. 2013. [5] Brown, R.G., Exponential smoothing for
predicting demand
[11] D.J. Lilja & S.S. Sapatnekar, Designing Digital Computer Systems with Verilog., Cambridge, UK:
Cambridge University Press, 2005, p. 176.
[12] S.K. Sengupta, J.M. Farnham & J.E. Whitten, "A Simple Low-Cost Lock-In Amplifier for the
Laboratory," J. Chemiacal Education, vol. 82, no. 9, pp. 1399–1401, Jan. 2012.
[13] Analog Devices, “Low Cost Low Power Instrumentation Amplifier” AD620 datasheet, 2011
[Revised June, 2014].
[14] Analog Devices, “Balanced Modulator/Demodulator” AD630 datasheet, 2004 [Revised June,
2014].
[15] H. Golnabi & A. Ashrafi, "Phase-shift generation and monitoring by a simple circuit," Rev.
Scientific Instruments, vol. 67, no. 5, pp. 2017–2019, May 1996.
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ABSTRACT I
Predicted Milestones from interim report with actual dates (in italics):
Final Revision done
June 8, 2014 - June 16, 2014
Hardware and Software Development done
August 3, 2014 - August 10, 2014
Testing and Optimization finished
August 24, 2014 - August 26, 2014
Finished Master Thesis
September 14, 2014 - August 30, 2014
Notice: At first, it was assumed that the deadline for Master Thesis submission is in
the middle of September. And schedule for Master Thesis preparation was initially
organised regarding these dates.
It was also assumed that focus only would be on digital design. However both were
implemented:
Circuit design and Soldering done
July 27, 2014
Testing and Optimization finished
August 22, 2014
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ABSTRACT II
Bipolar -15 to 15V to Unipolar 0.4 to 2.9V Conversion Resistor Chain:
Figure A.1 Spice circuit simulation
Transient Response:
Figure A.2 Spice circuit simulation: transient response
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ABSTRACT III
Figure A.3 Phase shift producing circuit with analog LM565 PLL [15]. 8-9 terminals are connected to
variable 0-5kΩ resistor and 0.5uF capacitor circuit. Phase shift is controlled by altering resistor value.
6-7 outputs terminals has voltage that is proportional to phase shift, 0V corresponds to 90 o phase shift.
This voltage after being filtered and amplified is feed to LCD display through ADC converter and to
LCD indicator. But it can be measured by voltmeter as well. So, only highlighted left half is used in
analog Lock-in Amplifier design.
Figure A.4 Proteus ISIS diagram for Analog Lock-in Amplifier. Adjustable resistors and capacitors are
used for input instrumentation amplifier gain and RC filter cut-off frequency respectively.
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Figure A.5 Proteus ARES diagram for Analog Lock-in Amplifier
Figure A.6 Final Analog Lock-in amplifier board
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