Memory Interconnection Technologies in FPGAs
1. Introduction
A Field-Programmable Gate Array (FPGA) is an integrated circuit designed to be configured by a
customer or a designer after manufacturing. FPGAs are gate-array-like devices, and they are typically
used to implement multi-level logic functions. The implementation process is based on the
interconnection of repeated arrays of identical blocks/cells. Several types of interconnection technology
of FPGAs are in wide use today. These include SRAM (Static RAM Cells), Anti-fuse, EPROM Transistor,
EEPROM Transistor… Each one has many characteristics and advantages. The choice basically depends
on the final use.
This report is organised as follows. Section 2 describes the most known types of interconnection
technology used for FPGAs. Sections 3 and 4 present the SRAM and DRAM memory interfaces,
respectively. Sections 5 and 6 summarise technical details of Xilinx and Altera FPGAs respectively.
Finally, Section 7 concludes the report.
2. Types of Interconnection Technology
There are many techniques of memory interconnection technology used for FPGAs. The most common
ones are SRAM/DRAM, Flash, and anti-fuse. Below, we overview these 3 and other techniques.

Anti-fuse: The configuration memory of the FPGA consists of fuses. During the configuration
process fuses are left intact or are destroyed by the application of an adequate voltage, in order
to disconnect two elements. Programming is final and non-reversible. It offers a low capacity in
terms of logical resources. The two main players in this market are Actel [4] and Lattice [5].

SRAM/DRAM: Static/Dynamic Random Access Memory. Given its volatile nature, these
components must be reprogrammed each time the FPGA is powered on. Consequently, the
configuration data are stored in a non-volatile external memory (usually PROM) which is read at
start-up by the FPGA. The advantage of this technology is its integration density, thereby
producing components of high capacity while maintaining low prices. Primary manufacturers are
Xilinx [2], Altera [3], Actel and Atmel [6].

Flash: The flash memory technology is at the intersection of the fuse and SRAM. Indeed, it
combines non-volatile fuses and re-programmability of SRAM. Such a component requires no
external memory for storing configuration. Progress made on the flash memory in recent years
can achieve integration densities offering an interesting alternative to SRAM-based FPGAs.
Finally, the flash memory is not as sensitive to disturbance as is the SRAM. Actel and Lattice
offer components based on this technology.
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
PROM: Programmable Read-Only Memory. They are one-time programmable and come in a
plastic packaging. PROMs are usually used with SRAMs.

EPROM: Erasable Programmable Read-Only Memory. EPROM cells are electrically programmed
in a device programmer. Some EPROM-based devices are erasable using ultra-violet (UV) light if
they are in a windowed package. However, some have plastic packages and cannot be UV
erased. Vendors using EPROM technology are: Xilinx, Altera, Cypress [7], Atmel …

EEPROM: Electrically Erasable Programmable Read-Only Memory. They can be erased, even in
plastic packages. Some but not all EEPROM devices can be in-system programmed.

Fuse: A fuse is a metal link that can be programmed by passing a current through the fusible
link. It is one-time programmable. Texas Instruments [8] is using fuse technology.
3. SRAM Based FPGA Interconnection
SRAM devices offer extremely fast access times—approximately four times faster than DRAM—but are
much more expensive to produce [3]. Unlike DRAM, SRAM does not need to be refreshed periodically to
prevent data loss through leakage [3]. SRAM devices are capable of storing data as long as the device is
supplied with power. If the power is turned off, the contents are lost. Typical FPGA systems require both
SRAM (for performance-critical applications) and DRAM memory (for all other applications) [3]. A
common structure of SRAM consists of select lines and data access line for a memory cell (Figure 1) [1].
Figure 1: SRAM Storage Cell Array [1]
QDR and QDR II SRAM Devices allow two ports to run independently at DDR, which results in four data
items per clock cycle. QDR SRAMs allow operation at data rates with frequency above 200 MHz which
maximizes bandwidth [3]. The QDR consortium, which consists of Cypress Semiconductor, Integrated
Device Technology (IDT) [9], Micron Technology [10], and NEC Corporation [11], developed the QDR
architecture.
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ZBT SRAM is a synchronous burst SRAM with a simplified interface that provides higher bandwidth and
efficient bus utilization by eliminating turnaround cycles and idle cycles between read and write
operations. IDT, Micron, and Motorola [12] jointly developed the ZBT SRAM architecture, which is
optimized for networking and telecommunications applications [3].
The main vendors are: Cypress Semiconductors, NEC, Renesas and Samsung [13].
4. DRAM Based FPGA Interconnection
The dynamic RAM (DRAM) form of integrated circuit memory has surpassed all other random access
read/write memories in the number of cells or bits that can be placed in a memory chip. A DRAM
memory circuit uses charges on a capacitor to represent binary data values [1]. Figure 3 below shows an
example of a three transistor dynamic cell [1].
Figure 2: Three Transistor Dynamic RAM Cell [1]
DRAM devices are volatile memories offering a lower cost per bit than SRAM devices [3]. A compact
memory cell consisting of a capacitor and a transistor makes this possible over the six-transistor cell
used in SRAM. However, the capacitor will discharge, causing the memory cell to lose its state, which
means that DRAM memory needs to be refreshed periodically.
SDR SDRAM is the first generation of synchronous DRAM. It improves memory bandwidth over
extended data out (EDO) DRAM by offering single data rate (SDR) transfers up to once-per-clock cycle.
DDR SDRAM Double data rate (DDR) SDRAM is an evolution of SDR SDRAM. It offers higher performance
through increased bus speeds using a lower I/O voltage, and most importantly, data transfer on both
clock edges, doubling the raw bandwidth. DDR SDRAM is a widely established memory technology. It
offers the lowest cost per bit, due in part to its broad acceptance in almost any marketplace.
DDR2 SDRAM is an evolution of DDR SDRAM. It operates using a lower voltage. DDR2 SDRAM offers
increased densities and even higher performance through higher bus speeds and an optimized interface.
The advantages of DDR2 SDRAM architecture over DDR SDRAM architecture are summarized as follows:



Data rate speed ranges from 400 to 667 Mbps
Power is lower than DDR SDRAM due to reduced I/O and core voltage
Smaller footprint for FPGA packages
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DDR3 SDRAM is an improvement over its predecessor, DDR2 SDRAM. The primary benefit of DDR3
SDRAM is the ability to transfer at twice the data rate of DDR2 SDRAM, thus enabling higher bus rates
and higher peak rates than earlier memory technologies. In addition, the DDR3 SDRAM standard allows
for greater chip capacities. The advantages of DDR3 SDRAM architecture over DDR2 SDRAM architecture
are summarized as follows:



Data rate speed ranges from 800 to 1,600 Mbps
Device capacity ranges from 512 Mb to 8 Gb
Power is lower than DDR3 SDRAM due to reduced I/O and core voltage
RLDRAM (Reduced Latency Dynamic Random Access Memory) is a development of DDR SDRAM,
designed to address the low latency requirements of certain applications, such as packet buffers in highperformance line cards. RLDRAM has a high-performance DDR data bus and offers a non-multiplexed
address bus, reducing the number of clock cycles to initiate read or write applications. A banked
architecture also reduces access time. In some systems, RLDRAM eliminates the need for specialized
content-addressable memory (CAM) or SRAM [3].
The main vendors are: Micron Inc [14], Samsung and SK Hynix.
5. Xilinx FPGA Memory Technologies
Xilinx is one of the biggest FPGA producers with almost half of the US market. The company has
different FPGA devices with different characteristics. The table below summarizes the memory types
used for some and their corresponding data transfer rates and frequencies [2].
Memory Type
Device
7 Series
Virtex-6
Spartan-6
Virtex-5
DDR3
SDRAM
DDR2
SDRAM
DDR
SDRAM
LPDDR
SDRAM
LPDDR2
SDRAM
QDR II/QDRII+
SRAM
RLDRAM
II
RLDRAM
3
1866 Mbps
800 Mbps
-
-
800 Mbps
2 x 1100 Mbps
1066 Mbps
1600 Mbps
933 MHz
400 MHz
400 MHz
550 MHz
533 MHz
800MHz
1066 Mbps
800 Mbps
2 x 800 Mbps
1000 Mbps
533 MHz
400 MHz
-
-
-
400 MHz
500 MHz
-
800 Mbps
800 Mbps
400 Mbps
400 Mbps
400 MHz
400 MHz
200 MHz
200 MHz
-
-
-
-
800 Mbps
667 Mbps
400 Mbps
2 x 600 Mbps
667 Mbps
400 MHz
333 MHz
200 MHz
300 MHz
333 MHz
-
-
-
There exist several configuration storage devices for Xilinx FPGAs. Among them:

Platform Flash XL is the industry's fastest 128Mb configuration and storage device specially optimized
for high-performance Virtex-5 FPGA configuration.
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


Platform Flash is a single in-system programmable solution for configuring all Xilinx FPGAs with densities
up to 32Mb.
System ACE™ is used for system level solutions, high density, and multiple FPGAs.
Legacy PROMs provide a single solution for in-system and one-time programming configuration for
densities up to 16Mb.
6. Altera FPGA Memory Technologies
Like Xilinx, Altera provides different devices of FPGAs with different memory types. The table below
summarises the data transfer rate sand the frequencies of each device [3].
Memory Type
Device
Stratix V (1)
Stratix IV
Stratix III
Stratix II and
Stratix II GX
Stratix and
Stratix GX
Arria V (1)
Arria II GZ
Arria II GX
DDR3
SDRAM
DDR2
SDRAM
DDR
SDRAM
LPDDR2
SDRAM
MOBILE
DDR
2,132 Mbps
1,066 MHz
1,066 Mbps
533 MHz
1,066 Mbps
533 MHz
1,066 Mbps
400 MHz
800 Mbps
400 MHz
800 Mbps
400 MHz
400 Mbps
200 MHz
400 Mbps
200 MHz
-
667 Mbps
333 MHz
-
-
1,334 Mbps
667 MHz
800 Mbps
400 MHz
800 Mbps
400 MHz
800 Mbps
400 MHz
666 Mbps
333 MHz
666 Mbps
333 MHz
466 Mbps
200 MHz
-
-
-
-
-
-
-
400 Mbps
200 MHz
-
-
600 Mbps
300 MHz
400 Mbps
200 MHz
-
-
400 Mbps
200 MHz
-
800 Mbps
400 MHz
400 Mbps
200 MHz
-
-
-
-
-
-
-
-
-
-
400 Mbps
200 MHz
400 Mbps
200 MHz
QDRII
SRAM
QDRII+
SRAM
1,400 Mbps
350 MHz
1,400 Mbps
350 MHz
1,400 Mbps
350 MHz
2,200 Mbps
550 MHz
2,200 Mbps
550 MHz
1,600 Mbps
400 MHz
-
1,200 Mbps
300 MHz
1,200 Mbps
300 MHz
-
800 Mbps
200 MHz
-
1,600 Mbps
400 MHz
1,200 Mbps
300 MHz
1,000 Mbps
250 MHz
1,600 Mbps
400 MHz
1,400 Mbps
350 MHz
1,000 Mbps
250 MHz
-
-
-
RLDRAMII RLDRAMIII
1,067 Mbps
533 MHz
1,067 Mbps
533 MHz
800 Mbps
400 MHz
800 Mbps
400 MHz
700 Mbps
350 MHz
1,600 Mbps
800 MHz
-
-
Arria GX
-
Cyclone
V (1)
800 Mbps
400 MHz
800 Mbps
400 MHz
-
667 Mbps
333 MHz
-
-
-
-
-
Cyclone IV
-
400 Mbps
200 MHz
334 Mbps
167 MHz
-
-
-
-
668 Mbps
167 MHz
-
Cyclone III
LS
-
333 Mbps
167 MHz
300 Mbps
150 MHz
-
-
-
-
600 Mbps
150 MHz
-
Cyclone III
-
-
-
-
-
334 Mbps
167 MHz
333 Mbps
167 MHz
400 Mbps
200 MHz
400 Mbps
200 MHz
400 Mbps
200 MHz
-
Cyclone II
400 Mbps
200 MHz
333 Mbps
167 MHz
667 Mbps
333 MHz
667 Mbps
333 MHz
533 Mbps
267 MHz
-
-
-
-
-
-
-
-
-
-
HardCopy IV
HardCopy III
HardCopy II
1,067 Mbps
533 MHz
800 Mbps
400 MHz
-
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800 Mbps
400 MHz
800 Mbps
400 MHz
500 Mbps
250 MHz
-
668 Mbps
167 MHz
668 Mbps
167 MHz
1,200 Mbps
300 MHz
1,200 Mbps
300 MHz
1,000 Mbps
250 MHz
1,400 Mbps
350 MHz
1,400 Mbps
350 MHz
1,000 Mbps
250 MHz
Because SRAM memory is volatile, the SRAM cells must be loaded with configuration data each time the
device powers up. The enhanced configuration devices are ISP-capable through its Joint Test Action
Group (JTAG) interface. The enhanced configuration devices are divided into two major blocks, the
controller and the flash memory [3]. Because of its large flash memory size and decompression feature,
enhanced configuration devices hold configuration data for one or multiple Altera FPGAs. After
configuration, access to the flash memory is through the external flash interface of the enhanced
configuration devices. Fast passive parallel (FPP) configuration, where configuration data is sent bytewide on the DATA pins every clock cycle, is also supported for fast configuration times [3].
7. Conclusion
From The tables in Sections 5 and 6, it is clear that DRAM based FPGA memory interconnecion is the
most used. Anti-fuse is not used for today’s high speed FPGAs because of long programming time, they
are used mostly for Flash Memories because there is very low error probability in this method. But
DRAM/SRAM based FPGA technique is a very fast method, however, it suffers from higher error rate in
programing and there are many techniques recently offered to overcome this problem such as SEU
Mitigation Solution in high/architectural level description and fault injection in the FPGA bitstream [15].
References
[1] Randall L. GEIGER, Phillip E. ALLEN and Noel R. STRADER. “VLSI Design Techniques for Analog and
Digital Circuits”. McGraw-Hill. 1990
[2] http://www.xilinx.com
[3] http://www.altera.com
[4] http://www.actel.com/
[5] http://www.latticesemi.com/
[6] http://www.atmel.ca/
[7] http://www.cypres.cc/
[8] http://www.ti.com/
[9] http://www.idt.com/
[10] http://www.micron.com/
[11] http://www.nec.co.jp/press/en/0204/1501.html
[12] http://www.motorola.ca/
[13] http://www.samsung.com
[14] http://www.micron.com/
[15] F. L. Kastensmidt, L. Carro and R. Augusto. “Fault-Tolerance Techniques for SRAM-Based FPGAs.”
Springer. 2006.
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