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Differential Amplifier Implementation on ICs Difference Amplifiers are quite popular as building blocks of ICs They are much less sensitive to noise (CMRR >>1). They allow direct coupling of stages (no need for coupling and/or by-pass capacitors). Typical implementation in an IC Two outputs Single ended output Need to get rid of R’s Biasing with a Current Mirror – Bias VG is the bias voltage at gates of Q1 and Q2 VG = 0 if no bias is applied (e.g., first stage) Bias Half circuit (common mode) VGS = VG − VS Current mirror is in the Source Circuit 0.5 I o = I D = 1 k n′ (VGS − Vtn ) 2 (1 + λVDS ) 2 VDD = I D RD + VDS + VS DS-KVL Can be solved to find VDS and VS (and VGS) Does not require a precise circuit to set VG exactly (VS gets adjusted automatically) Biasing with a Current Mirror – Small Signal Small Signal Analyzed before (replace RSS with ro3) Current mirror is in the Source Circuit Biasing with a Current Mirror Why is the current mirror in the source circuit? Current mirror is in the Drain Circuit Current mirror is in the Source Circuit Recall: For CS amplifier we argued that current source should not be located in the source circuit! Biasing with a Current Mirror Why is the current mirror in the source circuit? Difference Amp. ro3 does not affect the differential gain Need a large “RSS ” to get a high CMRR |A | CMRR = d = 1 + 2 g m1 RSS + RD / ro1 | Ac | = 1 + 2 g m1ro 3 + RD / ro1 CS Amp. With current source in the source circuit A large resistor in the source circuit reduces the gain substantially Av = − g m1 R D 1 + g m1ro 2 + R D / ro1 Biasing with a Current Mirror Why is the current mirror in the source circuit? Difference Amp. CS Amp. With current source in the drain circuit It does not require a precise circuit to set VG exactly (VS gets adjusted automatically) We can set VG = 0 . Ideal for first stage as it would not require coupling capacitors Requires precise bias voltage for Q1 Difference amplifiers with active load (differential output) We need to replace RD with active loads. Choices are: Diode Connected transistor* RD= 1/gm Not useful as the gain is Ad = − g m R D Large gain as RD= ro Ad = − g m R D But above is really a leg of a current mirror! *See Sedra & Smith, Problem 8.20 Note: Circuit is incorrect. Gates Q3 and Q4 should NOT be connected to each other Current source (mirror) as active load For NMOS difference amplifier, we need PMOS load as Q1 should see the drain of Q3 (in order to see large R) Bias current should flow into the drain of Q1 (and thus out of drain of Q3) For PMOS difference amplifier, we need NMOS load. This is Similar to a CS amplifier. Q3 and Q4 should be identical to get a symmetric circuit Current source (mirror) as active load Requires careful biasing • Q1 and Q2 are identical and VGS1 = VGS 2 • Thus, I D 2 = I D1 = I o / 2 • I D 3 = I D1 = I o / 2 • I D4 = I D2 = Io / 2 • Note: VSG 3 = VSG 3 = VDD − VG 3 Q3 and Q4 are identical Q1 and Q2 are identical Q3 and Q4 should be identical. Q3, Q4, and Q5 parameters (i.e., W/L) and VG3 should be chosen carefully such that I D3 = I D 4 = I o / 2 Current source (mirror) as active load Example Implementation on IC PMOS Amps NMOS Amps, PMOS current source (active load) NMOS current source (active load) Current source (mirror) as active load Small Signal Response Differential Mode vo1 = − g m1ro3 (−0.5vd ) = 0.5 g m1ro3vd vo 2 = −vo1 = −0.5 g m1ro3vd Ad = Common Mode vo 2 − vo1 = − g m1r o 3 vd vo1 g m1ro 3 =− 1 + 2 g m1ro 5 + ro 3 / ro1 vc vo1 = vo 2 Ac = vo 2 − vo1 =0 vc CMRR = | Ad | =∞ | Ac | Cascode Difference amplifier ro 5 + ro 7 + g m 5 ro 5 ro 7 ≈ g m 5 ro 5 ro 7 Small signal Cascode Difference amplifier* Differential Mode vo1 = − g m1 ( g m 3 ro3 ro1 || g m 5 ro5 ro7 )(−0.5vd ) vo 2 = −vo1 Ad = vo 2 − vo1 = − g m1 ( g m 3 ro3 ro1 || g m 5 ro5 ro7 ) vd Common Mode vo1 = vo 2 Ac = * See Sedra & Smith, Chap 12.2 for a folded cascode version vo 2 − vo1 =0 vc Exercise: Calculate vo1 for common mode Active load for a single-ended output Works fine but require biasing of Q3 and Q4 (i.e., VG3) “Popular” active load for single-ended output Does not require biasing of Q3 and Q4 (i.e., VG3) Gets a similar gain and CMRR But, circuit is NOT symmetric (half-circuit does not work!) Active load for a single-ended output Small Signal Note ro4 = ro3 and gm4 = gm3 Diode-connected transistor Active load for a single-ended output Small Signal Note ro4 = ro3 and gm4 = gm3 ro2 = ro1 and gm2 = gm1 Circuit is NOT symmetric CANNOT use “half-circuit” Differential Gain ro4 = ro3 and gm4 = gm3 ro2 = ro1 and gm2 = gm1 vgs1 = − 0.5vd − v5 vgs2 = + 0.5vd − v5 v g 3 − v5 Node vg3 g m 3v g 3 + g m1 (−0.5vd − v5 ) + Node vo g m 3v g 3 + Node v5 v5 v5 − v g 3 v5 − vo + + − g m1 (−0.5vd − v5 ) − g m1 (+0.5vd − v5 ) = 0 ro 5 ro1 ro1 ro1 =0 vo v −v + g m1 (+0.5vd − v5 ) + o 5 = 0 ro 3 ro1 Differential Gain Rearranging terms: 1 1 vg 3 g m 3 + + v5 − g m1 − = +0.5 g m1vd ro1 ro1 1 1 1 v g 3 ( g m 3 ) + v5 − g m1 − + vo + = −0.5 g m1vd ro1 ro 3 ro1 1 1 2 1 v g 3 − + v5 + 2 g m1 + + + vo − = 0 ro1 ro 5 ro1 ro1 Dropping 1/ro terms compared with gm v g 3 ( g m 3 ) + v5 (− g m1 ) = +0.5 g m1vd 1 1 v g 3 ( g m 3 ) + v5 (− g m1 ) + vo + = −0.5 g m1vd ro 3 ro1 1 1 v g 3 − + v5 (+ 2 g m1 ) + vo − = 0 ro1 ro1 Dropping v5 /ro5 term implies that very little current flows into ro5 (can remove ro5 from the circuit as done in the textbook) Differential Gain v g 3 ( g m 3 ) + v5 (− g m1 ) = +0.5 g m1vd 1 1 v g 3 ( g m 3 ) + v5 (− g m1 ) + vo + = −0.5 g m1vd ro 3 ro1 1 1 v g 3 − + v5 (+ 2 g m1 ) + vo − = 0 ro1 ro1 Subtracting second equation from the first*: vo = − g m1vd ro1 || ro 3 ⇒ vo = − g m1 (ro1 || ro 3 )vd ⇒ Ad = − g m1 (ro1 || ro 3 ) Adding all three equations give: 2 g m 3v g 3 + vo vo = 0 ⇒ vg 3 = − ro 3 2 g m 3 ro 3 vg 3 = + Note: vg3 << vo g m1 (ro1 || ro 3 ) g m1 vd ≈ vd 2 g m 3 ro 3 4 g m 3 ro Textbook Eq. 7.1.40 is incorrect * This is sloppy math as if subtract 2nd equation from first before dropping ro terms, a vg3 term appears in the above equation. Fortunately, as vg3 << vo, ignoring vg3 term is justified Common-Mode Gain ro4 = ro3 and gm4 = gm3 ro2 = ro1 and gm2 = gm1 vgs1 = − 0.5vd − v5 vgs2 = + 0.5vd − v5 vg 3 − v5 Node vg3 g m 3vg 3 + g m1 (vc − v5 ) + Node vo g m 3v g 3 + Node v5 v5 v5 − vg 3 v5 − vo + + − g m1 (vc − v5 ) − g m1 (vc − v5 ) = 0 ro 5 ro1 ro1 ro1 =0 vo v −v + g m1 (vc − v5 ) + o 5 = 0 ro 3 ro1 Common-Mode Gain g m 3vg 3 + g m1 (vc − v5 ) + g m 3v g 3 + vg 3 − v5 ro1 =0 vo v −v + g m1 (vc − v5 ) + o 5 = 0 ro1 ro 3 v5 v5 − vg 3 v5 − vo + + − g m1 (vc − v5 ) − g m1 (vc − v5 ) = 0 ro 5 ro1 ro1 Subtracting second equation from the first and dropping 1/ro terms compared with gm vo =0 ⇒ ro1 || ro 3 Ac = 0 ⇒ CMRR = ∞ Solving equations without dropping 1/ro terms compared with gm vo = 1 2 g m 3 ro 5 vc ⇒ Ac = 1 2 g m 3 ro 5 ⇒ CMRR = 2 g m 3 ro 5 g m1 (ro1 || ro 3 ) Output Resistance Attach a source vx to the output and calculate ix) Node vg3 g m 3vg 3 + g m1 (−v5 ) + vg 3 − v5 ro1 =0 vx v −v + g m1 (−v5 ) + x 5 = ix ro1 ro 3 Node vx g m 3v g 3 + Node v5 v5 v5 − v g 3 v5 − v x + + − g m1 (−v5 ) − g m1 (−v5 ) = 0 ro 5 ro1 ro1 Subtracting second equation from the first and dropping 1/ro terms compared with gm vx = ix ro1 || ro 3 Ro = vx = ro1 || ro 3 ix