University of Hertfordshire
Faculty of Engineering and Technology Sciences
MSc in Radio and Mobile Communication Systems
WiMAX Base Station Waveform Synchronization Using Early/LateGate Synchronizer
Report by
Mohammed Ishaq Pasha
Supervisor
Pandelis Kourtessis
Date
September 2010
DECLARATION STATEMENT
I certify that the work submitted is my own and that any material derived or quoted from
the published or unpublished work of other persons has been duly acknowledged (ref.
UPR AS/C/6.1, Appendix I, Section 2 – Section on cheating and plagiarism)
Student Full Name: ISHAQ PASHA MOHAMMED
Student Registration Number: 08192081
Signed: …………………………………………………
Date: 01 August 2016
School of Engineering and Technology
MSc Final Year Project Report
ABSTRACT
WiMAX is the new wireless communication technology that has emerged, which
delivers high data rates and long coverage. Base station (BS) plays a very important
role in WiMAX. Waveform synchronization takes place in BS of WiMAX. This project
presents the waveform synchronization at BS of WiMAX using Early/Late-Gate
synchronizer technique. The most important part in synchronization is symbol timing
recovery which has been highlighted in this report. The project work has already been
done on this topic of symbol timing recovery. During synchronization the receiver clock
adjusted continuously in frequency and phase. This was done to optimize the sampling
instants of the received data signal and to compensate for frequency drifts between the
oscillators used in the transmitter and receiver timing recovery methods. This project
presents an early/late-gate circuit model, which was implemented on simulink®
software. Frequency and time domain analysis were used for simulation and testing of
the model.
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ACKNOWLEDGEMENTS
I would like to express my gratitude to my supervisor Dr Pandelis Kourtessis, for his
guidance and invaluable time spent on those numerous discussions we had. It is in
those fruitful discussions that I have learned may more things apart from project and I
am sure those will be helpful in future. Thanks for everything.
Finally I would like to thank my parents and friends, for their understanding and
motivation given to me during the pressured events in the process of completing the
project.
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TABLE OF CONTENTS
DECLARATION STATEMENT ....................................................................................... i
ABSTRACT .................................................................................................................... i
ACKNOWLEDGEMENTS.............................................................................................. ii
TABLE OF CONTENTS ............................................................................................... iii
LIST OF FIGURES ....................................................................................................... vi
GLOSSARY ................................................................................................................. ix
Chapter 1: INTRODUCTION ........................................................................................ 1
1.1 Project Introduction............................................................................................. 1
1.2 Project Aim and Objective .................................................................................. 1
Aim ....................................................................................................................... 1
Objective .............................................................................................................. 1
1.3 Project Overview ................................................................................................ 2
1.4 Report Structure ................................................................................................. 2
Chapter 2: Literature Review ........................................................................................ 4
2.1 Modulation .......................................................................................................... 4
2.1.1 Baseband and Bandpass Transmission ....................................................... 4
2.1.2 Baseband Transmission .............................................................................. 4
2.1.3 Bandpass Transmission............................................................................... 4
2.2 Receiver synchronization ................................................................................ 6
2.2.1 Coherent and Non-Coherent detection ........................................................ 6
2.3 Synchronization .................................................................................................. 6
2.3.1 Symbol Synchronization .............................................................................. 6
2.4 Phase-Locked Loop (PLL) .................................................................................. 7
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2.4.1 Operation of PLL.......................................................................................... 8
2.4.2 Properties of PLL ........................................................................................10
Chapter 3: Design and Development ...........................................................................11
3.1 Chapter Overview ..............................................................................................11
3.2 Symbol Timing Recovery ...................................................................................11
3.3 Operation of Mid-Symbol Sampling ...................................................................11
3.4 Early/Late-Gate Synchronizer ............................................................................12
3.4.1 Working ......................................................................................................12
3.4.2 Early/Late-Gate Theory...............................................................................14
3.4.3 Why Early/Late-Gate Synchronizer? ...........................................................16
3.4.4 Choice of Best Approach ............................................................................16
3.5 Hardware/Software Implementation ...................................................................17
Chapter 4: Matlab Implementation...............................................................................19
4.1 Simulink® Overview ..........................................................................................19
4.2 Block Parameters Setup ....................................................................................20
4.2.1 Bernoulli Binary Generator ..........................................................................20
4.2.2 Product .......................................................................................................21
4.2.3 Integrator Block...........................................................................................22
4.2.4 Transport Delay Block.................................................................................24
4.2.5 Pulse Generator Block ................................................................................25
4.2.6 Sample and Hold Block...............................................................................26
4.2.7 Absolute Value Block ..................................................................................27
4.2.8 Subtractor Block .........................................................................................28
4.2.9 Low-Pass Filter Block .................................................................................29
4.2.10 Voltage Controlled Clock Subsystem ........................................................30
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4.2.11 Scope Block ..............................................................................................32
4.2.12 Power Spectrum Block..............................................................................32
Chapter 5 Results and Discussions .............................................................................33
5.1 Input Data from Bernoulli Generator ..................................................................33
5.2 Integrators output ..............................................................................................34
5.3 Sample and Hold Output ...................................................................................35
5.5 Low Pass Filter Output (Control Voltage) ...........................................................35
4.6 Recovered Symbol Timing Signal ......................................................................36
Chapter 6 ....................................................................................................................38
6.1 Conclusion.........................................................................................................38
6.2 Future Development in synchronization .............................................................38
6.2.1 Future Development in WiMAX ...................................................................39
6.3 Other Points ......................................................................................................39
6.3.1 Project Planning..........................................................................................39
6.3.2 Issues Came Across ...................................................................................39
REFERENCES ............................................................................................................41
BIBLIOGRAPHY .........................................................................................................43
APPENDICES .............................................................................................................44
Appendix A ..............................................................................................................44
Appendix B ..............................................................................................................45
Appendix C ..............................................................................................................46
Appendix D ..............................................................................................................47
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LIST OF FIGURES
Figure 2-1 Baseband spectrum
[5] ............................................................................ 5
Figure 2-2 Double-Sideband Spectrums [5] .................................................................. 6
Figure 2-3 Schematic of the basic PLL [8]. ................................................................... 8
Figure 2-4 Block Diagram of phase-locked loop [9]. ..................................................... 8
Figure 2-5 Transfer funtion of VCO .............................................................................. 9
Figure 2-6 Phase Detector transfer function. ................................................................ 9
Figure 2-7 Scope of the static and dynamic limits of stability of a linear second-order
PLL [9].........................................................................................................................10
Figure 3-1 Symbol synchronization using mid-symbol values [9]. ................................12
Figure 3-2 Early/Late-Gate Data Synchronizer. ...........................................................13
Figure 3-3 Gate timing of the Early/late-gate circuit (a) Waveform for correct timing. (b)
Waveform for timing error ∆T. .....................................................................................13
Figure 3-4 The shaded areas show equal energy in both gates. Gates match symbol
transitions, no timing correction is necessary [12]. ......................................................14
Figure 3-5 The shaded areas show equal energy in both gates. Gates do not match
symbol transitions, but because the energy levels are equal for both gates, no timing
correction can be made [12]. .......................................................................................15
Figure 3-6 The shaded areas show unequal energy levels. Gates do not match symbol
transitions; therefore a timing correction is made [12]. .................................................15
Figure 3-7 The shaded areas show unequal energy levels. Gates do not match symbol
transitions, but the energy levels are not equal for both gates, therefore a timing
correction is made [12]. ...............................................................................................16
Figure 3-8 (a) Rectangular Signal Pulse. (b) Matched Filter Output [11]. .....................16
Figure 3-9 Early/Late-Gate Synchronizers [11]. ...........................................................18
Figure 3-10 Alternative method for Early/Late-Gate Synchronizer [11]. .......................18
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Figure 4-1 Simulation Model of Early-Late-Gate symbol timing recovery subsystem
based on Phase-Locked Loop .....................................................................................19
Figure 4-2 Bernoulli Binary Generator .........................................................................20
Figure 4-3 Bernoulli Binary Generator Block Parameters ............................................21
Figure 4-4 Product Block .............................................................................................21
Figure 4-5 Product Block Parameters ..........................................................................22
Figure 4-6 Integrator Block ..........................................................................................22
Figure 4-7 Integrator Block Parameters .......................................................................23
Figure 4-8 Transport Delay Block ................................................................................24
Figure 4-9 Transport Delay2 Block Parameters ...........................................................24
Figure 4-10 Transport Delay1 Block Parameters .........................................................25
Figure 4-11 Pulse Generator Block .............................................................................25
Figure 4-12 Pulse Generator Block Parameters ..........................................................26
Figure 4-13 Sample and Hold Block ............................................................................26
Figure 4-14 Sample and Hold Block Parameters .........................................................27
Figure 4-15 Absolute value Block ................................................................................28
Figure 4-16 Absolute Value Block Parameters ............................................................28
Figure 4-17 Subtractor Block .......................................................................................28
Figure 4-18 Subtractor Block Parameters....................................................................29
Figure 4-19 Low-Pass Filter Block ...............................................................................29
Figure 4-20 Low-Pass Filter Block Parameters............................................................30
Figure 4-21 Voltage Controlled Clock Block ................................................................31
Figure 4-22 Voltage Controlled Clock Block ................................................................31
Figure 4-23 Voltage Controlled Oscillator Block Parameters .......................................32
Figure 4-24 Scope Block .............................................................................................32
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Figure 4-25 Power Spectral Block ...............................................................................32
Figure 5-1 Time domain waveform of input data ..........................................................33
Figure 5-2 Input spectrum ...........................................................................................33
Figure 5-3 Integrators Output ......................................................................................34
Figure 5-4 Input Output Spectrum ...............................................................................34
Figure 5-5 Sample and Hold Output ............................................................................35
Figure 5-6 Low Pass Filter Output (Control Voltage) ...................................................36
Figure 5-7 Recovered Symbol Timing Waveforms.......................................................36
Figure 5-8 Recovered Symbol Timing during Lock Process ........................................36
Figure 5-9 Recovered Symbol Timing Output after Lock Loop ....................................37
Figure A-1 Gantt Chart ................................................................................................44
Figure B-1 Symbol Timing Synchronization .................................................................45
Figure B-2 Carrie Frequency Synchronizer Estimator ..................................................45
Figure C-1 WiMAX Physical Layer Simulation .............................................................46
Figure D-1 Simulink® Model of an analog PLL ............................................................47
Figure D-2 VCO output................................................................................................47
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GLOSSARY
WiMAX – Worldwide Interoperability for Microwave Access
PLL – Phase-Locked Loop
LAN – Local Area Network
MAN – Metropolitan Area Network
MAC – Media Access Control
BS – Base Station
SS – Subscriber Station
PAM – Pulse Amplitude Modulation
DSB – Double-sideband
NDA – Non-Data-Aided
DA – Data-Aided
PD – Phase Detector
LF – Loop Filter
VCO – Voltage-Controlled Oscillator
FM – Frequency Modulation
AC – Alternating Current
DC – Direct Current
SNR – Signal to Noise Ratio
VCC – Voltage Controlled Clock
APIs – Application Programming Interfaces
Abs – Absolute Value
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Chapter 1: INTRODUCTION
1.1 Project Introduction
This project is based on Wimax Base Station Waveform Synchronization which uses
Early-Late-Gate synchronizer (A method of basic PLL) for symbol timing recovery of
signal at the receiver. WiMAX is a new technology in wireless communication, which
delivers both high data rates and long coverage. With the approval of the new mobile
WiMAX standard (IEE802.16E 2005) at the beginning of the year 2006, this
technology has become even more exciting. For indoor applications and local area
network (LAN) WiFi technology was designed but WiMAX technology is optimized for
outdoor applications and metropolitan area network (MAN). Even it is expected that
the WiMAX technology will replace WiFi because its MAC layer supports more than
one physical layer mode, this feature not only enables companies to differentiate
their products from each other, but also makes WiMAX an adaptive technology that
can satisfy different needs depending on the application. Although WiMAX has these
advantages, its system complexity increases and new problems arise. One such
problem is timing and synchronization between a Base Station and subscriber
stations (SS’s) [1]. As far as this project concerned timing in base station is
considered.
To overcome this problem in WiMAX technology a method called PLL (Phase-Locked
Loop) is used for synchronization at the receiver. The main aim of this project is to
study the use of phase-locked loops (PLL) for synchronization in coherent modulation
schemes. Synchronization which is carried out at the receiver is of two types Carrier
synchronization and Symbol synchronization. Synchronization used for this project is
Symbol synchronization for waveform synchronization in WiMax Base Station. As this
project mainly deals with software, after the completion of research and design stage,
then the whole system will be implemented on Simulink®.
1.2 Project Aim and Objective
Aim
The main aim of this project is to establish early/late-gate synchronizer for WiMAX
base station waveform synchronization.
Objective
The following objectives are set in order to achieve the aim of this project:



To study and investigate various types of synchronization methods.
To study and investigate the operations of phase-locked loop and their
suitability for use in synchronization.
Investigate clock and symbol timing recovery techniques using PLL.
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


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Design a synchronizer model using PLL.
Implementation of design on Simulink® platform.
Test the designed model in order to get the appropriate results.
1.3 Project Overview
This Msc. Project deals with waveform synchronization in WiMAX base station using
ealy/late-gate synchronizer. Different stages have been involved in this project. First
stage was to investigate the various types of synchronization methods which are
suitable for timing recovery of signal and select the best suited synchronization
method for the given situation of the project.
Second stage was to investigate the operations of PLL and its implementation
according to the necessity of the project background. In this case early-late-gate
synchronizer circuit was chosen to obtain the waveform synchronization or the
symbol timing recovery of the signal at the receiver. After the selection of the method
for synchronization is done, then comes the next stage.
Verification of selected methodology comes under next stage, for the verification
purpose MATLAB simulation simulink® was used, where testing was carried out and
results obtained. This was the final stage of the project that includes the software
implementation.
1.4 Report Structure
Chapter 1: This chapter starts with the introduction of the chapter in which the
project’s background was discussed, that includes motivation behind the project and
the project’s aim and objective.
Chapter 2: This chapter presents literature review, which explains the topics related
to the project such as Bandpass and Baseband transmission, different types of
synchronization and the operation of Phase-Locked loops and its properties. This is
the most important chapter which gives the background information of topics related
to this project.
Chapter 3: This chapter gives the knowledge of different techniques of PLL used in
order to achieve the project aim. Early/late-gate and mid-symbol sampling has been
described and the best one is chosen to recover symbol time.
Chapter 4: Software implementation of chosen technique from chapter 3 has been
discussed in this chapter. Explanation of different block being used and setting up of
block parameters also included in this chapter.
Chapter 5: Information of results obtained while testing the model on simulink® is
given in this chapter. The outputs are shown in time domain and frequency spectrum.
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Chapter 6: Gives the analysis and discussions of the results obtained, it also discuss
and compares the practical and theoretical outputs.
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Chapter 2: Literature Review
2.1 Modulation
Modulation is the very important part of any communication systems. Modulation
refers to the modification of one signal’s characteristics in concern with another
signal. The modified signal is called the carrier, and the signal doing the modifying is
called the information signal. [2]
2.1.1 Baseband and Bandpass Transmission
There are many types of modulation techniques which are as follows:



Digital versus Analog modulation
Baseband versus Bandpass modulation
Linear versus Non-Linear modulation etc.
For the purpose of this project baseband versus bandpass modulation techniques is
taken into account. From these two modulation techniques the one which suits best
for this project is bandpass transmission; the reason for taking this transmission will
be discussed in the nest section.
There are two main rules for transmitting a digital data these are as follows:
Baseband and
Bandpass transmission.
2.1.2 Baseband Transmission
Determination of the spectrum of input bits to fit in a limited spectrum is referred to as
baseband transmission. Pulse amplitude modulation (PAM) is the commonly used
baseband modulation technique. Sequences of time translates are modulated by
data amplitude in PAM, which is of basic pulse. This is a form of linear modulation.
Baseband modulation is best suitable for analog signal as it has finite bandwidth. For
digital signals baseband transmission can transmits only a portion of it as it has
infinite bandwidth. Because of this limited channel bandwidth distortion is caused in
baseband transmission [3].
2.1.3 Bandpass Transmission
In bandpass transmission, before the signal is being transmitted over the channel,
the signals get modulated over a carrier of higher frequencies. The effect of
interferences is reduced in bandpass transmission and because of this it has an
advantage over baseband transmission. For signal processing the signals placed at
desired frequency for the purpose of filtering, amplification, and multiplexing in
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bandpass transmission. It maps digital information sequence into waveform. It has
one big disadvantage of having a transmission bandwidth which is double than the
baseband transmission bandwidth [4]. The waveform produced from bandpass
modulation is called double-sideband (DSB) modulated signal. The DSB can be
expressed as:
𝑥𝑐 (𝑡) = 𝑥(𝑡)𝑐𝑜𝑠2𝜋𝑓𝑐 𝑡
Equation 2-1
Where 𝑥(𝑡)the baseband is signal and cos 2 𝜋𝑓𝑐 𝑡 is the carrier wave.
The bandwidth of double-sideband is given as:
𝑊𝐷𝑆𝐵 = (𝑓𝑐 + 𝑓𝑚 ) − (𝑓𝑐 − 𝑓𝑚 ) = 2𝑓𝑚
Equation 2-2
Where 𝑓𝑐 is the frequency of the carrier 𝑓𝑚 is the highest frequency of the baseband
signal and 𝑓𝑐 ˃˃𝑓𝑚
Figure 2-1 Baseband spectrum
[5]
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Figure 2-2 Double-Sideband Spectrums [5]
The three qualities of the converted digital symbol which distinguish it from other
waveforms are;
Amplitude
Frequency and
Phase
2.2 Receiver synchronization
An incoming signal at the receiver in digital communication needs some degree of
synchronization. It was seen in section 2.1 that how bandpass modulation is
important than baseband modulation, and how the modulated signal have different
properties which differentiate other waveforms. In this section it will be seen how
these properties are used for demodulation and synchronization at the receiver.
2.2.1 Coherent and Non-Coherent detection
In coherent detection receiver computes decision variables based on the recovery of
the full electric field, which contains both amplitude and phase information [7].
Whereas in non-coherent detection the receiver computes decision variables based
on a measurement of signal energy [7]. Coherent detection is used for this project
because it allocates maximum flexibility in modulation design, because the
information can be encoded in amplitude and phase [7].
2.3 Synchronization
Two digital systems communicate only when the receiver’s clock is synchronized with
the transmitter’s clock. Synchronization is the process by which receiving system
establishes a common time base with the transmitter. Methods like pilot tones and
preambles were traditionally used to synchronize digital systems. Due to difficulty of
modern communication systems, dynamic synchronization needs to happen on
several levels [6]. These can be broadly categorized into four groups they are as
follows:
Carrier synchronization
Clock synchronization
Sequence synchronization
Network Synchronization
2.3.1 Symbol Synchronization
In digital communication the most important synchronization is symbol
synchronization, regardless of whether baseband or bandpass transmission is used
and whether coherent or non-coherent detection is used. In symbol synchronization
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the symbol timing from the received signal is extracted in order to synchronously
sample the output of the demodulator by taking into account any propagation delays
that might have occurred and which is usually unidentified by the receiver [5]. This
process is carried out by symbol and data synchroniser. There are two dissimilar
techniques of symbol synchroniser first one is non-data-aided (NDA) where the
receiver knows nothing about the actual data sequence. Second one is data-aided
(DA) which uses known information about the data stream to perform
synchronization. This knowledge is acquired by feeding back decisions on received
data or a know sequence has been injected into the data stream [5]. The symbol
synchronization can be classified into tow basic groups they are:
Open-loop symbol synchronizer and
Closed-loop symbol synchronizer
Open-loop synchronizer circuit recover a replica of the transmitter data clock output
directly from operation on the incoming data stream, whereas the closed-loop
synchronizer circuit attempt to lock a local data clock to the incoming signal by use of
comparative measurements on the local and incoming signal. Closed-loop methods
are more accurate, but they are more expensive and complex to implement.
Non-data-aided closed-loop symbol synchronisers best suits to achieve the aim of
the project. It will be seen later how these types of circuits can be designed by using
phase-locked loops.
2.4 Phase-Locked Loop (PLL)
De Bellescize, a French engineer invented PLL in the year 1932. PLL is at the heart
of almost all synchronization circuit. Though recognising this loop is difficult in
contemporary digital receivers, but its basic functional equivalent is always present.
PLL are servo-control loops. The parameters which control PLL are the phase of a
locally generated replica of the incoming carrier signal. For designing a non-dataaided closed-loop symbol synchronizer using PLL, the structure of the PLL was
discussed in this section. It has three critical components which are as follows:
Phase detector
Loop filter and
Voltage-Controlled Oscillator (VCO).
It can be shown in diagrams shown below:
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Figure 2-3 Schematic of the basic PLL [8].
Figure 2-4 Block Diagram of phase-locked loop [9].
Where: 𝑢1 (𝑡) is the reference or input signal
𝜔1 is the output signal of the VCO
𝑢2 (𝑡) is the output signal of the VCO
𝜔2
is the angular frequency of the output signal
𝑢𝑑 (𝑡) is the output signal of the phase detector
𝑢𝑓 (𝑡) is the output signal of the loop filter
𝜃𝑒
is the phase error or phase difference between 𝑢1 (𝑡) and 𝑢2 (𝑡)
2.4.1 Operation of PLL
A measurement of the difference between the phase of an incoming signal and the
local replica is done by using phase detector. In loop filter, due to the changes in the
incoming signal and local replica, the phase difference or phase error becomes a
time varying signal. PLL’s responses to the variations in the error signal are governed
by loop filter. A good loop should not response much to the receiver noise and should
look at the changes in the incoming signal. VCO a sinusoidal oscillator produces
carrier replica. The frequency of the VCO is controlled by voltage level at the input
[5]. At an angular frequency of 𝜔2 VCO starts oscillating, which is determined by the
output of the loop filter 𝑢𝑓 (𝑡). Hence the angular frequency of the VCO is given by:
𝜔2 (𝑡) = 𝜔0 + 𝐾0 𝑢𝑓 (𝑡)
Equation 2-3
Where 𝜔0 , is the centre frequency of the VCO, and 𝑘0 is the VCO gain.
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Figure 2-5 Transfer funtion of VCO
The phase detector develops an output signal 𝑢𝑑 (𝑡) by comparing the phase of the
output signal with the phase of the reference signal, and the output signal is
approximately proportional to the phase error 𝜃𝑒 .
𝑢𝑑 (𝑡) = 𝐾𝑑 𝜃𝑒 (𝑡)
Equation 2-4
Where, 𝐾𝑑 , represents the gain of the phase detector.
Figure 2-6 Phase Detector transfer function.
From PD the AC and DC components of the output signal are removed by loop filter.
When angular frequency of the input signal 𝑢𝑓 (𝑡) equals to centre frequency 𝜔0 ,
VCO will operate at its centre frequency this can happen only when phase error 𝜃𝑒
and output signal 𝑢𝑑 of PD is zero. Phase-locked loop was the term used when VCO
operates at its centre frequency of the input signal. If the phase error 𝜃𝑒 is not zero,
then a nonzero output signal 𝑢𝑑 would develop causing some delay at the loop filter.
This would result in VCO changing its operating frequency in such a way that the
error gets vanished [9].
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2.4.2 Properties of PLL
There are a number of parameters of the Phase-Locked loops, which need to be
considered in order to make sure the optimum performance. Since an in detail
understanding of these parameters will be outside the range of this report, only a
brief definition of each property was given.




PLL operation can be statically stable in frequency range called the
hold range ∆𝜔𝐻 . PLL is temporarily stable in this range.
The range in which the PLL is always locked is the pull-in range ∆𝜔𝑃 .
In this range the procedure can be quite slow
For stable operation of PLL there is a dynamic limit which is the pullout range ∆𝜔𝑃𝑂 . If tracking is lost the PLL is locked in this range and
also the pull-in process slows down.
Between reference frequency and output frequency PLL is locked in
one single-beat note this frequency range is the lock range ∆𝜔𝐿 . Lock
range is the range to which operation frequency of PLL is limited.
Figure 2-7 Scope of the static and dynamic limits of stability of a linear secondorder PLL [9].
In this chapter the importance of modulation techniques has been examined,
difference between baseband and bandpass transmission is also investigated.
Importance of synchronization in accurate sampling and to avoid loss and corruption
of data is also seen. Operation of Phase-Locked loops have been seen which gave a
good knowledge of how the PLL can be used to achieve synchronization at the
receiver.
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Chapter 3: Design and Development
3.1 Chapter Overview
In order to achieve any project it is very important to study its background theory in a
great depth, before its practical implementation on software. Chapter 2 provides the
in-depth knowledge of the synchronization which can be used to complete this
project. Importance of the different techniques for symbol timing recovery has been
discussed in this chapter, and then the best technique is selected for the design and
implementation for the project.
3.2 Symbol Timing Recovery
In modern digital communications the critical task at the receiver for reliable data
recovery is symbol timing recovery. There are different methods to recover the
symbol timing. That will be discussed later. It was seen in chapter 2 that the main
difficulty with open-loop symbol synchronisers is that they initiate a non-zero-mean
tracking error; this cannot be removed because the recovered data clock relies on
the incoming signal. Closed-loop synchronizers make use of relative measurements.
Because of this the receiver can track any drift, jitter or delay, occurred in the data
clock while transmitting information [5].
There are many methods to achieve symbol synchronization, but for the purpose of
this project only two of the methods which are widely used have been discussed in
this report. From these two methods the best method which suits for this project is
chosen. The following are the methods used for symbol synchronization.
Mid-symbol sampling
Early/Late-Gate synchronizer
3.3 Operation of Mid-Symbol Sampling
This method is used when the data are lowpass filtered e.g. by the root raised cosine
filter. The correlator output is then sampled at the end of each symbol period T,
which corresponds to the instants, 𝑡 = −2𝑇, −𝑇, 0. 𝑇, 2𝑇. If 0’s sequence is
transmitted, then the succeeding end-symbol amplitudes will be around -1. If 1’s
sequence is received, the end-symbol amplitudes will be around +1.
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Figure 3-1 Symbol synchronization using mid-symbol values [9].
The transitions between 1 and 0 and vice versa makes the data signal to cross
through zero, which was shown in figure 3-1. The zero crossing is in the centre of two
succeeding points, this happen because the symbol clock is well adjusted. This can
be labelled as end-symbol 1 and end symbol 0 in figure 3-1. The average of these
tow end-symbol time gives the calculated mid-symbol time. The theoretical location
of the zero-crossing is labelled mid-symbol (expected). Inaccuracy occurs and must
be corrected when the actual zero crossing of the symbol signal move away from the
precalculated value i.e. mid-symbol (actual). The timing error is the difference
between the actual and expected location of the mid-symbol. This timing error is
used to regulate the frequency of a local symbol clock generator. Zero crossing is
being used in mid-symbol synchronization. The timing information becomes
unavailable if a logical 1 is following another logical 1. It is same in sequence of 0’s
[9].
3.4 Early/Late-Gate Synchronizer
3.4.1 Working
Early/late-gate synchronizer is the most popular closed-loop synchronizer. This
synchronizer technique is very popular and older, which has been around for a long
time. The synchronizer operates by performing two separate integration of the
incoming signal energy over two different (𝑇 − 𝑑) second portions of a symbol
interval. The first integration which takes place at the early gate starts integration at
the loop’s best approximate of the beginning of a symbol period and integrates for
the next (𝑇 − 𝑑) seconds, the nominal time is zero. Second integration occurs at the
late gate, which delays the start of its integration for 𝑑 seconds, and integrates to the
end of the symbol period, the nominal time is 𝑇. The divergence in the absolute
values of the output of these two integrations, 𝑦1 and 𝑦2 , is a measure of the
receivers symbol timing error, and it can be fed back to the loops timing reference to
correct loop timing.
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Figure 3-2 Early/Late-Gate Data Synchronizer.
Early/late-gate synchronizers performance can be understood by referring to the
figure 3-3, in which it shows that in case of perfect synchronization both gates are
entirely within a signal symbol interval. In this case both integrators will accumulate
the same amount of signal, and their difference in error signal 𝑒 is zero. This shows
that the device is synchronized and stable; there is no need of synchronization.
Figure 3-3 Gate timing of the Early/late-gate circuit (a) Waveform for correct
timing. (b) Waveform for timing error ∆T.
In another case the receiver’s data clock is early when compared to the incoming
data. In this case the first portion of the early-gate falls in the previous bit interval,
while the late-gate is inside the current symbol. The late-gate integrator will gather
signal over its entire (𝑇 − 𝑑) integration interval, and the early-gate collected energy
is (𝑇 − 𝑑) − 2∆, where ∆ is the portion of the early-gate interval falling in the earlier
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bit interval. The error signal for this case would be 𝑒 = −2∆, which will lower the input
voltage to the VCO, which reduce the output frequency and retard the receiver’s
timing to bring it back toward the incoming signal’s bit timing. From figure 3-2 it is
seen that if the receiver’s timing had been late, the amounts of energy integrated in
the early gate and late gate would be reversed, as would the sign of the error signal.
Thus, late receiver timing produces an increase in the VCO input voltage, increasing
the output frequency and advancing the receiver’s timing toward that of the incoming
signal [5].
3.4.2 Early/Late-Gate Theory
The basic principle for this data synching technique is to compare the energy in the
first half of a symbol period to the energy in the last half of a symbol period. Thus
Early and Late gate, respectively. As the energy levels in these gates are compared
to each other there are four conditions that can happen:




The loop has locked to the symbol period. The energy levels are
equal. The symbol transition occurs between the early and late gate.
No timing correction is made for this condition [12].
Two identical symbols have been transmitted. The energy levels are
equal. This means that a symbol transition was not found in this
symbol period. No timing correction is made for this condition [12].
The energy in the early gate is greater than the energy in the late
gate. This means that there was a symbol transition in the last half of
a symbol period. A timing correction can now be made to sync up to
the symbol boundary [12].
The energy in the late gate is greater than the energy in the early
gate. This means that there was a symbol transition in the early gate.
A timing correction can now be made to sync up to the symbol
boundary [12]. These four cases are shown in figures given below.
Figure 3-4 The shaded areas show equal energy in both gates. Gates match
symbol transitions, no timing correction is necessary [12].
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Figure 3-5 The shaded areas show equal energy in both gates. Gates do not
match symbol transitions, but because the energy levels are equal for both
gates, no timing correction can be made [12].
Figure 3-6 The shaded areas show unequal energy levels. Gates do not match
symbol transitions; therefore a timing correction is made [12].
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Figure 3-7 The shaded areas show unequal energy levels. Gates do not match
symbol transitions, but the energy levels are not equal for both gates, therefore
a timing correction is made [12].
3.4.3 Why Early/Late-Gate Synchronizer?
It was seen in the previous sections that how the mid-symbol synchronizer compares
estimated and actual measurements done on the incoming signal to generated an
error signal while the other method early/late-gate method uses integrators to
compare the symbol energy and recover the correct timing. The following figure is
used to describe the early/late-gate method in depth.
Figure 3-8 (a) Rectangular Signal Pulse. (b) Matched Filter Output [11].
Consider a rectangular pulse 𝑠(𝑡), 0 ≤ 𝑡 ≤ 𝑇, filters output 𝑠(𝑡) attain its maximum
value at time 𝑡 = 𝑇, this is the exact time to sample for maximum accuracy in the
detection process.
It is difficult to identify the peak value of the signal in the presence of noise. Instead
of sampling the signal at the peak, suppose the signal is sampled early, at 𝑡 = 𝑇 − 𝛿 ,
and late at 𝑡 = 𝑇 + 𝛿. The absolute value of the early samples |𝑦(𝑚(𝑇 − 𝛿))| and the
late sample |𝑦(𝑚(𝑇 + 𝛿))| will be smaller than the samples of the peak value
|𝑦(𝑚(𝑇))|. The absolute value of the correlation function is equal since the auto
correlation function is even with respect to the optimum sampling time. Under this
condition the suitable sampling time is the midpoint between 𝑡 = 𝑇 − 𝛿 and 𝑡 = 𝑇 +
𝛿, which is the basis of early/late gate synchronizer [11].
3.4.4 Choice of Best Approach
The operations of mid-symbol sampling and early/late-gate have been investigated in
the above sections. Mid-symbol sampling if compared with early/late-gate results in
issues like noise performance and data format required in order to ensure maximum
efficiency. Output of the correlator gets sampled at the end of each symbol period in
mid-symbol technique. This process is imprecise if the peak is hidden in noise,
resulting in wrong mid-symbol estimation. This technique makes use of zero crossing
to recover the timing information, the type of data format used is very important to
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achieve a reliable performance. This is because no timing information is available
every time there is a sequence of 0’s or 1’s because the zero crossing will only occur
when there is a transition in the data state. Thus this technique is not suitable for this
project. Whereas the early/late-gate technique ensures reliable and optimum
performance even with reduced signal to noise ratio (SNR), as this technique does
not use zero crossing, it allows timing information to be recovered even when the
data consists of long sequences of 1’s although as with the mid-symbol sampling no
information is available when a sequence of 0’s is sent. This is the reason why
early/late-gate is suitable for this project.
3.5 Hardware/Software Implementation
There are some issues encountered while implementing early/late-gate on hardware
and software. An offset will be introduced between two integrators if early/late-gate
implemented on hardware. This issue arise because it is difficult to build two
integrators, which are exactly the same because of different tolerances in the
components being used. This offset is will be small for well-designed integrators but
will cause the loop to drift out of synchronism if there are long sequences of identical
data symbols. To solve this problem in early/late-gate synchronizer two methods has
been used. The first, and conceivably most obvious, is to format the data in a manner
which certifies that there will be no transitionless intervals that are long enough to
allow the loop to break lock. Second response is to modify the loop design so that it
contains a single integrator; example of this type is tau-dither loop [5]. Simulink®
software is used to implement the early/late-gate synchronizer circuit; the software
allows design of identical integrators which is difficult to implement on hardware.
An additional loop design issue is that an early/late-gate integrators works by
integrating at different times during the symbol period and by comparing the two
outputs. This method cannot be implemented on hardware or software because
controlling the integrators to operate only during the required portions of the symbol
period for a given amount of time requires very complex and expensive circuit
designs. After, further research this method can be implemented by using two
alternative methods, which was discussed below.
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Figure 3-9 Early/Late-Gate Synchronizers [11].
In the above figures, it was seen that correlators are being used instead of matched
filters, these correlator integrate over the symbol interval 𝑇, and delay by 𝛿 seconds.
The difference between the absolute values of the two correlators output results in
signal error. The error signal is passed through the lowpass filter to smooth the noise
which corrupts the signal samples. The average error signal at the output of the
lowpass filter is nonzero if the timing is off relative to the optimum sampling time,
which makes the clock signal to retard or advance, depending on the sign of the
error. Thus, the error signal is used to drive a voltage controlled clock (VCC), whose
output is the desired clock signal that is used for sampling. The pulse is then
advanced or delayed and fed to the two correlators as shown in figure 3-4. The
bandwidth of the loop is increased to provide faster tracking of time variation in
symbol timing, since there are delays in channel and transmitter clock with respect to
time. Correlators are affected by adjacent symbols in tracking mode. The output of
the correlators from adjacent symbols averages out to zero in the lowpass filter, as
the information symbol has a zero mean [11].
Figure 3-10 Alternative method for Early/Late-Gate Synchronizer [11].
Hence, early/late-gate synchronizer is used instead of mid-symbol sampling because
the early/late-gate synchronizer gives better accuracy, reliability, efficient use of
bandwidth and robustness, although it is expensive and complex to implement.
In this chapter different techniques of symbol timing recovery of a system has been
discussed. Methods like early/late-gate and mid-symbol sampling can be used for
synchronization, but only early/late-gate method was chosen for implementation
because of its accuracy, reliability, use of bandwidth and robustness. This chapter
also describes alternative methods for early/late-gate synchronizer.
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Chapter 4: Matlab Implementation
Figure 4-1 Simulation Model of Early-Late-Gate symbol timing recovery
subsystem based on Phase-Locked Loop
4.1 Simulink® Overview
The base for multi-domain simulation is Simulink®. For dynamic and embedded
systems simulink® is the model-based design. Simulink® gives a set of customizable
block libraries and also gives an interactive graphical environment for designing,
simulating, implementing and also testing of time-varying systems. It also includes
communication, controls, and processing of video and image signals. Add-on
products in simulink® not only extend the simulink® software to modelling domain
but also provide tools for tasks like designing, verification, validation, and
implementation [10].
Simulink® included with MATLAB®. This provides instantaneous access to wide
range of tools that helps to build up algorithms. It also helps to analyze and visualize
simulation, create batch processing scripts, customize the modelling environment,
and classify signal, parameter, and test data. It allows design of communication
systems and their semiconductor components, such as commercial or defence
wireless and wire line systems [10]. The important characteristics of simulink® are:

It is capable of managing difficult designs by separating models, with
respect to group of design components.
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



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It has extensive and flexible libraries of predefined blocks.
It Design and simulates blocks and systems. This includes source and
channel encoding, equalisation, modulation, channel encoding, phaselocked loops. It also includes a range of degradations such as Additive
White Gaussian Noise (AWGN) and, fading.
It is capable of tuning models and visualising results by using eyediagram, bit error rate calculation, and scatter diagrams.
Application programming interfaces (APIs), includes hand written
codes and connects with other simulation programmes [10].
4.2 Block Parameters Setup
4.2.1 Bernoulli Binary Generator
The random binary numbers are generated by Bernoulli Binary Generator block. It
uses Bernoulli distribution to generate random binary numbers. The Bernoulli
distribution with parameter p produces zero with probability p and one with probability
1-p. The Bernoulli distribution has mean value 1-p and variance p(1-p). The
probability of zero parameter specifies p, and can be any real number between zero
and one. Bernoulli Binary Generator is used in the model to generates random data
which will act as the received demodulated data pulsed from which the symbol
recovery will be carried out [10].
Figure 4-2 Bernoulli Binary Generator
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Figure 4-3 Bernoulli Binary Generator Block Parameters
As seen in above figure4-3 that the probability, p, was set to 0.5, which gives a 50%
chance of generation a 0 or a 1 during a data sequence. The sample time was set to
1e-7 resulting in clock source of 10 MHz
4.2.2 Product
The multiplication and division of the input is done by Product block. It constructs
outputs using either element-wise or matrix multiplication, depending on the value of
the multiplication parameter. The number of inputs parameter identifies the operation.
Multiply (*) and divide (/) characters indicate the operation to be performed on the
inputs. It performs the multiply or divide operations on the inputs, then converts the
results to the output data type using the specified rounding and overflow modes [10].
Figure 4-4 Product Block
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Figure 4-5 Product Block Parameters
The Product block in the design was used to multiply the output from the Bernoulli
Binary Generator and the Voltage Controlled Clock before integration is carried out.
4.2.3 Integrator Block
The integrator block outputs the integral of its input at the current time step. The
following equation represents the output of the block 𝑦 as a function of its input 𝑢 and
an initial condition𝑦0 , where 𝑦 and 𝑢 are vector functions of the current simulation
time T [10].
𝑡
𝑦(𝑡) = ∫ 𝑢 (𝑡) 𝑑𝑡 + 𝑦0
𝑡0
Equation 4-1
Figure 4-6 Integrator Block
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Defining Initial conditions with the help of Integrator we can define the initial
conditions as a parameter on the block box or input them form an external signal:
To define the initial conditions as a block parameter, specify the Initial
condition source parameter as internal and enter the value in the Initial
condition parameter field.
To provide the initial conditions from an external source, specify the Initial
condition source parameter as external.
The block can reset its state to the specified initial condition based on an external
signal. To cause the block to reset its state, select one of the external reset choices.
A trigger port appears below the block’s input port and indicates the trigger type [10].
Figure 4-7 Integrator Block Parameters
In the Integrator block parameter the external reset was set to rising, which allows
the integration to be reset after each symbol duration in order to obtain the optimum
peak sampling time.
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4.2.4 Transport Delay Block
Figure 4-8 Transport Delay Block
The Transport Delay block delays the input by a specified amount of time. This block
is used to simulate a time delay. The input to this block should be a continuous
signal. At the start of simulation, the block outputs the initial output parameter until
the simulation time exceeds the time delay parameter. Then the block begins
generation the delayed input. The Time delay parameter must be nonnegative [10].
Figure 4-9 Transport Delay2 Block Parameters
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Figure 4-10 Transport Delay1 Block Parameters
From the above two figures 4-9 and 4-10 it can be seen that the time delay
parameter for Early sampler was set to (1𝑒 − 7)/2 and for Late sampler the time
delay parameter was set to 3 ∗ (1𝑒 − 7)/2, which shows that sampling took place
(1𝑒 − 7) seconds early in the first sampler with respect to the late sampler.
4.2.5 Pulse Generator Block
Figure 4-11 Pulse Generator Block
The Pulse Generator block generates square wave pulses at regular intervals. The
block’s waveform parameters, amplitude, pulse widt, period, and phase delay,
determine the shape of the output waveform [10].
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Figure 4-12 Pulse Generator Block Parameters
From the above figure 4-12, the pulse type was set to time based, which computes
the block’s output only at times when the output actually changes. This can result in
fewer computations for computing the block’s output over the simulation time period.
The sample time period was set to (1𝑒 − 7), so that the pulses obtained from the
output of the generator could be used to reset the integrator after each symbol
interval.
4.2.6 Sample and Hold Block
Figure 4-13 Sample and Hold Block
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Sample and Hold block acquires the input at the signal port whenever it receives a
trigger event at the event at the trigger port (marked by ). It then holds the output
at the acquired input until the next triggering event occurs. If the acquired input is
frame based, the output is also frame based; otherwise, the output is sample
based.The trigger input must be sample-based scalar with the sample rate equal to
the input frame rate at the signal port [10]. This can be done in Trigger type pop-up
menu:
Rising edge triggers the block to acquire the signal input when the trigger input rises
from a negative value or zero to a positive value.
Falling edge triggers the block to acquire the signal input when the trigger input falls
from a positive value or zero to a negative value.
Either edge triggers the block to acquire the signal when the trigger input either rises
from a negative value or zero to a positive value or falls from a positive value or zero
to a negative value [10].
Figure 4-14 Sample and Hold Block Parameters
The Sample and Hold block in the simulation model takes the outputs from the two
transport delays block and trigger it to achieve early and late sampling.
4.2.7 Absolute Value Block
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Figure 4-15 Absolute value Block
The Abs block outputs the absolute value of the input. For signed-integer data types,
the absolute value of the most negative value is challenging since it is not
representable by the data type. In this case, the saturate on integer overflow check
box controls the behaviour of the block.
Figure 4-16 Absolute Value Block Parameters
4.2.8 Subtractor Block
Figure 4-17 Subtractor Block
The Sum block performs addition or subtraction on its inputs. This block can add or
subtract scalar, vector, or matrix inputs. It can also collapse the elements of a signal.
Characters like plus (+), minus (-), and spacer (|) indicates the operation to be
performed on the inputs. This block first converts the input data types to its
accumulator data type, and then performs the specified operations on it. The block
converts the result to its output data type using the specified rounding and overflow
modes.
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Figure 4-18 Subtractor Block Parameters
4.2.9 Low-Pass Filter Block
Figure 4-19 Low-Pass Filter Block
The Analog filter design block designs and implements a Butterworth, Chebyshev
type Ι,Chebyshev type Ι Ι, or elliptic filter in a highpass, lowpass, or bandstop
configuration. The input to the filter must be a sample-based, continuous-time, realvalued, scalar signal. To select the design and band configuration of the filter, the
design method and filter type pop-up menus in the dialog box is used.
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Figure 4-20 Low-Pass Filter Block Parameters
From figure 4-20 it can be seen that the design method used is Butterworth lowpass
configuration with cut-off frequency of 10 MHz, which removes the unwanted high
frequency components generated while integrating and passing through the mixer.
Butterworth filter magnitude response is maximally flat in the passband and
monotonic overall.
4.2.10 Voltage Controlled Clock Subsystem
The Continuous-Time voltage controlled oscillator block generates a signal whose
frequency shift from the quiescent frequency parameter is proportional to the input
signal. The input signal is interpreted as a voltage. It the input signal is 𝑢(𝑡), then the
output signal is
𝑡
𝑦(𝑡) = 𝐴𝑐 cos (2𝜋𝑓𝑐 𝑡 + 2𝜋𝑘𝑐 ∫ 𝑢(𝜏)𝑑𝜏 + 𝜑)
0
Equation 4-2
Where 𝐴𝑐 is the output amplitude parameter, 𝑓𝑐 is the Quiescent frequency
parameter, 𝑘𝑐 is the Input sensitivity parameter, and 𝜑 is the initial phase parameter.
This block uses a continuous-time integrator to interpret the equation above. The
input and output signals are both sample-based scalars.
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Figure 4-21 Voltage Controlled Clock Block
The sinusoidal waveform comes from the voltage controlled oscillator converted to
square pulses which represent the symbol timing; this can be done by voltage
controlled clock (VCC).
Figure 4-22 Voltage Controlled Clock Block
From figure 4-22 it is seen that the sinusoidal waveforms from VCO is converted to
square pulses by simply comparing the output of the VCO to a constant zero, such
that all negative values were fixed to zero and positive value become 1’s.
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Figure 4-23 Voltage Controlled Oscillator Block Parameters
It was shown in the above figure 4-23 that the oscillator output frequency that is
quiescent frequency was set to the clock frequency (which was 10 MHz) when the
input signal is zero. The input sensitivity scales the input voltage and then the shift
from the centre frequency value, was set to 10 GHz.
4.2.11 Scope Block
Figure 4-24 Scope Block
The Scope block displays its input with respect to simulation time. This block can
have multiple axes (one per port) and all axes have a common time range with
independent y-axes, which allows adjusting the amount of time and the range of input
values displayed. It allows moving and resizing the Scope window and it also allows
modifying the Scope’s parameter values during the simulation.
When the simulation starts the Scope windows are not opened, but data is written to
connect Scopes. As a result, if the Scope is opened after a simulation, the Scope’s
input signal or signals will be displayed [10].
4.2.12 Power Spectrum Block
The averaging power spectral density block displays the frequency content of the
buffer in the graph window, which is used in the design to acquire frequency
spectrum of the input and recovered data for comparison [10].
Figure 4-25 Power Spectral Block
This chapter gives the information of each and every block and its parameters to be
used in the simulation process. Setting of block parameters to get the desired output
has been given. The voltage controlled clock designed using a VCO has been
discussed in this chapter.
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Chapter 5 Results and Discussions
5.1 Input Data from Bernoulli Generator
To achieve synchronization using early/late-gate synchronizer MATLAB software was
used, which gives the design of simulink® system in order to get the desired output.
Input data was Bernoulli generator, which generates binary numbers using a
Bernoulli distribution. The output from Bernoulli generator is shown below in time
domain and frequency domain.
Figure 5-1 Time domain waveform of input data
Figure 5-2 Input spectrum
Bernoulli binary generator generates random sequence of 1’s and 0’s at the output
which was shown in figure 5-1. The spectrum in figure 5-2 demonstrates the clock
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frequency at 10MHz. There is a raise in the bandwidth efficiency of the subsystem
due to format of data which is Non-Return to Zero (NRZ).
5.2 Integrators output
The output from early and late gate integrator along with received data is shown
below.
Figure 5-3 Integrators Output
Figure 5-4 Input Output Spectrum
The integrators key function in the subsystem was to act as matched filters. The
output is the time autocorrelation function of the input signal, resulting in the
expected isosceles-triangular waveforms which attains its peak at the symbol period,
𝑇. The property of the output or autocorrelation function being even with respect to
the optimum sampling time, therefore accounts for the ability of this loop to sample
early at time 𝑇1 and late time 𝑇2 . 𝑇2 and 𝑇1 will become equal if exact sampling was
performed. This can be shown in figures 5-3 and 5-4.
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5.3 Sample and Hold Output
Figure 5-5 showed the output of the sampler and hold block, it can be seen from the
figure that there is a time delay between outputs of early and late gates sampler. This
delay is due to the sampler and hold device performed sampling early with respect to
late sampler, resulting in control voltage at the output of the loop filter, the output
achieved from sample and hold device were not exactly the same as mention in
section 3.4.1.
Figure 5-5 Sample and Hold Output
5.5 Low Pass Filter Output (Control Voltage)
The low pass filter generates error or control voltage which is fed to the VCC. This
control voltage becomes zero for sequences of 0’s at the start of the simulation. The
output of loop filter varies between positive and negative values for 1’s sequences. It
has been noticed that the control voltage turn out to be zero at 25µs, which specifies
that the output of the sample and hold circuits are matching and that the loop is in
phase-lock with the incoming clock frequency. It’s been observed that the low pass
filter with a cut-off frequency 10MHz attenuate any high frequency components,
which may be there at the output of the mixer.
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Figure 5-6 Low Pass Filter Output (Control Voltage)
4.6 Recovered Symbol Timing Signal
The results obtained from figures 5-7, 5-8, and 5-9 clearly shows that the recovered
clock signal is same as input signal, which is given by the Bernoulli generator. At
centre frequency of 10MHz the VCO eliminates unnecessary frequencies and locks
itself onto the clock frequency. When the frequency spectrum of input data from
Bernoulli generator compared with frequency spectrum of recovered data from VCC
once the loop is in lock, it can be observed that the loop correctly recovered the
symbol timing as they are matching with one another, together consisting of the clock
frequency at 10MHz.
Figure 5-7 Recovered Symbol Timing Waveforms
Figure 5-8 Recovered Symbol Timing during Lock Process
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Figure 5-9 Recovered Symbol Timing Output after Lock Loop
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Chapter 6
6.1 Conclusion
This project gives the information of waveform synchronization in WiMAX base
station using different techniques of phase-locked loops. In order to achieve this it
was important to gain knowledge of topics like bandpass or baseband transmission,
phase-locked loop operations, coherent detection etc. The most common two
methods used for symbol timing recovery between base stations are mid-symbol
timing and early/late-gate. The operations of these two techniques were studied
which gives merits and demerits of these two techniques which were essential for
implementation of one of the method.
It was examined that mid-symbol sampling technique uses zero-crossing in the data
signal, while the early/late-gate technique make use of integration. Therefore the
early/late-gate technique was preferred to implement as this technique gives more
accurate results along with improved efficiency. During development process the
circuit design was implemented on simulink® software. It was seen how the
integrators settings and design of VCC to generate the recovered clock waveform
had been addressed. It was noticed that during implementation the block parameters
had to be cautiously set up in order to match the design and the required data rate.
After implementing the circuit model on simulink® the results were obtained which
were investigated in time and frequency domain. The simulation results showed that
the proposed model control to lock on the clock frequency within about 25µs of
simulation time. Hence the proposed model can be used in WiMAX base station.
6.2 Future Development in synchronization
Synchronization is an important technique in digital communication system. Impact of
synchronization has been great and influential on various techniques like decoding
channel estimation, equalization etc. For the future development following implication
can be made in synchronization, based on the [13]:
1. Frequency domain synchronization plays a dynamic role to ensure the estimation
accuracy after the coarse synchronization estimation is completed in time domain.
Control model is significantly necessary to coordinate the whole estimation process
between time and frequency domains. This is unfavourable for the burst packet mode
systems because the FFT calculation and other factors may significantly increase
synchronization time. Therefore, it is of great importance to find the useful
approaches to perform the synchronization throughout the time domain with the
acceptable estimation accuracy [13].
2. Two major research directions i.e. efficient design of the distribution patterns of the
pilots or the training symbols, and the blind or semi-blind algorithms of low
computational complexity [13].
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3. Synchronization and channel estimation are dealt separately at present. This effect
the channel estimation by residual synchronization errors, and in view of system
design optimization point of view, these two operations should be considered
together [13].
4. The Doppler shift in wireless mobile communications caused ICI and destroys the
orthogonality of OFDM symbols. Phase noises in the OFDM systems may introduce
common phase error (CPE) and inter-carrier interference ICI. There have already
been many solutions, yet special attention should be paid to deal with them in the
OFDM systems [13].
6.2.1 Future Development in WiMAX
WiMAX-TDD (OFDM-256) has been implicated in the convergence investigation
which was presented in [14]. Future work in WiMAX-FDD (OFDM-256) convergence
investigation can also be done, which include the implementation of simple Read
Salmon block code and Vertabi convolution code. Wireless Mesh Network standards
are under development, it would be a good chance to involve the WiMAX-WiFi
convergence in mesh topology applications [14].
6.3 Other Points
6.3.1 Project Planning
The original plan to complete the project within the given time duration was divided
into several work stages. This plan can be seen in Appendix A, which illustrates the
actual Gantt chart during the development stages of the project. During the first two
months the research was carried out as usual. After the research work was done,
there were some difficulties while implementation of design occurred, which will be
discussed in next section. The majority of the work stages have been done on time or
a week earlier than the proposed original time plan except for the “Model
Implementation”, which took three weeks extended than expected. But the project
completed before the deadline.
6.3.2 Issues Came Across
As mentioned in the last section that there were some major issues occurred during
the project implementation work stage, which encountered due to lack of knowledge
on using the simulink® software, which led to problems in setting up block
parameters. First issue which occurred was to implement the model, because there
was no availability of proper circuit design or circuit diagrams of early/late-gate
synchroniser. Extra research had to be carried out which led to precise design being
acquired. After finalising the circuit design issues like Voltage-Controlled Oscillator
(VCC), integrators, and Sample and Hold circuit settings were evolved.
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The VCC calculates input sensitivity, which commands the shift from the centre
frequency when an error voltage is applied. The VCC block parameter was set to
10GHz which solve the problem occurred. The problem in integrators was that they
both integrate only during one symbol period. This difficulty was solved by using the
integrators blocks option i.e. external reset and a pulse generator was used to
produce the reset waveform. The sample and hold circuit had to be set up in such a
way that it produces the waveforms early relative to the late sampler. This can be
done by setting up the delays blocks.
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REFERENCES
1. Hisham A. Mahmoud, Huseyin Arslan(Electrical Engineering Department,
University of South Florida), and Mehmet Kemal Ozdemir Logus (Broadband
wireless solutions), “Initial Ranging for WiMAX (802.16e) FDMA”
http://www.eng.usf.edu/~hmahmoud/pdf/pubs/hmahmoud_MILCOM06.pdf
2. Ian A. Glover and Peter M. Grant, “Digital Communication”, Pearson Prencice
Hall: England, Second Edition, Pg 390-391.
3. http://www2.ing.puc.cl/~iee3552/Baseband.PDF
4. Dr.
Oke C. Ugweje, “Modulation and Demodulation Techniques in
Communication Systems” Department of Electrical & Computer Engineering,
University
of
Akron,
June28
2000.
http://www.ecgf.uakron.edu/ugweje/web/Research/Publication/NASAseminarLect
ure3.PDF
5. Bernard Sklar., “DIGITAL COMMUNICATIONS: Fundamentals and Applications”
Second Edition, Communications Engineering Services, Tarzana, California and
University of California, Los Angeles. Prentice Hall 2001.
6. Nirmala Chamath Wijeratne, “IMPLEMENTAITON OF THE EARLY-LATE GATE
SYNCHRONIZER AS AN SOPC COMPONENT”, University of Auckland,
Auckland, New Zeland. Nwij007.paf
7. Ezra Ip, Alan Pak Tao Lau, Daniel J. F. Barros, Joseph M. Khan, “Coherent
dectection in optical fiber systems”, Stanford Univeristy Published 9 Jan 2008, 21
January 2008/ Vol . 16, No. 2/ OPTICS EXPRESS,
http://www-.stanford.edu/~jmk/pubs/coherent.review.optics.express.corrected.pdf
8. Nasa Report
http://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/19910012122_1991012122.
pdf#search
9. Roland E. Best, “Phase-Locked Loops: Design, Simulation, and application”,
Sixth Edition.
10. http://www.mathworks.com/ (Online reference)
WiMAX Base Station Waveform Synchronization Using Early/Late-Gate Synchronizer 41
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11. John G Proakis, “Digital Communications”, Mc Graw-Hill:Singapore, Third Edition
1995, Chapter-6 Carrier and Symbol Synchronization.
12. Darrel R. Judd, “Data Synchronization Simulation Using The MATHWORKS
Communications Toolbox”, Harman-Motive Inc. IEEE-1996.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=541273&userType=ins
t
13. Ai Bo, Zhong Zhang-Dui, Zhu Gang, Xu Rong-Tao, and Ding Jian-Wen, “Patents
on Synchronization Techniques in Wireless OFDM Systems”, Recent Patents on
Electrical Engineering 2008, 1, 14-21, 2008 Bentham Science Publishers Ltd.
14. Ali Al-Sherbaz, Chris Admans & Sabah Jassim, “WiMAX-WiFi Convergence with
OFDM Bridge”, Applied computing Department, University of Buckingham.
WiMAX Base Station Waveform Synchronization Using Early/Late-Gate Synchronizer 42
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MSc Final Year Project Report
BIBLIOGRAPHY
1. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1093326
2.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1532198
WiMAX Base Station Waveform Synchronization Using Early/Late-Gate Synchronizer 43
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APPENDICES
Appendix A
Original Project Plan
Figure A-1 Gantt Chart
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MSc Final Year Project Report
Appendix B
Figure B-1 Symbol Timing Synchronization
Figure B-2 Carrie Frequency Synchronizer Estimator
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Appendix C
Figure C-1 WiMAX Physical Layer Simulation
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Appendix D
Figure D-1 Simulink® Model of an analog PLL
Figure D-2 VCO output
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