On the Design of Efficient Modulo 2n+1 Multiply-Add-Add
Units
Abstract:
In this work efficient modulo 2n+1 fused multiply-add-add units for weighted and
diminished-1 operands are proposed. The proposed architectures can be applied in systems in
which fused multiply-add-add units accelerate the execution of the targeting algorithms. Long
integer arithmetic would also show considerable gains by using multiply-add-add units. Also,
implementation results for the proposed units are given and compared to the performance of
existing designs.
Existing Method: The Residue Number System (RNS) reduces the delay of carry
propagation in arithmetic operations making it attractive for computationally intensive
applications. The use of RNS accelerates Digital Signal Processing (DSP) algorithms such as
Finite Impulse Response (FIR) filters and Fast Fourier Transforms (FFT). RNS-based processors
have been proposed in [3]. RNS arithmetic is also widely used for the speedup of cryptographic
algorithms [4], [5] and in the Fermat number transform [6], [7]. The moduli set (2n -1,2n,2n +1)
attention offering simple and efficient
implementations [8]. Weighted and diminished-1 representations are used in modulo 2n+1
arithmetic. The weighted representation of the numbers (0,2n) requires n+1 bits. In the
diminished-1 form [6], a number A €(0,2n)is represented asA-1= A-1 while zero operands are
handled separately. Since only n bits are
A €(0,2n) , the
diminished- 1 representation leads to implementations with delay and area complexity similar to
those of the modulo 2n-1 and 2n representations. To avoid extra hardware for handling zero
operands, efficient architectures of modulo 2n+1 units for diminished-1 operands including zero
indication bits are developed.
Further Details Contact: A Vinay 9030333433, 08772261612
Email: takeoffstudentprojects@gmail.com | www.takeoffprojects.com
Proposed Method:
In this work efficient modulo 2n+1 multiply-add-add units for weighted and diminished-1
operands with zero indication bits are proposed. The unit for the weighted operands is based on
the modulo 2n+1 multiplication algorithm while the one for the diminished-1 operands is based
on the multiplication algorithm which is extended to handle zero operands. The proposed
architectures are applicable in systems where fused multiply-add-add units accelerate the
execution of the targeting algorithms, e.g. DSP and cryptography systems. Using multiply-addadd units would also lead to gains in long integer arithmetic applications as such an operation is
executed in the inner loop of various algorithms of long integer arithmetic.
Applications:
1) DSP Applications.
2) Filter Design approaches.
3) Cryptography.
Advantages:
Simple and easy to implement for MAC Units
System Configuration:In the hardware part a normal computer where Xilinx ISE 14.3 software can be easily
operated is required, i.e., with a minimum system configuration
Further Details Contact: A Vinay 9030333433, 08772261612
Email: takeoffstudentprojects@gmail.com | www.takeoffprojects.com
HARDWARE REQUIREMENT
Processor
Pentium –III
-
Speed
- 1.1 GHz
RAM
- 1 GB (min)
Hard Disk
-
40 GB
Floppy Drive
-
1.44 MB
Key Board
- Standard Windows Keyboard
Mouse
- Two or Three Button Mouse
Monitor
- SVGA
SOFTWARE REQUIREMENTS
 Operating System
:Windows95/98/2000/XP/Windows7
 Front End
: Modelsim 6.3 for Debugging and Xilinx 14.3 for
Synthesis and Hard Ware Implementation
 This software’s where Verilog source code can be used for design implementation.
Further Details Contact: A Vinay 9030333433, 08772261612
Email: takeoffstudentprojects@gmail.com | www.takeoffprojects.com