1. Readout electronics
The front-end readout electronics consist of a differential Amplifier-Shaper-Discriminator of
very high performance with peaking times of order 2 ns, high gain of order 4-8 mV/fC, and
comparator threshold uniformity of a few mV. The VMM chip developed by the Brookhaven group,
using IBM 130 nm technology, meets this specification. The readout scheme is proposed, as is shown
in Fig. 3. In collaboration with the sTGC groups, we would like to investigate the plan of digital
processing circuit that accepts the signals from the ASD and delivers coincidence times, maximum
strip selection, and a second coordinate based on the differential timing from signals read from
opposite ends of the sTGC pickup lines.
Figure 3: sTGC readout scheme for trigger processing before Level 1.
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2. Optical link
The optical link connects the router signal out of the detector rim to the electronic hub for data
logging. Digitized data from the individual layers will need to be multiplexed then serialized for the
off-detector transmission. The Multiplexer and serializer will need to be implemented with some of
the following functional blocks:
1. Form a transmission frame where a local clock counter may be inserted into the ADC data.
2. Encode the frame which provides the deserializer in the receiver side to recover the word
boundary.
3. Scramble to provide DC balance.
4. Insert error correction or detection (for example, parity bits for each frame).
Different encoding and error detection schemes are being evaluated: either standard encoding
schemes commonly used in high speed optical links, or novel encoding/framing schemes optimized
for prompt corrections and re-synchronizations of the links. Embedded synchronization codes or
cyclic control and synchronization messages and redundancy schemes may be needed for high speed
serial communication systems installed in a radiation environment.
The optical fibers carrying the digitized higher granularity data will be transmitted to receiving
and processing modules before being sent to the Level-1 trigger system. Fig. 4 exemplifies a possible
implementation under investigation:
1. As for the analog trigger tower signals, the arriving optical signals are rearranged through an
optical splice panel.
2. Receiving modules realize opto-electrical conversion, time alignment of digital signals, error
detection and correction.
3. Proper subtraction of the baseline looking at the signal history over approximately 600 ns,
taking into account out-of-time pile-up contributions.
4. FPGA-based processing units apply digital filtering techniques and convert raw ADC data to
fully calibrated energy, and to transverse energy.
5. Finally filtered data are transmitted serially to the following stage. The interface to the trigger
will be designed and developed aiming at full compatibility with a similar interface to be
developed for the Phase-II upgrades.
6. Filtered data are locally buffered awaiting a Level-1 decision. Upon arrival of a Level-1 accept
signal, data are transmitted to the DAQ and/or to the high-level trigger system.
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2.1 CERN Versatile Link [A.C. Xiang, HSTD 8]
The optical transceiver developed by the CERN Versatile-Link project [4] aims to deliver a
radiation tolerant 4.8 Gb/s bi-directional optical link for the LHC upgrade program. The front-end
interface module, VTRx, illustrated in Fig.5, is a low power dissipation and low mass electro-optical
transceiver that is protocol-agnostic. The link is also targeted to operate in tandem with the CERN
GBT serializer-deserializer chip. Two versions of the transceivers are being developed: single-mode
and multi-mode operating at 850nm and 1310nm wavelength respectively. The circuit diagram and
picture of a VTRx module is shown in Fig. 6.
The fundamental requirement for the Versatile Link is the reliable operation in radiation
environments of particle physics detectors. Radiation induced degradation in circuits, optical modules
and in fiber must be taken into account in the system level design. Parts must not only be resistant to
ionizing, but also displacement damage while system level design to mitigate Single Event Effects
(SEE) must be in place. In the Versatile Link we design for two radiation tolerance grades: the
calorimeter (10 kGy, 5×1014 neutron/cm2) grade and the tracker (500 kGy, 2×1015 neutron/cm2,
1×1015 hadron/cm2) grade. Based on studies of optical components (lasers and PIN diodes) and
fibers, we specify an optical power budget with margin for all link configurations. The timing jitter
budget is adapted from FC 4G standards. A full set of system and components specifications can be
found in [5].
Figure 4: Block diagram of the receiving/processing system and interface to the Level-1 calorimeter
processors.
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Figure 5. Overview of the Versatile Link architecture.
Figure 6. Circuits and picture of a VTRx module. The eye diagram of signal transfer is also show.
The VTRx is customized for use in the HI-LHC detector environment: the laser driver and
detector amplifier are custom-designed as part of the GBT project; the laser and photo-detector have
been evaluated for their radiation tolerance; and the mechanical interface has been re-designed to
reduce its mass and remove magnetic material.
A broad spectrum of optical devices and subassemblies has been tested using both neutron and
pion beams to ensure that they will survive the HI-LHC lifetime fluence levels. System impact of
radiation degradation is accounted for in the power budget. SEE testing has also been carried out on
candidate photodiodes and ROSA assemblies. The Bit Error Rate induced by a particle beam requires
the use of a forward error correction code. The one implemented in the GBT chipset has been shown
to be effective.
The development of VTRx module is chosen to qualify commercially available components for
use in the HL-LHC environment so as to minimally customize them only where necessary. The
project has now concluded of its second phase with the successful demonstration of feasibility of the
proposed optical link system. The full VTRx built from radiation-tolerant, low-mass components has
been tested and shows good results. A full list of candidate optical link components has been
established for all parts of the versatile link. These components have been validated according to the
specifications established for functional performance and radiation tolerance. These specifications
give us confidence that a large scale implementation of the Versatile Link will operate correctly.
System demonstrators are in development and will soon be available to interested users for sampling.
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2.2 SMU LAr Optical Link [NIM A 699, pages 120-123]
The SMU group has been working on designs of Application Specific Integrated Circuits
(ASICs) [6] for the transmitting of an optical link to meet the LHC upgrade challenge for LAr
detector and the needs in many new detectors, especially those designs to operate in radiation
environment. The goal of data throughput is 10 Gbps per fiber. A functional block diagram of serial
data transmission over fiber optics is shown in Fig. 1 [8,9].
Fig. 1. Block diagram of a fiber optics based
serial link system.
The interface block consists of a 16:1 serializer designed to operate at 5 Gbps, and an LC based
phase-locked-loop (PLL) that runs up to 5 GHz. Both designs are based on a commercial thin-film
silicon-on-sapphire (SOS) 0.25 μm CMOS technology. The optical interface consists of a (current)
laser driver (LD) circuit and a laser. The LD is the same as a CML line driver with matching
modulation current and impedance of the laser in use. The design of the serializer follows an inverted
tree structure with a cascade of many 2:1 multiplexing units, as shown in Fig.2. The schematics of
the laser driver (only the last two stages shown) an eye diagram at 8 Gbps based on the post layout
simulation are shown in Fig. 3. [9]
Fig. 2. Block diagram design of the 16:1
5 Gbps serializer.
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Fig. Schematic of the laser driver and the an eye diagram at 8 Gbps based on the post layout
simulation.
Simulation results indicate that both LOCs2 and LOCld should work at 8 Gbps and this is
really what this technology can offer. We will need either change the system design to work with the
speed of 8 Gbps per fiber, or move to a newer SOS technology to reach higher speeds.
[1] R. Santonico, R. Cardarelli, Nucl. Instrum. Meth. A 187 (1981) 377.
[2] ATLAS Collaboration, JINST 3, (2008) S08003.
[3] G. Aad et al. (ATLAS Collaboration), arXiv:0901.0512.
[4] C. Soos et al.,”Versatile transceiver development status”, 2012 JINST 7 C01094
http://iopscience.iop.org/1748-0221/7/01/C01094/pdf/1748-0221_7_01_C01094.pdf
[5] https://edms.cern.ch/nav/P:CERN-0000076379:V0/P:CERN-0000090391:V0/TAB3
[6] A.C.Xiang, HSTD-8 poster
http://hepweb03.phys.sinica.edu.tw/opto/Irradiation/Documents/SMU_papers/Poster_Teng_hstd2011_vl_rev2.pdf
[7] G. Mazza et al., “The GBLD: a radiation tolerant laser driver for high energy physics
applications”, JINST 8 C01033, 2012.
http://iopscience.iop.org/1748-0221/8/01/C01033/pdf/1748-0221/8/01/C01033.pdf
[8] D. Gong et al., “ASIC developments for high speed serial data transmission in particle physics
experiments”, Nucl. Instrum. Meth. A 699 (2013) 120.
http://www.sciencedirect.com/science/article/pii/S0168900212006262
[9] F. Liang et al., “The design of 8-Gbps VCSEL drivers for ATLAS liquid Argon calorimeter
upgrade”, JINST8 C01031, 2013.
http://iopscience.iop.org/1748-0221/8/01/C01031/pdf/1748-0221_8_01_C01031.pdf
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