ECE4273/6273
Checkoff exercise #6a
2-terminal MOS junction
version 2.2
The nominal MOS construct is a four-terminal (transistor) device as indicated by figure nMOS2-1b. Even
though we may choose to operate and even fabricate MOS devices in forms other than the 4-terminal form,
the only device in the simulation library is the MOS transistor, with four terminals: gate, drain, source, and
body, as indicated by figure nMOS2-1a.
Figure nMOS2-1: nMOS transistor, schematic and cross-section
And if you check the parts libraries, you will also find that there is no such item as a discrete MOS transistor.
All MOS transistors are defined by a SPICE parameter files, instantiated into a device template.
Usually we acquire our SPICE parameters from the MOSIS (http://www.mosis.org/Technical/Testdata/)
fabrication service. Templates are of the form of a ‘breakout’ part, e.g. MbreakN, for an nMOS transistor.
In addition, you also must define the geometrical features of the MOS transistor, for which explicit width
(W) and length (L) values are needed, as indicated by figure nMOS2-2. Dimensions invariably should be
specified as microns (see figure). There are other geometrical parameters (AS, AD, PS, PD) defined when
the transistor is used in a circuit, but for now will be omitted.
Figure nMOS2-2: nMOS transistor, menu for dimensional specifications invoked.
For the ‘physical’ model of the MOS transistor we will invoke level-3 parameters, for which (you might
notice) the level specification (LEVEL= ) is level=3, as represented by table nMOS2-1
.MODEL CMOSN NMOS (
LEVEL = 3
+ TOX = 1.4E-8
NSUB = 1E17
GAMMA = 0.5483559
+ PHI = 0.7
VTO = 0.7640855
DELTA = 3.0541177
+ UO
= 662.6984452
ETA = 3.162045E-6
THETA = 0.1013999
+ KP
= 1.259355E-4
VMAX = 1.442228E5
KAPPA = 0.3
+ RSH = 7.513418E-3
NFS = 1E12
TPG = 1
+ XJ
= 3E-7
LD
= 1E-13
WD
= 2.334779E-7
+ CGDO = 2.15E-10
CGSO = 2.15E-10
CGBO = 1E-10
+ CJ
= 4.258447E-4
PB
= 0.9140376
MJ
= 0.435903
+ CJSW = 3.147465E-10 MJSW = 0.1977689
)
Table nMOS2-1: T15D MOSIS parameters
AMIS C5 (0.50 micron).
The first task is to create an operational transistor, which may be accomplished by the tutorial
http://www.ece.msstate.edu/~winton/CDNuE/Tutorial/PSinstance.pdf. This tutorial will guide you
through the process of creating a viable MOS transistor as it insults your intelligence.
However, unlike the tutorial, you will need to instantiate model parameters for the MOSIS T15D model.
since we desire to evaluate the MOS device under the ‘physical’ (level-3) model rather than the ‘semiempirical’ (level-7) short-channel model. And since the level-3 model is no longer supported except for
academic exposition, you will need to use the parameter set (copy/paste) as given by table nMOS2-1.
In order to clearly identify this (these) transistor as being defined by the T15D process, change the name
from MbreakN to MnT15D. Also give it a parametric width and length W = {Wn}, L = {Ln}. It is good
form to display your W (dimension) parameter beside your transistor, as represented by figure nMOS2-3.
The length L is assumed to be the same for all transistors.
Figure nMOS2-3: Initialization of MOSFET devices under a specific fabrication process
.Each transistor device then becomes a template that we copy, paste and modify as needed. In this case and
for device analysis it is of necessity that the value of the parameters GAMMA be replaced by a parametric
value, as indicated by the ‘PARAMETERS’ declaration of figure nMOS2-4. Like parametric treatment
should be given to parameters VTO and PHI, which will be of importance to later assignments.
(a) (20pts) Having accomplished the necessary component setup, now construct the circuit indicated by
figure nMOS2-4. This circuit will be your figure nMOS2-1. The AC source V1 is of type VAC.
Figure nMOS2-4: 2-terminal MOS device test circuit sets.
From the construct it should be evident that you are creating a (set of 3 ) ‘2-terminal’ MOS device(s) by
connecting terminals of the 4-terminal device so that it effectively has two terminals. These 2-terminal
devices are consistent with those of ‘MOS capacitances’. Their C(V) characteristics can be called up by use
of the goal function (also shown with the schematic)
YatX(IMG(IG(M1)/VG(M1))/(2*pi*Frequency),1k)
This goal function is (of course) of the same form as used in the exercise for the diode capacitance. As
written it is explicit to transistor M1. The C(V) character of the other transistors is invoked by change of
the component index from M1 to M3, M5, etc., respectively. From figure nMOS2-4 we have set up three
transistors each for which the parameter gamma is different in each case, as indicated by the parameter
declaration. For each of the model files it is necessary to replace the value of gamma with a parametric
name such as {gamma1} for transistor M1 with device model MnT15D3a, {gamma2} for transistor M3
with device model MnT15D3b, etc.
(b) In order to assess C(V) behavior, execute a simulation of the circuit of figure nMOS2-4, with a (decade
scale) AC sweep (Analysis>AC Sweep) of 1kHz < f < 2kHz, and a parametric stepping
(Analysis>parametric) of the VDC source (as a Voltage source) stepped linearly from –2V to +2V
increment .02. This analysis construct will give you a decent sweep of C(MOS) as a function of VG. Use
the set values of gamma and (W, L) values as indicated by Figure nMOS2-4.
(10pts) The use of three transistors will allow you to display a curve family of CMOS(V) as your figure
nMOS2-1. You should expect an outcome something like that shown by Figure nMOS2-5
Extract the following information from each of the traces and list in a short table (your Table nMOS2-1):
(a) (10pts) The (two) transition corners (values of VG) for which the depletion curve = COX
(b) (10pts) The values for Cmos(min). Use part (a) to assess the analytical Cmos(min) and compare the
two values. Be sure to include the area factor associated with the simulation.
(c) (10pts) Speculate why the two values of CMOS(min) (pspice and analytical) are different.
Figure nMOS2-5: 2-terminal MOS C(V) outcomes