EECS 270 Fall 2014, Lecture 25
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What we’ve done and working some
problems…
Today we’re going into review mode. I want to touch on all the material we’ve covered, smooth a few
things out, and work a few problems as a group.
The “big” topics we’ve covered are:
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Logic and logic rules. Recall you are to have the following theorems memorized: Commutativity,
Associativity, Distrbutivity and DeMorgan’s Law. You should be able to use the rest of the
theorems and axioms (found at http://www.eecs.umich.edu/courses/eecs270/Misc/Axioms.pdf)
Computer arithmetic and number representation. Using binary numbers, addition and
subtraction.
o Two’s complement numbers, binary representation of fractions, signed-magnitude.
Including range of representation and overflow.
o Full adders, half-adders, ripple-carry adders, carry-look ahead adders.
o Subtractors, absolute value.
o Question: Can you get overflow when taking the absolute value of a two’s complement
number? A signed magnitude number? An unsigned number?
Combinational logic delay
o Finding the worst-case (longest) delay for a circuit. Glitches. Designing circuits to
minimize delay.
MSI devices.
o Combinational: MUX, adder, decoder, encoder, priority encoder.
o Sequential: Counter (modulo vs. saturating, up/down), register, shift-register, memory.
Memory
o Memory types (dynamic vs. static, volatile vs non-volatile), memory organization
(square memory converted to something more useful).
o Using memory (in a data path mainly)
Verilog
o Combinational logic, sequential logic, state machines. Reg vs. wire.
o Writing and instantiating modules. Being able to convert Verilog to a circuit diagram
and back.
Sequential logic devices
o How to build (SR latch, SR latch with enable, D latch, D flip-flop)
o Non-ideal issues (setup and hold time of a flip-flop, oscillation of a latch, how they are
related)
State machines
o How to design with a state-transition diagram
o Converting from a state-transition diagram to gates and flip-flops and reversing that.
EECS 270 Fall 2014, Lecture 25
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o Encoding SMs (One’s hot vs. minimal), minimizing SMs.
Datapath and control
o How to design datapath and control. Generally we’ve had the datapath and written the
controller for it, but..
o Specific applications:
 One-bus systems (tri-states, reading, timing issues); Basic computer (what
makes it a computer vs. just a state machine).
Underlying implementation options.
o CMOS: Design a circuit with CMOS. Figure out what a CMOS circuit is implementing.
o FPGA: Idea of memory as logic. Understanding as to why. Ability to design with it.
o Understanding of levels of abstraction below us as a general thing (read lecture 15)
Mealy Machines
o Timing issues, pros and cons.
Minimization
o Kmaps, Quine-McClusky, implication tables.
Parity and error correction
o Hamming distance. Various schemes to detect and correct errors.
Lab:
o NES controller, traffic light, Robbie and Renee, calculator, up/down counter. You should
review them.
Misc.
o Logic synchronization: Two (or three) flip-flops. Why they work (most of the time).
When they won’t work (data too fast compared to our clock) and why.
o Tri-state devices: How to use them. How not to use them. Making them out of CMOS.
Questions
1. Design a non-inverting tri-state buffer out of CMOS.
EECS 270 Fall 2014, Lecture 25
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2. Multiple choice.
a. A 6-bit 2’s complement number can represent values from _________ to _________.
b. ______ is the only negative value that has the same 3-bit representation as both a signed
magnitude and 2’s complement number.
c. A 6-input NAND gate has ____________ minterms
d. If F=∑A,B,C,D (0,2,3,4,5) then F has __________ maxterms.
e. DRAM and SRAM both are volatile / are dynamic / store their data in a capacitor.
f.
Write 23.36 as a decimal number: _____________.
g. When comparing a 32-bit ripple-carry adder and a 32-bit carry-lookahead adder, you would
expect the carry-lookahead adder to have more / less / exactly the same delay and use
more / fewer / exactly the same number of gates.
h. Say you want to develop an encoding that allows you to send 2-bit messages (one of
{00,01,10,11}) over a wire. Say you wish to encode that information so that one bit of error
can be detected. How many bits would you need, at a minimum, to encode each of these
messages allowing for one bit of detection? 3 / 4 / 5 / 6 / 10
i.
If A↑B=C and B↑C=A then ↑ is the Boolean operator OR / AND / NOR / NAND/ XOR.
EECS 270 Fall 2014, Lecture 25
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3. Reduce the number of states in the state transition diagram to as few states as. Show your work
and draw the reduced state diagram. [10]
X
X’
X’
B
Z=0
A
Z=1
X’
X
X
X
X’
C
Z=0
D
Z=0
X’
X
X’
X
F
Z=1
X
E
Z=0
A
B
C
D
E
F
A
B
C
D
EECS 270 Fall 2014, Lecture 25
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4. Fill the boxes in both 8x2 memories and the switch matrix below to implement the following logic
functions:
X=((A*B)+(C*!B))⊕(D*E)
Y=A+B+C
Clearly indicate what each Px is connected to in the table below leaving any values that don’t matter
blank. [12]
P0
P1
A
P2
P3
P4
P5
P6
P7
P8
P9
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5. A common task is to count the number of 1s in a string. Let X[6:0] be the input and C[2:0] be the
output. C should be the number of 1s in X. So if X=”1100011” C should be “100” or 4 because there
are 4 1s in X.
Design a circuit which computes C given X. You may only use the following components: 1-bit full
adders, 2-to-4 decoders, 2-to-1 MUXes and 3-input AND gates. To get full credit, you must use as
few devices as possible. Any solution that uses more than 10 devices will get zero points.
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6. Using a K-map find all the minimal sum-of-rpodcuts of F= Σ(PQRS) (1,2,4,5,6,7,8,9,10,12,13,14). Place
a star (*) next to each distinguished 1 in your K-map.
7. Using only standard gates (AND, OR, NOT, XOR), D flip-flops and bubbles as well as a single up
counter with a synchronous reset, design a device which generates a clock with 12 times the period
of the input clock and has a duty cycle of 1/3. The output should be glitch free and your answer
should be clear and neat.