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POWER MANAGEMENT
AUGUST 29 – SEPTEMBER 2, 2011
The course will discuss the most important practical problems facing power management
system engineers and IC designers and their solutions on an advanced level. Among others,
the course covers DC-DC converter topologies, switched mode power supplies, adaptive
power management techniques, bandgap references, linear regulators and battery chargers.
The course will also discuss a fully-integrated CMOS DC-DC, switched-capacitors power
supplies and LDOs.
This course is accepted by the doctoral school of the Swiss Federal Institute of Technology
(EPFL), Lausanne, Switzerland. PhD students can be granted 3 ECTS credits after evaluation
based upon a paper or an oral test on a theme to be agreed with the course program board.
The course fulfills all the criteria imposed by the FP7 EURO-DOTS program, and has been
provisionally granted the EURO-DOTS label. PhD students fulfilling the requirements can
apply for scholarship. Details on the FP7 EURO-DOTS program, program, these requirements
and the application procedure can be found on www.eurodots.org.
PROGRAM
Monday, August 29th 2011
8h30-12h00 am
DC-DC Converters, Topologies & Control Techniques (Richard Redl)
Basic nonisolated dc/dc converter topologies, waveforms, and operating modes. Derivative nonisolated
converters (two-switch buck-boost, SEPIC, Cuk, coupled-inductor buck). Isolated and multi-output
converters. Synchronous rectification. Control techniques: single-loop (constant- frequency and variablefrequency voltage-mode control, voltage regulation without error amplifier), multiple-loop [constantfrequency and variable frequency current-mode control, feedforward control (input-voltage feedforward
for line-transient rejection and for frequency stabilization, load-current feedforward), Vsquare control].
Control for improving efficiency at light load. Overload protection techniques.
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1h30-3h00 pm
Converter Modeling and Feedback Loop Design (Richard Redl)
Averaged small-signal and large-signal models (state-space averaging, direct circuit averaging, method of
injected/absorbed currents). Transfer-function block models. Control-to-output and input-to-output
transfer functions of voltage-mode-controlled and current-mode-controlled converters. The right-halfplane (RHP) zero. Fundamentals of stability analysis. Feedback loop design for phase/gain margin using the
K factor. Practical design examples.
3h30-5h00 pm
Fundamentals of Switched-Mode Power Supplies for Portable Applications (Eduard Alarcon)
Review of power management requirements of key IC building blocks in current and future portable
applications, comparison of on-chip power conversion methods and topologies: Magnetic switching
converters vs switched-capacitor converters (charge-pumps) vs linear power converters (LDO) / Efficiency
optimization / Trends in fully monolithic integration of switching power converters: on-chip reactive
components for switchers: IC-compatible power inductors and low ESR on-chip capacitors, Power MOSFET
switches, efficient switch drivers in standard CMOS technologies / Power management subsystems in an
SoC environment.
Tuesday, August 30th 2011
8h30-10h00 am
Control Techniques and their Integrated Circuit Implementation for Switched-Mode Converters in
Portable Applications (Eduard Alarcon)
Review of control requirements / Voltage-mode and current-mode circuit techniques for analog controllers
/ IC architecture and block design details of analog controller for sliding-mode control, one-cycle control
and neurofuzzy control/ Integration of PFM or pulse-skipping control for light-load efficiency
improvements/ Description of several practical implementations of analog IC controllers / Digital versus
analog control of switching power converters / IC architecture and block design details of digital PWM
controller / design of A-D converters / Area and power efficient implementation of digital pulse width
modulators (DPWM): hybrid and segmented architectures / Quantization and limit-cycle phenomena in
digitally controlled switchers.
10h30-12h00 am
Adaptive Power Management Techniques for Portable Applications (Eduard Alarcon)
Adaptive power supplies for RF power amplifiers/ Slow envelope tracking / Fast Envelope Elimination and
Restoration (EER) technique / Specifications for EDGE, IS95 and 3GPP-WCDMA modulations / Adaptive
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voltage and threshold scaling for low-power microprocessor and DSP supply/ Description of several
practical implementations of adaptive power management.
1h30-5h00 pm
Bandgap References (Barrie Gilbert)
Voltage references derived from the base-emitter voltage of bipolar transistors, and why they are generally
known as "Bandgaps." Fundamental ideas related to most circuits, including noise, temperature behavior
and trimming, curvature and curvature correction, and sensitivity to component variability. Some basic
circuits and the practical issues related to their use in power management. Additional examples which
illustrate the use of parasitic bipolar transistors to derive a reference voltage on CMOS circuits.
Wednesday, August 31st 2011
8h30-12h00 am
CMOS Linear Regulators, Design and Case Studies (Maher Kayal)
Summary of conventional CMOS fully integrated linear voltage regulators. Review of CMOS OTA
design trade-offs, output stage for Low Dropout Regulator (LDO) and non Low Dropout Regulator.
Stability conditions. Overview of main techniques for efficiency and stability improvement. Case
studies and practical implementations in CMOS technology of common drain (LDO) with depletion
output transistor and battery charger for mobile phone using shunt regulator.
1h30-5h00 pm
Battery Charging Techniques & Circuits for Notebook Computers & Cellular Phones (Thomas
Szepesi)
NiCad, NiMH, LiIOn, Li-Metal and Li-Polimer batteries and their properties. Charging and charge
termination techniques for the different battery chemistries. Off-line, DC/DC and linear battery
charger circuits.
Thursday, September 1st 2011
8h30-10h00 am
DC-DC: From Discrete Towards Fully CMOS Integrated (Michiel Steyaert )
Trends and techniques towards fully integrated CMOS DC-DC converters is studied. Both inductive and
capacitive DC-DC converters are analyzed. The different required on chip components such as inductors are
discussed. Different control loop techniques are presented in order to achieve high integrated density and
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meanwhile achieving low ripple requirements. Many designed cases, both boost and buck are analyzed and
compared with classical LDO regulators.
10:30-12h00 am + 1h30-5h00 pm
Switched-Capacitor Power Supplies (Jesper Steensgaard)
General overview of switched-capacitor (SC) power supplies: topologies and properties. Efficiency
analysis, and circuit techniques that may be used to improve the efficiency. How to design and
evaluate CMOS switches for SC power supplies. Step by step design of a voltage doubler. Analysis
and several practical examples of how to design voltage multipliers.
Friday, September 2nd 2011
8h30-10h00 am
Transistor-Level Off-Line DC-DC Controller Design (Robert Blauschild)
Typical application and design of a current-mode off-line, switched-mode power supply. Review of the
application diagram and general theory of operation. Start-up and bias techniques. The design of critical
blocks, including voltage references, oscillators, error amplifiers, protection circuits, and output drive, with
emphasis on design tradeoffs and performance in bipolar and CMOS technologies.
10h30-12h00 am
Design of the LDO's with Instant Load Regulation and Unconditional Stability (Vadim Ivanov)
Discussed is a new class of LDO's: any load stable, with instant transient response, large power supply
rejection and low noise. Examples include the embedded in SoC LDOs for the SRAM unit (5 ns reaction time
on the load steps), LDO for radio transmitter (shaping the required noise vs. frequency curve) and LDO for
memory retention in the shutdown state (300 nA quiescent current). These LDOs can operate with or
without off-chip load capacitors; they are robust to the process and temperature variations and portable to
any CMOS process.
1h30-3h00 pm
Circuit Techniques for Integrated Switching Regulators (Vadim Ivanov)
Power switches: static and dynamic power loss, switch sizing, wire bonds and their inductance, parasitic
vertical PNP and lateral NPN structures, substrate noise, signal grounding and isolation of the control
circuitry. Switch Control: Low and high-side gate drivers, use of the bootstrap capacitors with charge
regeneration, transfer of the control signal to the high-side. Low and high-side synchronous rectifiers:
comparator design, minimization of delays, elimination of shoot-through currents. Feedback and frequency
compensation: continuous and discontinuous operation, current and voltage mode; inductor current
sensing with and without external elements; oscillator and PWM circuits; error amplifier.
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WHO SHOULD ATTEND
The prerequisite for the course is a basic knowledge of semiconductor devices and
circuits. It addresses the training needs of all electrical engineering community involved in
microelectronics and nanoelectronics.
PhD students and members of academic institutes will particularly benefit from an update information for their current research and teaching. This course is intended for any
IC design engineer already working in academia or semiconductor industry, technical
supervisors, managers and directors working in, or having responsibilities for:
- IC design, layout and characterization
- Research and development
- Decision making for technology choice and architectures
- Projects completion
- Teaching
The course aims to cover a broad view on the subject, from short introduction to an indepth knowledge and to practical aspects and hints, which can be applied immediately
after the course. This is why this course will have special appeal to different level of
expertise, from beginners to advanced specialists in the field.
COURSE LOCATION
The course will take place at the premises of the Federal Institute of Technology (EPFL),
Lausanne, Switzerland.
Route description: http://www.mead.ch/info-ch/course-venue_ch.htm
FEES AND REGULATIONS
The fee of EUR 2,100 includes all lectures, a complete set of course notes on electronic
format, lunches and two daily coffee breaks. One social evening will be organized for all
attendees and instructors of the course. The social evening is usually held on the
Wednesday evening.
Discounted fee for PhD students: EUR 1,000.
Registration deadline: July 29, 2011.
Payment deadline: August 19, 2011.
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Hotel accommodations and meals other than lunches are note included in the course fee.
Mead reserves the right to cancel the program up to one month before the start of the
course and its liability is limited to a full refund of the course fee.
Fees will be fully refunded if a cancellation is received by the payment deadline. No refund
will be issued for cancellation notices received after this date. Registration fees may be
transferred to an alternative attendee or used to pay for participation in a future MEAD
course. Unpaid registrants are responsible for fees unless a cancellation is received by the
deadline for payment. All reimbursement will incur a 10% fee per course.
For any further information or to contact us please see our web site: www.mead.ch
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