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Operation of an n MOS device Gate Polysilicon Gate dielectric πππ2 πππ2 π+ π+ Source Drain P Substrate Figure 1 Let us consider the operation of n MOS device such as the one shown in Fig 1. Initially we connect the source, drain, gate and bulk to “0” source and observe its behavior. ππ = 0 ππ = 0 π+ ππ· = 0 π+ Depletion layer Depletion layer ππ Build in potential ππ΅ = 0 Figure 2 Initially electrons will be attracted to the P region, while holes will be attracted to the n+ region. Equilibrium will be reached when barriers are formed at the depleted regions at the interface of N and the P regions, around the source and the drain in the substrate as shown in Fog.2. No current flows between source and drain. Now with ππ = ππ΅ = 0 we apply ππ > 0 at the gate. The positive voltage at the gate will attract the electrons to the surface. While holes will be depleted thus depletion layer is formed under the gate. No current flows between source and the drain. 0 < ππ ≥ ππ‘β πΌπ·π = 0 ππ > 0 but small < ππ A continuous depletion region is formed from source to drain, but no current is flows as shown in Fig.3. 1 ππ > 0 0π£ 0π£ n n P 0π£ Figure 3 0π£ π > ππ 0π£ Depletion ππΉ Channel 0π£ Figure 4 Now we keep increasing ππππ‘π . Now extra electrons are attracted beneath the gate. At some point the p Type material will be n+ due to the extra electrons and at same density of n+ of the source or drain. At this point we say the material is inverted and thus a continuous channel is formed between the source and the drain as shown in Fig. 4. The gate voltage at this point is ππππ‘π = ππ‘βπππ βπππ . Parameters affecting this inversion are: The gate voltage the source to bulk voltage and a parameter, πΎ called the body effect, The threshold voltage can be obtained by ππ = ππ‘β0 + πΎ(√|−2ππΉ + πππ΅ | − √|2ππΉ |) Equation 1 where ππ‘β0 = π‘βπ π‘βπππ βπππ π£πππ‘πππ π€ππ‘β π§πππ ππππ ππΉ = π‘βπ ππ’πππ πππ‘πππ‘πππ ππ π‘βπ πππππ πππ‘πππ‘πππ πππ΅ = π‘βπ π ππ’πππ π‘π ππ’ππ π£πππ‘πππ ππ = 2ππΉ ππ π‘βπ π π’πππππ πππ‘πππ‘πππ 2 Also note that ππ is negative for n MOS and positive for p MOS πΈ, the body effect coefficient or the substrate bias coefficient is positive for n MOS and negative for p MOS. The above parameters change from process to process and as the technology changes. ππ is +ve for n MOS and –ve for p MOS for an enhancement mode transistors. Substrate bias voltage πππ΅ is +ve for n MOS and –ve for p MOS. Although for many processes the threshold voltage ππ‘β is fixed, however sometimes it is necessary to adjust the threshold voltage. NMOS transistors implanted with n- type dopant results in a decrease in threshold voltage. An effective mean to adjust the threshold voltage is to change the doping concentration through ion implantation. Note that n MOS transistor implanted with p- type dopant results in an increase in the threshold voltage. Accordingly the following model can be used ππ‘ = ππ‘0 + (π. π·πΌ ⁄πΆππ₯ ) Equation 2 where π is charge of an electron = 1.6 ∗ 10−19 πΆππ⁄ππ‘ππ π·πΌ = Dose of dopant in the channel (ππ‘πππ ⁄ππ2 ) πΆππ₯ = Gate oxide capacitance per unit area ππΉ⁄ππ2 The necessity for adjusting the gate threshold voltage is primarily due to variation in oxide thickness and the variation in doping concentration. 3 Linear Region ππ = 0 πππ ≥ ππ πn+ + ππ·π > 0 < ππ·ππ΄π πn+ + P Channel informed Figure 5 Referring to Fig 5 with ππππ‘π > ππ‘βπππ βπππ we apply a small positive voltage to the drain. Thus current can flow from drain to source. At this point the channel acts like a linear resistor. As we increase ππ·π the current is increased at he some time the channel gets thinner at the drain and the depletion layer widens up. As we keep increasing ππ·π the channel at the drain end is diminished. We say that the channel is pinched off. The Vdrain at this point is called ππ·π ππ‘ , and the channel with ππ·π → ππ·π ππ‘ is non-linear and the transistor is working in the non-linear region shown in fig 6. ππ = 0 πππ > ππ ππ·π = ππ·ππ΄π depletion πππ΅π = = 00 ππ = 0 Figure 6 Linear region The current at this stage is a function of πππ , ππ , ππ·π , transistor geometry, mobility of the channel and the dielectric constant of the gate. In the linear region, the channel has the shape shown in fig 7. 4 Source dy Drain Width,W y Figure 7 To determine an expression for the current in the linear region, we will look into a segment length dy, width W across the path Source Drain where we assume that the current flows uniformly. The incremental voltage drop along the incremental segment is πππ = πΌπ· ππ ππ¦ now ππ = π ππ π Equation 3 Equation 4 πΌ and ππΌ = πΆππ Equation 5 where ππΌ in the total charge in the inversion layer and ππ is the channel voltage at point y. Substituting Eq 4 and 5 in (3) we have ππ¦ ππ ππΆππ πΌπ· ππ¦ = ππ ππΆππ πππ Equation 6 Where the channel voltage is πππ − ππ‘β − ππ¦ Equation 7 πππ = πΌπ· ∗ Substituting Eq7 in Eq 4 and integrating πΏ πππ ∫ πΌπ· ππ¦ = ∫ 0 πΌπ·Μ = π πΏ 0 ππ πΆπ(πππ − ππ‘β − ππ )πππ 1 2 ππ πΆ(πππ − ππ )πππ − 2 πππ Equation 8 Now ππ πΆ = π ′ is termed process parameter π And π ′ πΏ = π½ is termed device conductance/parameter 1 2 Then πΌπ· = π½ [(πππ − ππ‘ )πππ − 2 πππ ] , Drain-Source current in the linear region when ππ·ππ΄π > πππ > Vth 5 Saturation Region When ππ·π is increased above ππ·π ππ‘ then the channel is pinched off and channel length is decreased as shown in Fig 8. This means there is no continuous channel as well as the depletion layer widens. ππ = 0 πππ > ππ ππ· > ππ·ππ΄π n+ Depletion Layer Channel P+ Figure 8 - Saturation Region That implies that there is no continuous layer below the gate. However current flows from Drain to Source. Electrons arriving at the edge of the inverted region are injected in the depletion near the drain and swept away to the drain by the drain voltage. The current under these circumstances behaves differently. If ππ·π ππ‘ is the drain voltage at the on- set of channel being pinched off, then theoretically increasing the drain voltage beyond ππ·π ππ‘ will not increase the current and stays constant at π½ πΌπ·π ππ‘ = 2 (πππ − ππ‘ ) 2 Equation 10 Practically however as πππ is increased above ππ·π ππ‘ there is a slight increase in the current and the following expression represents the current more accurately. π½ 2 πΌπ·π ππ‘ = 2 (πππ − ππ‘ ) (1 + ππππ ) Equation 11 Where π is the channel length modulation coefficient and is constant for a given process. Finally there are 3 regions of operation for the transistor For n MOS and p MOS as follows: Region of operation NMOS PMOS 6 πππ < ππ‘ πΌπ· = 0 πππ ≥ ππ‘ & πππ < πππ − ππ‘ Cut off πΌπ· = ππ πΆππ₯ Linear πππ > ππ‘ πΌπ· = 0 πππ ≤ ππ‘ & πππ > πππ − ππ‘ 2 π πππ 2 [(πππ − ππ‘ ) − ] πΏ 2 2 πΌπ· = ππ πΆππ₯ 2 2 2 or πΌπ· = π½π [(πππ − ππ‘ ) − π2ππ ] πππ ≥ ππ‘ & πππ ≥ πππ − ππ‘ or πΌπ· = π½π [(πππ − ππ‘ ) − π2ππ ] πππ ≤ ππ‘ & πππ ≤ πππ − ππ‘ ππ πΆππ₯ π 2 (π − ππ‘ ) (1 + ππππ ) 2 πΏ ππ π½π 2 πΌπ· = (π − ππ‘ ) (1 + ππππ ) 2 ππ ππ πΆππ₯ π 2 (π − ππ‘ ) (1 + ππππ ) 2 πΏ ππ π½π 2 πΌπ· = (πππ − ππ‘ ) (1 + ππππ ) 2 πΌπ· = Saturation 2 π πππ 2 [(πππ − ππ‘ ) − ] πΏ 2 πΌπ· = Note that the n MOS and the p MOS have opposite polarity and Vt , λ for n MOS are positive while for p MOS they are –ve. Also note the reverse polarity for regions of operation. πΌππ πΌππ Saturation Cut-off linear ππ‘β πππ 3 > πππ 2 πππ 2 > πππ 1 πππ 1 ππ·π ππ‘ πππ πππ Figure 9 Figure 10 Fig 9,10 show variation of the drain current with Vds and Vgs 7