Operation of an n MOS device
Gate Polysilicon
Gate dielectric
𝑆𝑖𝑂2
𝑆𝑖𝑂2
𝑛+
𝑛+
Source
Drain
P
Substrate
Figure 1
Let us consider the operation of n MOS device such as the one shown in Fig 1. Initially
we connect the source, drain, gate and bulk to “0” source and observe its behavior.
𝑉𝑠 = 0
𝑉𝑔 = 0
𝑛+
𝑉𝐷 = 0
𝑛+
Depletion layer
Depletion layer
𝜑𝑓
Build in potential
𝑉𝐵 = 0
Figure 2
Initially electrons will be attracted to the P region, while holes will be attracted to the n+
region. Equilibrium will be reached when barriers are formed at the depleted regions at the
interface of N and the P regions, around the source and the drain in the substrate as shown
in Fog.2. No current flows between source and drain. Now with 𝑉𝑠 = 𝑉𝐵 = 0 we apply
𝑉𝑔 > 0 at the gate. The positive voltage at the gate will attract the electrons to the surface.
While holes will be depleted thus depletion layer is formed under the gate. No current flows
between source and the drain.
0 < 𝑉𝑔 ≥ 𝑉𝑡ℎ
𝐼𝐷𝑆 = 0
𝑉𝑔 > 0 but small < 𝑉𝑇 A continuous depletion region is formed from source to drain, but
no current is flows as shown in Fig.3.
1
𝑉𝑔 > 0
0𝑣
0𝑣
n
n
P
0𝑣
Figure 3
0𝑣
𝑉 > 𝑉𝑇
0𝑣
Depletion
𝜑𝐹
Channel
0𝑣
Figure 4
Now we keep increasing 𝑉𝑔𝑎𝑡𝑒 . Now extra electrons are attracted beneath the gate. At
some point the p Type material will be n+ due to the extra electrons and at same density of
n+ of the source or drain. At this point we say the material is inverted and thus a continuous
channel is formed between the source and the drain as shown in Fig. 4. The gate voltage at
this point is 𝑉𝑔𝑎𝑡𝑒 = 𝑉𝑡ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 . Parameters affecting this inversion are: The gate voltage
the source to bulk voltage and a parameter, 𝛾 called the body effect,
The threshold voltage can be obtained by
𝑉𝑇 = 𝑉𝑡ℎ0 + 𝛾(√|−2𝜑𝐹 + 𝑉𝑆𝐵 | − √|2𝜑𝐹 |)
Equation 1
where 𝑉𝑡ℎ0 = 𝑡ℎ𝑒 𝑡ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑤𝑖𝑡ℎ 𝑧𝑒𝑟𝑜 𝑏𝑖𝑎𝑠
𝜑𝐹 = 𝑡ℎ𝑒 𝑏𝑢𝑖𝑙𝑑 𝑝𝑜𝑡𝑒𝑛𝑡𝑖𝑎𝑙 𝑜𝑟 𝑡ℎ𝑒 𝑓𝑒𝑟𝑚𝑖 𝑝𝑜𝑡𝑒𝑛𝑡𝑖𝑎𝑙
𝑉𝑆𝐵 = 𝑡ℎ𝑒 𝑠𝑜𝑢𝑟𝑐𝑒 𝑡𝑜 𝑏𝑢𝑙𝑘 𝑣𝑜𝑙𝑡𝑎𝑔𝑒
𝜑𝑠 = 2𝜑𝐹 𝑖𝑠 𝑡ℎ𝑒 𝑠𝑢𝑟𝑓𝑎𝑐𝑒 𝑝𝑜𝑡𝑒𝑛𝑡𝑖𝑎𝑙
2
Also note that 𝝋𝑭 is negative for n MOS and positive for p MOS
𝜸, the body effect coefficient or the substrate bias coefficient is positive for n MOS and
negative for p MOS.
The above parameters change from process to process and as the technology changes. 𝑉𝑇
is +ve for n MOS and –ve for p MOS for an enhancement mode transistors. Substrate bias
voltage 𝑉𝑆𝐵 is +ve for n MOS and –ve for p MOS.
Although for many processes the threshold voltage 𝑉𝑡ℎ is fixed, however sometimes it is
necessary to adjust the threshold voltage.
NMOS transistors implanted with n- type
dopant results in a decrease in threshold voltage.
An effective mean to adjust the threshold voltage is to change the doping concentration
through ion implantation. Note that n MOS transistor implanted with p- type dopant results
in an increase in the threshold voltage.
Accordingly the following model can be used
𝑉𝑡 = 𝑉𝑡0 + (𝑞. 𝐷𝐼 ⁄𝐶𝑜𝑥 )
Equation 2
where 𝑞 is charge of an electron = 1.6 ∗ 10−19 𝐶𝑜𝑙⁄𝑎𝑡𝑜𝑚
𝐷𝐼 = Dose of dopant in the channel (𝑎𝑡𝑜𝑚𝑠⁄𝑐𝑚2 )
𝐶𝑜𝑥 = Gate oxide capacitance per unit area 𝑃𝐹⁄𝑐𝑚2
The necessity for adjusting the gate threshold voltage is primarily due to variation in oxide
thickness and the variation in doping concentration.
3
Linear Region
𝑉𝑠 = 0
𝑉𝑔𝑠 ≥ 𝑉𝑇
𝑛n+
+
𝑉𝐷𝑆 > 0 < 𝑉𝐷𝑆𝐴𝑇
𝑛n+
+
P
Channel informed
Figure 5
Referring to Fig 5 with 𝑉𝑔𝑎𝑡𝑒 > 𝑉𝑡ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 we apply a small positive voltage to the drain.
Thus current can flow from drain to source. At this point the channel acts like a linear
resistor. As we increase 𝑉𝐷𝑆 the current is increased at he some time the channel gets
thinner at the drain and the depletion layer widens up. As we keep increasing 𝑉𝐷𝑆 the
channel at the drain end is diminished. We say that the channel is pinched off. The Vdrain
at this point is called 𝑉𝐷𝑠𝑎𝑡 , and the channel with 𝑉𝐷𝑆 → 𝑉𝐷𝑠𝑎𝑡 is non-linear and the
transistor is working in the non-linear region shown in fig 6.
𝑉𝑠 = 0
𝑉𝑔𝑠 > 𝑉𝑇
𝑉𝐷𝑆 = 𝑉𝐷𝑆𝐴𝑇
depletion
𝑉𝑉𝐵𝑠 =
= 00
𝑉𝑠 = 0
Figure 6
Linear region
The current at this stage is a function of 𝑉𝑔𝑠 , 𝑉𝑇 , 𝑉𝐷𝑆 , transistor geometry, mobility of the
channel and the dielectric constant of the gate.
In the linear region, the channel has the shape shown in fig 7.
4
Source
dy
Drain
Width,W
y
Figure 7
To determine
an expression for the current in
the linear region, we will look into a segment length dy, width W across the path Source
Drain where we assume that the current flows uniformly.
The incremental voltage drop along the incremental segment is
𝑑𝑉𝑐 = 𝐼𝐷 𝑑𝑅
𝑑𝑦
now 𝑑𝑅 = 𝜇 𝑊𝑄
𝑛
Equation 3
Equation 4
𝐼
and 𝑄𝐼 = 𝐶𝑉𝑐
Equation 5
where 𝑄𝐼 in the total charge in the inversion layer and 𝑉𝑐 is the channel voltage at point y.
Substituting Eq 4 and 5 in (3) we have
𝑑𝑦
𝜇𝑛 𝑊𝐶𝑉𝑐
𝐼𝐷 𝑑𝑦 = 𝜇𝑛 𝑊𝐶𝑉𝑐 𝑑𝑉𝑐
Equation 6
Where the channel voltage is 𝑉𝑔𝑠 − 𝑉𝑡ℎ − 𝑉𝑦
Equation 7
𝑑𝑉𝑐 = 𝐼𝐷 ∗
Substituting Eq7 in Eq 4 and integrating
𝐿
𝑉𝑑𝑠
∫ 𝐼𝐷 𝑑𝑦 = ∫
0
𝐼𝐷̇ =
𝑊
𝐿
0
𝜇𝑛 𝐶𝑊(𝑉𝑔𝑠 − 𝑉𝑡ℎ − 𝑉𝑐 )𝑑𝑉𝑐
1
2
𝜇𝑛 𝐶(𝑉𝑔𝑠 − 𝑉𝑇 )𝑉𝑑𝑠 − 2 𝑉𝑑𝑠
Equation 8
Now 𝜇𝑛 𝐶 = 𝑘 ′ is termed process parameter
𝑊
And 𝑘 ′ 𝐿 = 𝛽 is termed device conductance/parameter
1
2
Then 𝐼𝐷 = 𝛽 [(𝑉𝑔𝑠 − 𝑉𝑡 )𝑉𝑑𝑠 − 2 𝑉𝑑𝑠
] , Drain-Source current in the linear region when
𝑉𝐷𝑆𝐴𝑇 > 𝑉𝑔𝑠 > Vth
5
Saturation Region
When 𝑉𝐷𝑆 is increased above 𝑉𝐷𝑠𝑎𝑡 then the channel is pinched off and channel length is
decreased as shown in Fig 8. This means there is no continuous channel as well as the
depletion layer widens.
𝑉𝑠 = 0
𝑉𝑔𝑠 > 𝑉𝑇
𝑉𝐷 > 𝑉𝐷𝑆𝐴𝑇
n+
Depletion Layer
Channel
P+
Figure 8 - Saturation Region
That implies that there is no continuous layer below the gate. However current flows from
Drain to Source. Electrons arriving at the edge of the inverted region are injected in the
depletion near the drain and swept away to the drain by the drain voltage.
The current under these circumstances behaves differently. If 𝑉𝐷𝑠𝑎𝑡 is the drain voltage at
the on- set of channel being pinched off, then theoretically increasing the drain voltage
beyond 𝑉𝐷𝑠𝑎𝑡 will not increase the current and stays constant at
𝛽
𝐼𝐷𝑠𝑎𝑡 = 2 (𝑉𝑔𝑠 − 𝑉𝑡 )
2
Equation 10
Practically however as 𝑉𝑑𝑠 is increased above 𝑉𝐷𝑠𝑎𝑡 there is a slight increase in the current
and the following expression represents the current more accurately.
𝛽
2
𝐼𝐷𝑠𝑎𝑡 = 2 (𝑉𝑔𝑠 − 𝑉𝑡 ) (1 + 𝜆𝑉𝑑𝑠 )
Equation 11
Where 𝜆 is the channel length modulation coefficient and is constant for a given process.
Finally there are 3 regions of operation for the transistor
For n MOS and p MOS as follows:
Region of operation
NMOS
PMOS
6
𝑉𝑔𝑠 < 𝑉𝑡
𝐼𝐷 = 0
𝑉𝑔𝑠 ≥ 𝑉𝑡 & 𝑉𝑑𝑠 < 𝑉𝑔𝑠 − 𝑉𝑡
Cut off
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥
Linear
𝑉𝑔𝑠 > 𝑉𝑡
𝐼𝐷 = 0
𝑉𝑔𝑠 ≤ 𝑉𝑡 & 𝑉𝑑𝑠 > 𝑉𝑔𝑠 − 𝑉𝑡
2
𝑊
𝑉𝑑𝑠
2
[(𝑉𝑔𝑠 − 𝑉𝑡 ) −
]
𝐿
2
2
𝐼𝐷 = 𝜇𝑝 𝐶𝑜𝑥
2
2
2
or 𝐼𝐷 = 𝛽𝑛 [(𝑉𝑔𝑠 − 𝑉𝑡 ) − 𝑉2𝑑𝑠]
𝑉𝑔𝑠 ≥ 𝑉𝑡 & 𝑉𝑑𝑠 ≥ 𝑉𝑔𝑠 − 𝑉𝑡
or 𝐼𝐷 = 𝛽𝑝 [(𝑉𝑔𝑠 − 𝑉𝑡 ) − 𝑉2𝑑𝑠]
𝑉𝑔𝑠 ≤ 𝑉𝑡 & 𝑉𝑑𝑠 ≤ 𝑉𝑔𝑠 − 𝑉𝑡
𝜇𝑛 𝐶𝑜𝑥 𝑊
2
(𝑉 − 𝑉𝑡 ) (1 + 𝜆𝑉𝑑𝑠 )
2 𝐿 𝑔𝑠
𝛽𝑛
2
𝐼𝐷 =
(𝑉 − 𝑉𝑡 ) (1 + 𝜆𝑉𝑑𝑠 )
2 𝑔𝑠
𝜇𝑝 𝐶𝑜𝑥 𝑊
2
(𝑉 − 𝑉𝑡 ) (1 + 𝜆𝑉𝑑𝑠 )
2 𝐿 𝑔𝑠
𝛽𝑝
2
𝐼𝐷 = (𝑉𝑔𝑠 − 𝑉𝑡 ) (1 + 𝜆𝑉𝑑𝑠 )
2
𝐼𝐷 =
Saturation
2
𝑊
𝑉𝑑𝑠
2
[(𝑉𝑔𝑠 − 𝑉𝑡 ) −
]
𝐿
2
𝐼𝐷 =
Note that the n MOS and the p MOS have opposite polarity and Vt , λ for n MOS are
positive while for p MOS they are –ve. Also note the reverse polarity for regions of
operation.
𝐼𝑑𝑠
𝐼𝑑𝑠
Saturation
Cut-off
linear
𝑉𝑡ℎ
𝑉𝑔𝑠3 > 𝑉𝑔𝑠2
𝑉𝑔𝑠2 > 𝑉𝑔𝑠1
𝑉𝑔𝑠1
𝑉𝐷𝑠𝑎𝑡
𝑉𝑑𝑠
𝑉𝑑𝑠
Figure 9
Figure 10
Fig 9,10
show variation of the drain current with Vds and Vgs
7