Side-Channel Resistant Cryptography on FPGAs

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University of Pennsylvania
Department of Electrical and Systems Engineering
ESE, CIS SENIOR DESIGN PROJECT
ADVISOR PROJECT SUBMISSION FORM
1. Project Title: Side-Channel Resistant Cryptography on FPGAs
2. Proposer's Name: Nadia Heninger & André DeHon
E-mail: [email protected], [email protected]
Are you willing and able to serve as advisor for this project? _X_ Yes; ___ No
3. Brief Project Description:
Attackers have demonstrated remarkable ability to use side-channel information (e.g. power
consumption profile, RF emissions) to extract information (including the secret keys). How
much can we reduce the rate of data leakage with careful hardware design? And at what cost?
4. Project Design Objectives:
Implement cryptography routines with one or more protection schemes. Quantify resource
and implementation costs and effectiveness at preventing information leakage. Protection
against side-channel attacks is especially important for smart-card applications.
5. Project Prerequisites:
What specific knowledge (e.g. courses or topics) and skills (e.g. programming languages or software
packages) will this project require? Please rank order the knowledge and skills you have identified, with
the most important at the top of the list.
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Digital Design (ESE170, 171)
Discrete Math (CIS160)
Familiarity with electrical power issues and design styles (ESE215, ESE216 or ESE370)
Exposure to modern public-key cryptography a plus, but we figure you can pick it up
as part of the project.
References:
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Differential Power Analysis: http://www.cryptography.com/public/pdf/DPA.pdf
Differential Power Analysis attacks on FPGA bitstream encryption:
http://eprint.iacr.org/2011/391
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Attacks on Smart Cards: http://www.cs.uic.edu/~sloan/my-papers/ieee-messergesproof.pdf
One proposed protection scheme:
http://www.cs.berkeley.edu/~daw/papers/privcirc-crypto03.pdf
Proposal for DPA resilience on FPGA 10.1109/FPT.2010.5681790
Conference with relevant work: www.chesworkshop.org
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