Computer Architecture and Network
120CT - Portfolio
17th of April 2015
Module leader: Dianabasi Nkantah
Student: Andrei-Gabriel Stroescu
Student ID: 5768367
1
Contents
Exercise 1.1: Number Systems................................................................ 3
Exercise 1.2: Functional Units from Logic Gates and Sequential Logic ... 5
Exercise 1.3: Peripheral Devices ........................................................... 11
HP SimpleSave Portable External Hard Drive ..................................... 11
Logitech Z-5500 THX Certified 5.1 Speaker System............................ 12
Apogee GiO Guitar Interface .............................................................. 13
Exercise 1.4: Assembly Language ......................................................... 15
Exercise 2.1: Data Representation........................................................ 18
Exercise 2.2: Introduction to Logic Circuit Design ................................ 19
Exercise 2.3: More Logic Gates and Logic Circuit Design ...................... 22
Exercise 2.4: Computer Function and Interconnection ........................ 25
Exercise 2.5: Memory ........................................................................... 27
Exercise 2.6: Processors and Amdahl’s Law.......................................... 30
Exercise 2.7: Machine Sequence and Micro-operations....................... 33
Exercise 2.8: Practice for Phase Test 3 ................................................. 36
Reflective Report .................................................................................. 41
2
Exercise 1.1: Number Systems
1) Convert the following binary numbers to decimal:
a.
1101 – 1+4+8 = 13
b.
01101001 = 1+8+32+64 = 105
c.
11 0100 1110.101 = 2+4+8+64+256+512 = 846.625
2) Convert the following decimal numbers to binary:
a.
67 - 1000011
b.
381 - 101111101
c.
40.375 – 101000.011
3) Convert the following decimal numbers to 8-bit binary values:
a.
48 = 60
b.
103 = 117
c.
165 = 245
4) Convert the following hexadecimal numbers to binary:
a.
63F – 0110 0011 1111
b.
BEEF – 1011 1110 1110 1111
c.
F00D – 1111 0000 0000 1101
5) Convert the following binary numbers to hexadecimal:
a.
1001 0011 – 93
b.
1010 0010 1110 0101 – A2D5
c.
11 0010 0111 0110 0001 - 32761
6) Convert the following hexadecimal numbers to decimal:
a.
A7E – 14 + 7*16 + 10* 256
b.
95BF – 15 + 11*16+ 5*256+9*4096
c.
50B – 11 + 0* 16 + 5 * 256
7) Convert the following decimal numbers to hexadecimal:
a.
46 – 2E
b.
139 – 8B
c.
2014 – 7DE
8) Convert the following octal numbers to binary:
a.
627 – 110 010 111
b.
4550 – 100 101 101 000
3
c.
2771 – 010 111 111 001
9) Convert the following binary numbers to octal:
a.
101 011 001 - 531
b.
111 100 000 - 740
c.
1 100 101 011 – 1453
10) Convert the following octal numbers to decimal:
a.
45 – 4*8 + 5 = 37
b.
731 – 7*64+3*8+1 = 473
c.
173 – 64 + 7*8 +3 = 123
11) Convert the following decimal numbers to octal:
a.
68 = 104
b.
99 = 113
c.
145 = 221
12) Convert each of the following decimal numbers to BCD:
a.
8 = 0000 1000
b.
39 = 0011 1001
c.
526 = 0101 0010 0110
13) Convert each of the following BCD numbers to decimal:
a.
1001 - 9
b.
0010 0111 – 27
c.
0110 0001 0100 - 614
14) Perform the following arithmetic operations:
a.
11012 + 10112
b.
001011002 + 000100012
c.
110102 – 101112
d.
11102 – 112
e.
3716 + 2916
f.
A016 + 6B16
g.
C816 – 3A16
h.
FD16 – 8816
-
15) My name (“Dianabasi”) in ASCII is “0x44 0x69 0x61 0x6E 0x61 0x62 0x61 0x73 0x69”. What is your name converted
into ASCII?
Andrei – 0x41 0x6E 0x64 0x72 0x65 0x69
4
Exercise 1.2: Functional Units from Logic Gates and Sequential
Logic
SECTION A
1) A half-adder adds two bits. (True)
2) A half-adder has a sum output only. (False)
3) A full-adder adds three bits and produces two outputs. (True)
4) Two 4-bit numbers can be added using two full-adders. (False)
5) When the two input bits are both 1 and the carry input bit is a 1, the sum output of a full-adder is 0. (False)
6) A decoder detects the presence of a specified combination of input bits. (True)
7) The 4-line-to-10-line decoder and the 1-of-10 decoder are two different types. (True)
8) An encoder essentially performs a reverse decoder function. (True)
9) A multiplexer is a logic circuit that allows digital information from a single source to be routed onto several lines. (True)
10) A latch has two stable states. (True)
11) A latch is considered to be in the SET state when the Q output is LOW. (False)
12) A gated D latch must be enabled in order to change state. (True)
13) Flip-flops and latches are both bistable devices. (True)
14) An edge-triggered D flip-flop changes state whenever the D input changes. (False)
15) A clock input is necessary for an edge-triggered flip-flop. (True)
16) In an asynchronous counter, all flip-flops change state at the same time. (False)
17) In a synchronous counter, all flip-flops are clocked simultaneously. (True)
18) An asynchronous counter is also known as a ripple counter. (True)
19) Shift registers consist of an arrangement of flip-flops. (True)
20) Two functions of a shift register are data storage and data movement. (True)
21) In a serial shift register, several data bits are entered at the same time. (False)
22) All shift registers are defined by specified sequences. (False)
23) A shift register can have both parallel and serial outputs. (True)
24) A shift register with four stages can store a maximum count of fifteen. (True)
SECTION B
1) A half-adder is characterized by
a) two inputs and two outputs
b) three inputs and two outputs
c)
two inputs and three outputs
d) two inputs and one output
5
2) A full-adder is characterized by
a)
two inputs and two outputs
b) three inputs and two outputs
c)
two inputs and three outputs
d) two inputs and one output
3) The inputs to a full-adder are A = 1, B = 1, Cin = 0. The outputs are
a)
SUM = 1, Cout = 1
b) SUM = 1, Cout = 0
c)
SUM = 0, Cout = 1
d) SUM = 0, Cout = 0
4) A 4-bit parallel adder can add
a) two 4-bit binary numbers
b) two 2-bit binary numbers
c)
four bits at a time
d) four bits in sequence
5) To expand a 4-bit parallel adder to an 8-bit parallel adder, you must
a)
use four 4-bit address with no interconnections
b) use two 4-bit adders and connect the sum outputs of one to the bit inputs of the other
c)
use eight 4-bit adders with no interconnections
d) use two 4-bit adders with the carry output of one connected to the carry input of the other
6) In general, a multiplexer has
a)
one data input, several data outputs, and selection inputs
b) one data input, one data output, and one selection input
c)
several data inputs, several data outputs, and selection inputs
d) several data inputs, one data output, and selection inputs
7) Data selectors are basically the same as
a) Decoders
b) demultiplexers
c)
multiplexers
d) encoders
8) If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be
6
a) set
b) reset
c)
invalid
d) clear
9) The invalid state of an S-R latch occurs when
a)
S = 1, R = 0
b) S = 0, R = 1
c)
S = 1, R = 1
d) S = 0, R = 0
10) For a gated D latch, the Q output always equals the D input
a)
before the enable pulse
b) during the enable pulse
c)
immediately after the enable pulse
d) answers (b) and (c)
11) Like the latch, the flip-flop belongs to a category of logic circuits known as
a)
monostable multivibrators
b) bistable multivibrators
c)
astable multivibrators
d) one-shots
12) The purpose of the clock input to a flip-flop is to
a)
clear the device
b) set the device
c)
always cause the output to change states
d) cause the outputs to change states depending on the controlling (S-R, J-K, or D) inputs
13) For an edge-triggered D flip-flop,
a)
a change in the state of the flip-flop can occur only at a clock pulse edge
b) the state that the flip-flop goes to depends on the D input
c)
the output follows the input at each clock pulse
d) all of these answers
14) A feature that distinguishes the J-K flip-flop from the S-R flip-flop is the
a) toggle condition
7
b) preset input
c)
type of clock
d) clear input
15) A J-K flip-flop is in the toggle condition when
a)
J = 1, K = 0
b) J = 1, K = 1
c)
J = 0, K = 0
d) J = 0, K = 1
16) Asynchronous counters are known as
a) ripple counters
b) multiple clock counters
c)
decade counters
d) modulus counters
17) An asynchronous counter differs from a synchronous counter in
a)
the number of states in its sequence
b) the method of clocking
c)
the type of flip-flops used
d) the value of the modulus
18) A stage in a shift register consists of
a)
a latch
b) a flip-flop
c)
a byte of storage
d) four bits of storage
19) To serially shift a byte of data into a shift register, there must be
a)
one clock pulse
b) one load pulse
c)
eight clock pulses
d) one clock pulse for each 1 in the data
20) To parallel load a byte of data into a shift register with a synchronous load, there must be
a) one clock pulse
b) one clock pulse for each 1 in the data
c)
eight clock pulses
d) one clock pulse for each 0 in the data
21) The group of bits 10110101 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an
initial state of 11100100. After two clock pulses, the register contains
a)
01011110
8
b) 10110101
c)
01111001
d) 00101101
SECTION C
1) What are the full-adder inputs that will produce each of the following outputs:
T
B Cin
i.
SUM = 0, Cout = 0
0
0
0
ii.
SUM = 1, Cout = 0
1
0
0
iii.
SUM = 1, Cout = 1
1
1
1
iv.
SUM = 0, Cout = 1
1
1
0
2) Determine the outputs of a full-adder for each of the following inputs:
S Cout
i.
A = 1, B = 0, Cin = 0
1
0
ii.
A = 0, B = 0, Cin = 1
1
0
iii.
A = 0, B = 1, Cin = 1
0
1
iv.
A = 1, B = 1, Cin = 1
1
1
3) You wish to detect only the presence of the codes 1010, 1100, 0001, and 1011. An active-HIGH output is required to
indicate their presence. Develop the minimum decoding logic with a single output that will indicate when any one of
these codes is on the inputs. For any other code, the output must be LOW.
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
9
4) Using CircuitMaker, implement the decoding logic in question 3) above.
10
Exercise 1.3: Peripheral Devices
Overview
For this tutorial, you need to conduct some research on any three peripheral devices. The research should result in you
preparing a page of information (at least 200 words + diagrams) about the peripheral, its historical development, its
use and the technologies it employs.
HP SimpleSave Portable External Hard Drive
Hard drives have been developing over the last fifty years and they have been shrinking in size and growing in
capacity according to Moore’s Law. They are salient for today’s digital revolution and also cloud technology
infrastructure, as thousands of them form countless data servers around the world.
External hard drives have been around in the consumer technology sector for around a decade, being larger and
bulkier than USB memory sticks although still lighter than regular use in-computer hard drives (with the exception of
SSDs).
HP’s product is a 2.5” storage device with two capacity options: 320GB and 500GB. It is bus-powered and utilizes the
USB 2.0 technology. It was first made available in early 2009 starting at $120.
It features HP’s branded Simple Save software, which allows the device to connect seamlessly to the main device. The
biggest advantage for this family of external hard drives is size and weight: the HP device only measures 0.63 inches
in thickness while weighing only 5.93 ounces. The product’s possible main use is to backup data from the main hard
drive, as it is more portable than a computing unit, and less prone to damage due to its lower usage.
http://www.pcworld.com/product/297742/320-gb-external-hard-drive-retail.html
http://www.engadget.com/products/hp/simplesave/portable-hard-drive/
http://www.cnet.com/uk/news/hp-simplesave-backup-solution-for-dummies/
11
Logitech Z-5500 THX Certified 5.1 Speaker System
Speakers have been around in the actual form since the 1920s. The standard dynamic loudspeaker uses a magnetic
field to move either a coil or a magnet which is connected to a diaphragm. Today, almost everywhere we are, there is
some sort of speaker system near us, be it a smartphone speaker or a concert full set. Main attributes that are sought in
the market are the RMS watts and the nominal impedance, which represents the audio sensitivity of the speakers.
Logitech’s 5.1 system is a high-end product, with many features that appeal to audiophiles and audio professionals. It
boasts 505 watts, it is THX certified and it has several processing modes. It is highly durable and even if was launched
a good number of years ago, it still represents a benchmark when judged by audio quality.
The speaker system is intended to be the best all-round performer as a PC speaker system, as the wireless remote
control and the Pulse Code Modulator 96/24 decoder easily blend with computing technology. All these advantages
come at a steep price. Noticeable performance cons for the product are the fact that the subwoofer could have a tighter
sound and some construction details need to be overlooked.
http://www.edisontechcenter.org/speakers.html
http://lifehacker.com/five-best-5-1-surround-speaker-sets-1499066014/1501392334
http://www.engadget.com/products/logitech/z-5500/
http://www.tomshardware.co.uk/logitech-z,review-1130.html
12
http://www.cnet.com/uk/products/logitech-z-5500-digital-speaker-system-for-pc-9701150403/
http://www.digitaltrends.com/pc-speaker-reviews/logitech-z-5500-review/
Apogee GiO Guitar Interface
Guitar Interfaces are increasingly popular as MIDI technology reached mainstream and musically-trained individuals
are looking to expand their sonic vocabulary and creativity.
Ever since the first synthesizers, this kind of devices have been on the forefront of innovation on the international
music scene, especially in house and disco music.
The product is a standalone quality Analog to Digital and Digital to Analog converter and its main use is in studios.
Apogee focused on aligning with Apple in terms of interface line, maintaining a partnership with them. This guitar
interface is aimed to bring together the guitarist and the Mac user with a guitar-tailored experience.
In terms of size, the GiO is 7 x 18 x 2.5 inches and weighs approximately 9lbs. The unit is sturdy , being built on a
metal floor pedal. As software, it can operate with any Mac DAW; it sends standard MIDI Control Change messages
and is recognized by Mac OS X in either 44.1 kHz or 48 kHz.
GiO is a niche product, being dedicated to a narrow slice of people that seek to have the best experience from a Mac
product and their instruments. It blends well in the technology wave in sound engineering and it leaves the artist in its
creative flow in best way possible.
13
https://www.recordingmag.com/productreviews/2010/01/35.html
http://store.apple.com/us/reviews/TX346ZM/A/apogee-gio-guitar-interface
http://www.soundonsound.com/sos/jun10/articles/apogeegio.htm
http://www.musicradar.com/reviews/guitars/apogee-gio-263339
http://www.premierguitar.com/articles/Apogee_GiO_USB_Guitar_Interface_Controller_Review
14
Exercise 1.4: Assembly Language
Here is a sample program in assembler with comments to show how it works.
ORG
$1000
: set initial starting point of program to 1000(hex)
LDA NUMB1
: load AccA with value at location NUMB1 (direct
SUBA #%00110000
: turn ASCII digit into numeric value (immediate :address)
LDB NUMB2
: load AccB with value at location NUMB2 (direct
SUBB #%00110000
: turn ASCII digit into numeric value (immediate :address)
ADAB
: add together accumulators and put value in A
ADDA #%00110000
: turn numeric value into ASCII digit (immediate :address)
STA ANSWER
: place answer in memory at address ANSWER
SWI
: cause an interrupt which returns control to the OS
NUMB1
FCB ‘2’
: plant the ASCII code for ‘2’ at a location NUMB1
NUMB2
FCB ‘3’
: plant the ASCII code for ‘3’ at a location NUMB2
ANSWER
RMB 1
: reserve a memory byte called ANSWER
END
: informs assembler that this is the end of the code
1.
:address)
:address)
What does the following program do? Add comments to show what it is doing and (in some cases) why. You will find the
attached chart (page 4) helpful to write your comments. What exactly ends up in SORTED? As a clue, the 7-bit ASCII table
is printed here (page 3); look at the relationship between upper and lower case letters.
ORG $1000
LDA CHAR1
15
ADDA #%00100000
BGE LABEL1
SUBA #%00100000
LABEL1
LDB CHAR2
ADDB #%00100000
BGE LABEL2
SUBB #%00100000
LABEL2
STB TEMP
SUBA TEMP
BMI LABEL3
LDA CHAR2
BRA FINISH
LABEL3
LDA CHAR1
FINISH
STA SORTED
SWI
CHAR1
FCB ‘d’
CHAR2
FCB ‘E’
TEMP
RMB 1
SORTED
RMB 1
END
2.
If you could introduce the instruction:-
ORA - ‘or’ the contents of accumulator A with the value specified
you could make the program much simpler. How?
16
Label
Opcode
Operand
Comments
1
ORG
$1000
Set the initial starting point of the program to 1000(hex)
2
LDA
CHAR1
Load ACCA with value at location CHAR1
3
ADDA
#%00100000
Turn ASCII digit into a numerical value
4
BGE
LABEL1
Branch if previous value of LABEL1 is not negative
5
SUBA
#%00100000
Turn ASCII digit into numerical value
LDB
CHAR2
Replace the value in address LABEL1 in ACCB with CHAR2
7
ADDB
#%00100000
Turn ASCII digit into numerical value
8
BGE
LABEL2
Branch if previous value of LABEL2 is not negative
9
SUBB
#%00100000
Turn ASCII digit into numerical value
STB
TEMP
Place the value from ACCB in TEMP’s memory address
11
SUBA
TEMP
Subtract the value in ACCA and place it in TEMP
12
BMI
LABEL3
Branch if the value of LABEL3 is negative
13
LDA
CHAR2
Load the value of CHAR2 in ACCA
14
BRA
FINISH
Always finish at FINISH
6
10
LABEL1
LABEL2
15
LABEL3
LDA
CHAR1
Load the value of CHAR1 into address LABEL3
16
FINISH
STA
SORTED
Store the value from address FINISH in address SORTED
17
SWI
Cause an interrupt which returns control to the OS
18
CHAR1
FCB
‘d’
Put the ASCII code for ‘d’ at CHAR1
19
CHAR2
FCB
‘E’
Put the ASCII code for ‘E’ at CHAR2
20
TEMP
RMB
1
Reserve a byte of memory called TEMP
21
SORTED
RMB
1
Reserve a byte of memory called SORTED
22
END
Tell the processor that the program has ended
17
Exercise 2.1: Data Representation
5) Determine the 1’s complement of each of the following binary numbers:
a.
11011100 - 00100011
b.
01101001 - 10010110
c.
01010010 - 10101101
6) Determine the 2’s complement of each of the following binary numbers:
a.
00111010 – 11000101 - 11000110
b.
10110011 – 01001100 - 01001101
c.
01101100 – 10010011 - 10010100
7) Express each of the following decimal numbers as an 8-bit number in the 1’s complement form:
a.
-34 – 100010 – 00100010 - 11011101
b.
+103 – 1100111 – 01100111 - 00011000
c.
-99 – 1100011 – 01100011 - 10011100
8) Express each of the following decimal numbers as an 8-bit number in the 2’s complement form:
a.
-68 – 1000100 – 01000100 – 10111011 – 10111100
b.
+101 – 1100101 – 01100101 – 00011010 - 00011011
c.
-109 – 1101101 – 01101101 – 10010010 – 10010011
9) Determine the decimal value of each of the following signed binary numbers in the 1’s complement form:
a.
00010011 – 01101100 – 64 +32 + 8 + 4 = +108
b.
10100010 – 11011101 – 64 + 16 +8 +4 + 1 = -93
c.
11001001 – 10110110 – 32+ 16+4+2 = -54
10) Determine the decimal value of each of the following signed binary numbers in the 2’s complement form:
a.
00111001 – 00111000 – 01000111 – 64+4+2+1 = 71
b.
11010011 – 11010010 – 10101101 – 32 + 8 +4 +1 = -45
c.
11001001 – 11001000 – 10110111 – 32 + 16 + 4 + 2 +1 = -55
18
Exercise 2.2: Introduction to Logic Circuit Design
SECTION A
1.
Identify the following gates:-
Top left gate is an AND gate, top right gate is a NAND gate.
Center left gate is an OR gate, center right gate is a XOR gate.
Bottom left gate is an inverter, bottom right is a NOR gate.
2.
Using CircuitMaker, find the relevant gates in the library and place them on the grid with switch inputs and display
outputs. Simulate them one-by-one and draw the Truth Tables which describe them.
A
B
C
A
B
C
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
A
1
B
1
C
1
1
0
A
B
C
0
0
0
0
0
0
0
1
1
0
1
1
1
1
A
0
B
1
C
1
1
0
1
0
0
1
0
1
0
1
0
0
1
1
0
1
1
A
0
1
0
1
B
1
0
19
3.
Using CircuitMaker, construct and simulate the following circuits, and fill-in the truth tables for them. Indicate which
gate could be used to replace each circuit.
A
B
C
D
E
F
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
1
1
0
0
0
1
J
K
L
M
N
P
0
0
1
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
1
0
0
0
1
It could be replaced with an OR gate.
It could be replaced with an AND gate.
SECTION B
1) An AND gate can have only two inputs. (False)
2) If any input to an OR gate is 1, the output is 1. (True)
3) If all inputs to an AND gate are 1, the output is 0. (False)
20
4) When the input to an inverter is HIGH (1), the output is
(a) HIGH or 1
(b) LOW or 1
(c) HIGH or 0
(d) LOW or 0
5) An inverter performs an operation known as
(a) Complementation
(b) Assertion
(c) Inversion
(d) Both answers (a) and (c)
6) The output of an AND gate with inputs A, B, and C is a 1 (HIGH) when
(a) A = 1, B = 1, C = 1
(b) A = 1, B = 0, C = 1
(c) A = 0, B = 0, C = 0
7) The output of an OR gate with inputs A, B, and C is a 1 (HIGH) when
(a) A = 1, B = 1, C = 1
(b) A = 0, B = 0, C = 1
(c) A = 0, B = 0, C = 0
(d) Answers (a), (b), and (c)
(e) Only answers (a) and (b)
21
Exercise 2.3: More Logic Gates and Logic Circuit Design
SECTION A
1.
Using CircuitMaker, show how you could build a 2-input OR gate using only 2-input NAND gates. (There is a clue in
one of the solutions for Exercise 6).
2.
An ‘optional inverter’ has two inputs one called ‘INV(ert)’ and one called ‘D(ata)’. It has one output called
‘O(ut)’. If INV is 0 then O is the same as D. If INV is 1 then O is the inverse of D (i.e. not D). Draw a truth
table and design a circuit which does this. Simulate this circuit on CircuitMaker. Caution – it is much easier
than it looks!
3.
For each of the following truth tables:
a) Derive a standard Boolean expression (Sum-of-Products)
b) Simplify the expressions using Boolean algebra rules or Karnaugh maps
c) Implement the simplified expressions on Circuitmaker
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
X
0
1
0
0
1
1
0
1
notA* notB* C + A * notB * notC + A * notB * C + A* B * C
A
0
0
B
0
0
C
0
1
X
0
0
22
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
0
0
1
1
1
A * notB * C + A * B * notC + A * B * C
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
1
1
0
1
0
1
1
0
0
1
0
0
1
0
0
0
notA * notB * notC * notD + notA * notB * notC * D + notA * notB * C * D + notA * B * notC * D + notA * B * C *
notD + A * notB * notC * D + A * B * notC * notD
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
0
1
0
1
1
0
1
0
0
0
1
1
0
0
1
notA * notB * C * notD + notA * B * notC * notD + notA * B * notC * D + notA * B * C * D + A * notB * C * D +
A * B * notC * notD + A * B * C * D
23
SECTION B
8) A NAND gate has an output that is opposite the output of an AND gate. (True)
9) A NOR gate can be considered as an OR gate followed by an inverter. (True)
10) The output of an exclusive-OR is 0 if the inputs are opposite. (True)
24
Exercise 2.4: Computer Function and Interconnection
SECTION A
25) The buses that connect different parts of the processor can be hierarchical to improve the performance. (True)
26) Instead of hard-wiring the units, software is used to interpret and execute instructions in a general purpose system.
(True)
27) The program counter stores the address of the next instruction to be executed. (True)
28) The fetched instructions are stored in the Accumulator register. (True)
29) Interrupts are parts of the program that can cause the processor to stop. (True)
30) All interrupts are handled by the interrupt handler. (True)
31) Multiple interrupts cannot be handled by the processor. (True)
32) I/O modules can have direct access to the memory. (True)
33) If a module needs to transmit data, the data is sent through the buses immediately. (False)
34) Data transfer between modules/units cannot be controlled. (False)
35) The PCI bus is used for high speed I/O transfers. (True)
36) Interrupt request is a PCI command. (True)
SECTION B
22) How are data and instructions stored in the Von Neumann architecture?
e)
Unified read-write memory
f)
In separate memories
g) Dual ported memory
h) None of the above
23) Which of these are the main stages of an instruction cycle?
e)
Fetch, decode and exclude cycles
f)
Fetch and Execute Cycle
g) Decode and Store cycle
h) Fetch, encode, execute and store
24) Where is the fetched instruction stored?
e)
Program Counter
f)
Instruction buffer register
g) Instruction register
h) None of the above
25) Which of the following is a type of interrupt?
e)
Program Interrupt
25
f)
Hardware/power failure
g) I/O interrupt
h) All of the above
26) Which of the following approaches is used to handle multiple interrupts?
e)
Interrupt wait
f)
Parallel interrupt processing
g) Disable interrupts and priority assignment
h) None of the above
27) Which of these interconnection wires is not in the bus structure?
e)
Address lines
f)
Data lines
g) Control lines
h) Instruction lines
28) Which of the following is a bus arbitration scheme?
a)
Priority
b) Round-robin
c)
First come first serve
d) All of the above
26
Exercise 2.5: Memory
SECTION A
37) The memory devices used in a computer form a hierarchy based on a set of characteristics. (True)
38) The lowest level of memory in the hierarchy is the closest to the processor. (False)
39) Semiconductor ROM memory is a non-erasable but volatile type of memory. (False)
40) If the memory has faster access time, then the cost per bit is less. (False)
41) A hit occurs when the word requested can be accessed from the lowest memory in the hierarchy. (False)
42) Data stored in secondary or auxiliary memory is represented in terms of files or records. (True)
43) Direct mapping implies that the number of lines in the cache must be equal to the main memory. (False)
44) The best among the three cache replacement algorithms is the least recently used (LRU) algorithm. (True)
45) Like the entire memory, the system can have multi-level caches. (True)
46) Static RAM is a faster and denser memory than DRAM. (False)
47) The capability of being written into a stable state is one important property of semiconductor memories. (True)
48) DRAM uses set of transistors to store charge. (False)
49) ROMs cannot be used even when only few bits are corrupted. (True)
50) EPROMs and Flash memory use only a single transistor to store information in each cell. (False)
51) Read-mostly memory is a type of random-access memory. (False)
SECTION B
29) How are data stored in the internal memory??
i)
Bytes
j)
Pages
k) Words
l)
Bytes or Words
30) Which among the following is not as method of accessing data?
i)
Sequential
j)
Asynchronous
k) Random
l)
None of the above
31) The unit of transfer between the levels of memory is defined by
i)
Type of memory access
j)
Distance between memory and processor
k) Number of electric lines in and out of memory
l)
All of the above
27
32) Performance of the memory is decided by which of the following parameters
i)
Transfer rate
j)
Latency
k) Cycle time
l)
All of the above
33) Victim caching helps what type of cache architecture?
i)
Fully-associative
j)
Set-Associative
k) Direct mapped
l)
None of the above
34) Random cache line replacement policy performs close to which other policy?
i)
LRU
j)
LFU
k) FIFO
l)
All of the above
35) Split caches indicate separate
e)
L1 and L2 cache
f)
L2 and L3 cache
g) Data and Instruction cache
h) None of the above
36) Prefetching can be done only in what type of cache
a)
Fully-associative
b) Direct mapped
c)
Unified cache
d) Split-cache
37) As you go down the hierarchy,
a)
Latency increases
b) Cost per bit reduces
c)
Capacity increases
d) All of the above
38) An important attribute of RAM memories is
a)
Random access & non-volatile
28
b) Volatile
c)
Sequential access
d) None of the above
39) Important difference between SRAM and DRAM
a) Static/Dynamic & no refresh for SRAM
b) Static/Dynamic & no refresh for DRAM
c)
no refresh for DRAM
d) None of the above
40) In a DRAM, depending on what is the cell value decided as 1 or 0.
a)
Max capacitor charge
b) Transistor threshold voltage
c)
DC voltage high
d) Input voltage
41) How long does a static SAM hold data?
a)
Eternally
b) For as long as power is supplied
c)
Only during manufacturing
d) None of the above
42) How often/how is data written into the ROM?
a)
Anytime/when required
b) Before use – by microprogramming
c)
During manufacturing
d) All of the above
43) What happens when a bit of data is incorrect in a ROM?
a)
Error correction will be used
b) Redundancy will help
c)
ROM cannot be used
d) None of the above
44) From the following, which type of memory is not a read-mostly memory?
a)
EEPROM
b) PROM
c)
Flash
d) EPROM
29
Exercise 2.6: Processors and Amdahl’s Law
SECTION A
52) Registers MAR and MBR can be accessed by the user. (True/False)
53) RISC architecture has a very simple instruction set. (True/False)
54) The compilers are very simple in a CISC architecture. (True/False)
55) CISC's reduction in the number of instructions for a program, shows a drastic improvement in execution time as
compared to RISC. (True/False)
56) CISC does not combine load/store with an arithmetic operation. (True/False)
SECTION B
45) The type of addressing mode and operand information is obtained in which part of the instruction cycle?
m) Fetch
n) Execute
o) Issue
p) Decode
46) The CPU system bus involves transfer of
m) Control
n) Data
o) Instructions
p) Both a) and b)
47) These registers are set during the execution of an instruction
m) Data registers
n) Address registers
o) Condition Code
p) Control
48) The operating system executes certain privileged instructions by setting the
m) Status register
n) Privileged register
o) Stack pointer
30
p) Supervisor bit
49) The speedup of a processor is estimated using which of the following parameters
m) Throughput
n) Cycles per instruction in one and N processors
o) Execution time in one and N processors
p) None of the above
50) Storage space that has the fastest access time
m) Cache
n) Hard drive
o) Main memory
p) Registers
51) The instruction set of a CISC architecture is
i)
Very simple
j)
Similar to RISC
k) Highly complex
l)
None of the above
52) The number of instruction types available in the CISC architecture makes the program
e)
Smaller
f)
Longer
g) Does not change
h) None of the above
53) Compared the CISC, RISC architecture has
e)
Simpler opcode
f)
Fewer load/store
g) Simple addressing modes
h) All of the above
54) RISC architecture puts an emphasis on optimizing the
e)
Memory
f)
Compiler
g) System bus
h) None of the above
31
SECTION C
Given that 90% of a program can be run in parallel, use a spread sheet, and Amdahl’s Law, to calculate Speedup in the following
parallel cases and complete the following table.
Percentage that can be made parallel optimised
Number of Processors
Speedupenhanced
90
4
3.07
90
6
4
90
8
4.7
90
10
5.26
90
12
5.71
90
14
6.08
90
16
6.4
90
18
6.(6)
90
20
6.89
90
22
7.09
90
24
7.27
90
26
7.42
90
28
7.56
90
30
7.69
90
32
7.8
What do you notice about the resulting graph?
There is a healthy increase in the start when there is a single-digit number of Processors. But as the number approaches
32, there are diminishing returns, even if 90% of the code parallelized. It is all about the slope of the increase in
performance.
32
Exercise 2.7: Machine Sequence and Micro-operations
LDA #54
Load the accumulator with the number 54.
Instruction fetch
PC → MAR
send a copy of PC contents to MAR
(increment PC)
PC has 1 added to it so it points to the next instruction
MAR → store
the address of the instruction is sent to the store for a read to occur
store → MDR
the instruction is fetched from store and placed in the MDR
Decode
MDR → IR
instruction is moved to instruction register
(decode)
decoding of opcode occurs
Operand fetch
nothing to do here, data (54) is part of immediate mode instruction.
Execute
no data transformations to do
Write
IRADDR → Acc
a simple write to a register
Change are in red
1. If the instruction was modified to LDA 54 (load the accumulator with the number at address 54 in store, i.e. direct mode) what
changes would be necessary in the RTL?
Instruction fetch
PC → MAR
send a copy of PC contents to MAR
(increment PC)
PC has 1 added to it so it points to the next instruction
MAR → store
the address of the instruction is sent to the store for a read to occur
store → MDR
the instruction is fetched from store and placed in the MDR
Decode
MDR → IR
instruction is moved to instruction register
(decode)
decoding of opcode occurs
Operand fetch
IRADDR → MAR
send the address of operand to MAR
MAR → store
the address of the operand is sent to the store for a read to occur
store → MDR
the operand is fetched from store and placed in the MDR
Execute
no data transformations to do
33
Write
MDR → Acc
a simple write to accumulator
2. Now if the instruction was LDA [54] (load the accumulator with the number whose address can be found at location 54 in the
store, i.e. indirect mode) what further changes are necessary?
Instruction fetch
PC → MAR
send a copy of PC contents to MAR
(increment PC)
PC has 1 added to it so it points to the next instruction
MAR → store
the address of the instruction is sent to the store for a read to occur
store → MDR
the instruction is fetched from store and placed in the MDR
Decode
MDR → IR
instruction is moved to instruction register
(decode)
decoding of opcode occurs
Operand fetch
IRADDR → MAR
send the address of operand to MAR
MAR → store
the address of the operand is sent to the store for a read to occur
store → MDR
the operand is fetched from store and placed in the MDR
MDR  MAR
send address of operand to MAR
MAR  store
the address of operand is sent to store for a read to happen
store  MDR
the operand is fetched from store and placed in the MDR
Execute
no data transformations to do
Write
MDR → Acc
a simple write to accumulator
3. Finally, if the instruction was ADD [54] (add to the accumulator the number whose address can be found at location 54 in the
store, i.e. indirect mode) what other changes are necessary?
Instruction fetch
PC → MAR
send a copy of PC contents to MAR
(increment PC)
PC has 1 added to it so it points to the next instruction
MAR → store
the address of the instruction is sent to the store for a read to occur
store → MDR
the instruction is fetched from store and placed in the MDR
Decode
MDR → IR
instruction is moved to instruction register
34
(decode)
decoding of opcode occurs
Operand fetch
IRADDR → MAR
send the address of operand to MAR
MAR → store
the address of the operand is sent to the store for a read to occur
store → MDR
the operand is fetched from store and placed in the MDR
MDR  MAR
send address of operand to MAR
MAR  store
the address of operand is sent to store for a read to happen
store  MDR
the operand is fetched from store and placed in the MDR
Execute
MDR  IB
put the data in ALU’s input buffer
Acc  ALU
(via bus) plus IB  OB what is saved in Acc is take via bus to other ALU input, an add takes place
in the ALU and result is stored in OB
Write
OB → Acc
a simple write to accumulator
35
Exercise 2.8: Practice for Phase Test 3
SECTION A
1) One of the most important functions of the Operating System is scheduling processes/tasks. (True)
2) Multi-tasking involves the process of switching between different programs while holding them in an expanded memory.
(True)
3) Paging helps in reducing the number of holes in the memory. (True)
4) Demand paging brings all the pages required for the program into the main memory. (True)
5) Virtual memory uses demand paging to create the appearance of a larger memory that that present in hardware. (True)
6) The end user has complete access to the Operating System. (False)
7) The interrupt handler is a part of the computer hardware. (False)
8) The programmer can have access to privileged instructions in the Operating System. (True)
9) The OS also keeps track of processor and clock time used. (True)
10) Any external I/O connected to the computer is termed as a virtual I/O. (False)
11) Processor, main memory and the I/O cannot share the same system bus. (False)
12) DMA is the best type of I/O technique for large transfers. (True)
13) Parallelism in computers is exploited to increase performance of the system. (True)
14) In a multiprocessor architecture, the memory is usually divided between the processing units. (True)
15) Cache coherency is a common issue when using multiple levels of memory. (True)
16) A process and thread switch incur the same amount of time/cost. (False)
17) NUMA and cluster architectures have shared memories that are similar in configuration. (False)
18) All parts of the memory have the same access time in UMA. (True)
19) Multicore means that there are multiple similar cores on the same chip. (True)
20) Blocks of data brought into the shared cache by one processor in a multi-core chip cannot be used by any other
processor. (False)
SECTION B
55) Which of the following is not a function of the OS?
q) Program Execution
r)
Error correction
s)
Data/Instruction Access
t)
All of these options
56) Which part of the OS stores utilities or frequently accessed functions?
q) Memory
r)
Kernel
s)
Registers
t)
None of these options
36
57) This type of scheduling decides which process is run by the processor at any given time
q) Long-term
r)
Medium term
s)
Short-term
t)
All of these options
58) Holes left in the memory by variable size partitioning can be resolved by
q) Swapping
r)
Segmentation
s)
Virtualization
t)
Compaction
59) With paging (Memory management), the physical address is obtained by the processor using
q) Scheduler
r)
Program Counter
s)
Page table
t)
None of these options
60) When a page fault occurs, what process is implemented?
q) Page Overwrite
r)
Page Replacement
s)
Program switch
t)
All of these options
61) The page table is used to convert _______ into physical address.
m) Logical address
n) Frame number
o) Page number
p) None of these options
62) Swapping involves the process of incorporating processes in the
i)
Short-term queue
j)
I/O queue
k) Intermediate queue
l)
None of these options
63) Which of the following is a duty of a modern operating system?
i)
Memory Manager
j)
Process Manager
37
k) Device manager
l)
All of these options
64) Which of the following is NOT a type of OS scheduling?
i)
Long-term
j)
Fixed-term
k) Input/Output
l)
None of these options
65) What converts data signals from electrical to other forms of energy in an I/O device?
e)
Convertor
f)
Transformer
g) Transducer
h) Arbiter
66) Which of the following is an example of a communication I/O?
e)
Monitor
f)
Modem
g) Mouse
h) USB
67) Which of the following are types of I/O commands?
e)
Read
f)
Control
g) Test
h) All of these options
68) This I/O technique does not involve the processor during data transfer
e)
Direct Memory access
f)
Programmed I/O
g) Memory-mapped I/O
h) All of these options
69) In an Interrupt-driven I/O, when an interrupt is detected, details of the current processor condition are stored in
e)
Return address register
f)
Program counter
g) Program status word
h) Memory bank
38
70) SMP and NUMA are examples of
e)
SIMD
f)
MIMD
g) MISD
h) SISD
71) These require multiple control units to operate
a)
SIMD
b) NUMA
c)
SISD
d) None of these options
72) This takes care of scheduling and synchronisation between multiple processors
a)
Control unit
b) Hardwired control
c)
Operating System
d) All of these options
73) An important advantage of a clustered system is
a)
Parallelism
b) High availability
c)
Coherency
d) Fault tolerance
74) The function of switching a failed process to another node in a cluster is called
a)
Failure rate
b) Failover
c)
Failpush
d) None of these options
75) NUMA has the advantage over SMP in
a)
Cycle time
b) Performance and Parallelism
c)
Power
d) None of these options
76) If two (or more) identical processors on the same chip are used to execute different threads of the same process, it is
called
a) Multi-processing
39
b) Multi-programming
c)
SMP
d) Multi-core
77) Which of the following is a benefit of clusters?
a)
Incremental Scalability
b) Superior price/Performance
c)
Absolute Scalability
d) All of these options
78) Speedup is the fraction of speed gain for one processor to
a)
Memory banks
b) N processors
c)
Cache
d) N register banks
40
Reflective Report
I chose Phase Test 3 Exercises as the tutorial challenged me to learn efficiently and improve my memory on key concepts, aided
by lab materials. It covered more material than the others and I am thankful for this, as I aimed every time to learn as efficient as I
can, while pursuing my interests and my obligations. It also served as a stepping stone into preparing myself for the exam.
Peripheral Devices is a clever way to gain commercial awareness of what is right now on the market in regards to consumer
technology. My choices of devices reflected my interests, namely portable storage for books, music and video, sound systems and
guitar interfaces because of my passion for music.
Overall, I learned from the coursework that to master anything, there have to be hours put in. And you have to think, reflect and
make courageous mistakes in order to be less wrong than you were in the first place. I believe in focusing on one’s strengths,
while keeping in check one’s weaknesses. That is why my entire portfolio is related to what I had background knowledge.
Lastly, I praise the class structure and its topics, as they covered a lot of material which I did not have the opportunity to learn in
university in Romania. Relevance is key and I really appreciate it. The only thing I would change is the focus on students. There
were people that really had not even a basic idea of what is going on and I committed myself to alleviate this as much as I could.
41