Constraint Analysis for Minimization of Multiple Inputs Logic Programming Sahadev Roy, Chandan Tilak Bhunia Department of ECE NIT, Arunachal Pradesh Yupia, Itanagar, India sdr.ece@nitap.in Available at: http://www.elsevierst.com/conference_book_download_chapter.php?id=4436&file=9789351072676_ICSSP_11.pdf Abstract— Minimization of logic functions by computer programs is considered traditionally to be tuff and tedious as the incorporation of full logic negation tends to superexponential time complexity. The paper presents constrains for minimization of logic circuits. Using these analysis minimized sum of products terms may be generating from any given sum of product terms of multiple input variables. For new algorithm for minimization using computer programming must be overcome these problem. We also discuss the scope heuristic minimization technique over the exact minimization technique. Keywords- Algorithm, Minterms, Minimization, Logic Boolean function, SOP, Weighted sum, Complexity, Constraint. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] Sahadev Roy and Chandan Tilak Bhunia “ Minterms Generations Algorithm Using Weighted Sum Method” International Journal on Current Science & Technology, Vol.-1 No.-2 , ISSN : 2320 5636, pp 34-38 July-Dec 2013. Sahadev Roy and C. T. Bhunia “Minimization algorithm for multiple input to two input variables ” in IEEE international Conference on Control, Instrumentation Energy and Communication, (CIEC14), Jan 2014. C.R. Nayak and C.T. Bhunia, “Program to assist in computer hardware design,” in Electronic for You, pp 70-71, Jan. 1990. C.R. Nayak and C.T. Bhunia, “Application software to design multiple I/O digital system,” in Electronic for You, pp. 70-75, Oct. 1990. C.R. Nayak and C.T. Bhunia, “Development and Design of Software for Combinational/Sequential Logic Systems,” in IEEE Tencon Vol 75, pp. 37-39, Nov. 1994. C. T. Bhunia, “Engineering tricks in minimzation of combinational logic for c3 system design,” in IEEE Region 10 International Conference on EC3-Energy, Computer, Communication and Control Systems , vol.3, pp. 171-174, Aug. 1991. Mehmet Dincbas, Helmut Simonis and Pascal Van Hentenryck, Solving large combinatorial problems in logic programming,” in J. of Logic Programming, Volume 8, No1–2, pp 75-93 Jan.–Mar. 1990. Divya Nasa and Udayan Ghose, “C – Minimizer Algorithm: A New Technique for Data Minimization,” in I. J. of Computer Applications, ISSN : 0975 – 8887, Volume 44– No17, pp 15-19 April 2012. K. Somasundaram “Multi-level Sequential Circuit Partitioning for Delay Minimization of VLSI Circuits”, in J. of Information and Computing Science Vol. 2, No. 1, pp. 66-70, 2007. [10] Jr. E. J. McCluskey, , “Minimization of Boolean functions,” Bell System Technical Journal, vol. 35, pp. 1417-1444, November, 1956. [11] D. H. Green, “Families of Reed-Muller canonical forms,” Int. J. Electron. (UK), vol.70, no.2, 259-280, Feb. 1991. [12] R. Drechsler and B. Becker, “Sympathy: Fast Exact Minimization of Fixed Polarity Reed-Muller Expressions for Symmetric Functions.” IEEE Trans. CAD, Vol. 16, No 1, pp. 1-5, Jan. 1997. [13] T. Kozlowski, E. L. Dagless, J. M. Saul. “An enhanced algorithm for the minimization of exclusive-OR sum of products for incompletely specified functions”. Proc. of ICCD’95, pp. 244-249,1995. [14] Z.Zilic and Z.G.Vranesic, “A multiple-valued Reed-Muller transform for incompletely specified functions,” Computers, IEEE Transactions on , vol.44, no.8, pp.1012-1020, Aug 1995. [15] K.M. Dill and M.A. Perkowski, “Baldwinian learning utilizing genetic and heuristic algorithms for logic synthesis and minimization of incompletely specified data with Generalized Reed–Muller (AND– EXOR) forms,” J. of Systems Architecture, Vol. 47, no. 6, pp 477-489, June 2001.