GBT Bandgap Review and (slight) Buffer Amp Revision
lijianf@seas.upenn.edu
Block level schematic of bandgap and buffer amp.
The bandgap contains 2 part: one bandgap circuit and one output buffer amp.
2. Detailed look of bandgap circuit
The bandgap circuit is a typical low-voltage CMOS bandgap circuit with a PMOS version bandgap.
Annotations in yellow show our findings with the schematic and extracted layout.
The programmable resistors are ordered according to thermometric code. In schematic based
simulations they provide a voltage drop across a band cap determined constant current in the range
of554mV to 796mV with 15mV intervals.
Problem we have now:
Interchanging the schematic and layout extracted bandgap circuit shows a different output voltage
range between 968mV to 1373mV with a 26mV interval. Indicating that the bandgap has large constant
current source.
Transient analysis showing the difference between extracted view and schematic with programmable
resistor = 0xFFFF, 0C, TT process.
Extracted view
schematic view
As shown in the plot the output of the bandgap is 969mV when using the extracted netlist which differs
significantly from 555mV simulated with the same test bench using the schematic netlist. INP and INM
are the two inputs to the amp in the feedback loop.
The value of the bandgap determined constant current for the extracted netlist is 17uA compared to
10uA for the schematic. Checking further the output of the feedback opamp is at a lower voltage. 1.14
vs 1.21 for the schematic view resulting in the higher current. Both inputs to the opamp suffer from
the same 10mV input mismatch for reasons that are not clear. It could be a difference in the mismatch
between the output impedance of the PMOS and NMOS drains in the output of the bandgap opamp.
3. Detailed look of buffer amp.
The criss-cross output design of the buffer amp yields a very narrow range of high gain output drive.
For small deviations of the output voltage with respect to the correct voltage the output impedance is
1K ohm, but if the output voltage is more than a few hundred mV from the band gap input voltage as it
is during startup the impedance is quite high which keeps the opamp from being able to start up with a
load as high as 40Kohms. We slightly revised the output section of the circuit as indicated by the
annotations in yellow.
The plot below shows when ramping up the output current, the voltage falls as soon as current reaches
10uA originally and 40uA after the edits are applied.
Output current is up to only 10uA:
Trans analysis of buffer amp before edit.
After increase the bias current and double the current mirror, the output current is up to only 40uA:
Transient analysis of buffer amp output current after each edit and combined (orange).
Following figure shows the sweep of output current. as we can see, the edition of the circuit roughly
gives us 4 times larger output current.
DC analysis of sweeping output current.
AC analysis showing the stability of the circuit after insert a 0.1pF capacitance:
As of April 18 the problem of the disagreement between the schematic and extracted Netlists remains.