EEEE 381 – Electronics I
Lab #6: Frequency Response of CMOS Amplifier
Overview
The objective of this lab is to investigate the frequency response of a CMOS operational
amplifier (op-amp) through simulation and experimental measurement.
Theory
At low to moderate frequencies, the internal parasitic capacitances in a MOSFET are too small to
have a material impact on the frequency response of a circuit. Recall that the impedance of a
capacitor varies inversely with frequency and the magnitude of the capacitance. For small
capacitance values and low frequencies, then, the internal parasitic capacitances behave
essentially like open circuits and they are omitted from the small-signal MOSFET model.
At high frequency, however, the effect of the internal capacitances becomes significant, and the
small-signal MOSFET model must be augmented to include their effects. The MOSFET can be
represented at high frequency using the model shown in Figure 1.
D
Cgd
G
+
Cgs
ro
vgs
gm vgs
Cdb
gmb vbs
–
–
Csb
vbs
+
S
B
Figure 1. High-Frequency Small-Signal MOSFET Model
Electronics I – EEEE 381 — Lab #6: Frequency Response of CMOS Amplifier — Rev 5.1 (8/23/15) Page 1 of 11
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Gate-to-source capacitance Cgs and gate-to-drain capacitance Cgd are related to SPICE model
parameters CGSO and CGDO, respectively. The source-body capacitance Csb and drain-body
capacitance Cdb represent the capacitances of the reverse-biased pn junction formed between
each of the source/drain diffusions and the body, respectively. Recall that the small-signal
substrate (body) connection is always at small-signal ground since NMOS and PMOS substrates
are connected to the lowest and highest DC supply voltages, respectively.
This lab will investigate the frequency response of the two-stage CMOS op-amp that was
designed and tested in the previous lab. The two-stage amplifier is shown in Figure 2. Specific
values of R, RD7, and/or RD8 were determined as part of Lab #5.
CD4007
M3
+5 V
M4
VDD
5V
(DC)
M7
CDE4007
M1
4
R
IREF
10 
Rout
1 k 100 F
M2
RD7
+
vid
–
51 
vsig
1 kz
~
Rout8
100 F
vo
RL
20 k
RD8
VSS
5V
(DC)
Io
M5
Vcom
(DC)
RS = 200 
M6
CD4007
M8
–5V
Figure 2. Two-stage CMOS amplifier
Electronics I – EEEE 381 — Lab #6: Frequency Response of CMOS Amplifier — Rev 5.1 (8/23/15) Page 2 of 11
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Figure 3 shows representative magnitude (top) and phase (bottom) plots for this op-amp. It can
be seen from Figure 3 that at the point where the gain magnitude is unity, or 0 dB, there is a
phase shift of roughly –220, or a phase margin of –40 compared to a critical value of –180,
which is indicative of an unstable amplifier. The phase margin is generally required to be more
than +45. The requirement for stability can be stated as the following: the gain curve should
cross the 0 dB level before the phase curve reaches –180 (preferably –135 or –120, for phase
margins of 45 or 60, respectively). In its present form, this amplifier would be considered to
be unstable, although the instability problem can be easily fixed. Phase margin can be improved
by “compensation”, wherein the position of a pole is moved. Stability and compensation will be
studied in Electronics II.
Figure 3. Examples of magnitude and phase plots
Electronics I – EEEE 381 — Lab #6: Frequency Response of CMOS Amplifier — Rev 5.1 (8/23/15) Page 3 of 11
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Pre-Lab
(1) Use PSPICE to simulate the frequency response of the circuit. Obtain the magnitude
response, the phase response, the phase margin, and the unity-gain bandwidth.
a) See appendix on using SPICE model RIT4007N7 and RIT4007P7
b) Under Part properties set the following for NMOS, L=10u W=170u Ad=8500p
As=8500p Pd=440u Ps=440u NRD=0.1 NRS=0.1
c) Under Part properties set the following for PMOS, L=10u W=360u Ad=8500p As=8500p
Pd=440u Ps=440u NRD=0.1 NRS=0.1
d) Some hints for determining gain, unity-gain bandwidth (the frequency at which the gain
has dropped to unity, or 0 dB), and phase margin are given below:
Gain




For the gain, perform an AC sweep (use the VAC source).
Choose Logarithmic Sweep type, and under that choose Decade, with a frequency
range of 1–10G.
Use Points / Decade = 200.
Set the output variable to be the ratio of the output voltage to the differential
amplifier’s input voltage, vid, taken as the voltage across the 51  resistor in
Figure 2. The output voltage vo would be taken at the high side of the load resistor
RL in Figure 2. For example, taking the input as the gate of M2, the output variable
would be: <node at the top of RL>/M(2:g).
Unity-gain bandwidth

For the unity-gain bandwidth, observe the frequency where the gain is 0 dB.
(continued)
Electronics I – EEEE 381 — Lab #6: Frequency Response of CMOS Amplifier — Rev 5.1 (8/23/15) Page 4 of 11
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Phase Margin





A plot in degrees is needed → Add a trace.
From the Function of Macros column, choose Plot Template Window.
Choose Bode plot dB (separate from Function of Macros).
Remember that it is output/input that is being plotted, where the output node is
designated as vo at the high side of the load resistor RL in Figure 2. There is no need
to take the difference vs. the input phase since the input phase should be zero.
Now you will have two plots as shown in Figure 3. The critical phase is the angle
in the lower plot corresponding to unity gain bandwidth in the upper part. Then,
Phase Margin = 180 - Unity gain angle (in degrees).
(2) (Optional) If you would like to see the effect of compensation, try putting a modest amount
of capacitance — e.g., 20 nF — between the gate and drain of M7, then re-simulating to see
the effect on gain and phase. This compensation technique takes advantage of the Miller
effect to magnify the compensation capacitance to an effective level that is actually needed
for stabilization of the circuit.
Electronics I – EEEE 381 — Lab #6: Frequency Response of CMOS Amplifier — Rev 5.1 (8/23/15) Page 5 of 11
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Lab Exercise
(1) Measure the magnitude and phase at the output of the two-stage CMOS amplifier, varying
the frequency of the small-signal input (shown as 1 kHz in Figure 2). The frequency of vsig
should be varied from 1 kHz to a frequency that is sufficiently high to ensure that the
magnitude of the voltage gain drops to unity (0 dB) — i.e., until the output signal amplitude
is equal to the input signal amplitude. Most of the function generators go to up to 15 MHz.
(Don’t forget that the input is not 1 V in magnitude.)
The frequencies should be spaced roughly equally in the log-frequency domain — e.g., at
1 kHz, 10 kHz, 100 kHz, etc. Measurements should be made at a minimum of five
frequencies so as to allow the subsequent construction of representative magnitude and phase
plots like those shown in Figure 3.
Use a sinusoidal signal vsig from the signal generator of no more than 200 mV amplitude
(recall that there is substantial gain in the amplifier). Measure the peak-to-peak voltage
amplitudes of the input (vid) and output (vo) waveforms at each measurement frequency.
Note that the input to the differential amplifier vid is not the same as the signal source
vsig. Also, measure the phase difference between each pair of waveforms at each
measurement frequency. Calculate the gain magnitude for each of the frequencies using
v 
20 log 10  o  .
 vid 
(2) (Optional) If you would like to see the effect of compensation, try putting a modest amount
of capacitance — e.g., 20 nF — between the gate and drain of M7, then re-measuring to see
the effect on gain and phase. This compensation technique takes advantage of the Miller
effect (normally undesirable) to magnify the compensation capacitance to an effective level
that is actually needed for stabilization of the circuit.
Analysis of results
(1) Based on your measurements, construct Bode magnitude and phase plots like those shown in
Figure 3. Make sure the frequencies are spaced out in the log frequency domain. You may
need to determine where the graph crosses the 0 dB level by extrapolation if the frequency
generator does not go high enough in frequency.
(2) From your magnitude response plot, determine the upper 3-dB frequency, fH. Compare this
value to your value from pre-lab simulations. Also, determine the unity-gain frequency and
the phase margin of the amplifier.
(3) Determine the gain-bandwidth product of the amplifier.
Electronics I – EEEE 381 — Lab #6: Frequency Response of CMOS Amplifier — Rev 5.1 (8/23/15) Page 6 of 11
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Check-Off Sheet
A. Pre-Lab
 PSPICE simulation of the frequency response of the two-stage CMOS amplifier, resulting
in magnitude and phase response plots.
B. Experimental
 Two-stage CMOS amplifier built and debugged (may have been retained from Lab #5).
 Measurements of magnitude and phase taken at a minimum of five logarithmicallyspaced frequencies. Measurements must be taken at frequencies that are sufficiently high
to show the upper 3-dB frequency and the unity-gain frequency.
TA Signature: ____________________________ Date: ___________________________
Electronics I – EEEE 381 — Lab #6: Frequency Response of CMOS Amplifier — Rev 5.1 (8/23/15) Page 7 of 11
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Figure 4. CD4007 pin-out and specification
Electronics I – EEEE 381 — Lab #6: Frequency Response of CMOS Amplifier — Rev 5.1 (8/23/15) Page 8 of 11
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*SPICE MODELS FOR RIT DEVICES AND LABS - DR. LYNN FULLER 8-17-2015
*LOCATION DR.FULLER'S COMPUTER
*and also at: http://people.rit.edu/lffeee
*
*----------------------------------------------------------------------*Used in Electronics II for CD4007 inverter chip
*Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.1 NRS=0.1
.MODEL RIT4007N7 NMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=4E-8 XJ=2.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8
+VTH0=1.4 U0= 1300 WINT=2.0E-7 LINT=1E-7
+NGATE=5E20 RSH=300 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-8 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
*
*Used in Electronics II for CD4007 inverter chip
*Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=820u Ps=820u NRS=O.54
NRD=0.54
.MODEL RIT4007P7 PMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=5E-8 XJ=2.26E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8
+VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6
+NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-8 MJ=0.5 PB=0.94
+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5
+CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10)
*-----------------------------------------------------------------------
Electronics I – EEEE 381 — Lab #6: Frequency Response of CMOS Amplifier — Rev 5.1 (8/23/15) Page 9 of 11
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Appendix A — PSPICE Instructions
Please refer to the following for assistance in modifying the MbreakN MOSFET model. You
also need to modify the MbreakP model similarly see the spice model above for values for W, L,
NRD, and NRS.
We want to place the MbreakN Schematic symbol on our schematic then edit and display the
properties to represent the CD4007 transistors. We also want to change the name of the spice
Model from MbreakN to RIT4007N7.
Right Click on the transistor and select
“Edit Properties”, Pivot, Display, Apply
Finally, we want to let PSPICE know where to find the text
file that has the SPICE MODEL in it. That is done by editing
the PSPICE simulation profile. Under the Configuration
Files Tab, select Include, and then Browse to the Location of
the file where the SPICE model is. (Note: you should have
already placed the text file that has the RIT4007N7 SPICE
model in it on your computer in some location)
Electronics I – EEEE 381 — Lab #6: Frequency Response of CMOS Amplifier — Rev 5.1 (8/23/15) Page 10 of 11
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Teaching Assistants — Office: 09-3248
Electronics I – EEEE 381 — Lab #6: Frequency Response of CMOS Amplifier — Rev 5.1 (8/23/15) Page 11 of 11
Rochester Institute of Technology
Teaching Assistants — Office: 09-3248