NEHRU COLLEGE OF ARTS AND SCIENCE
DEPARTMENT OF ECS
EMBEDEDD SYSTEMS
UNIT I: INTRODUCTION TO EMBEDDED SYSTEMS
Definition and classification – Overview of microprocessor, Microcontroller, and DSP –
exemplary high performance processors – CISC and RISC architecture – hardware unit in an
embedded system- software embedded into a system – exemplary applications – embedded
systems on a chip and in VLSI circuit
SECTION-A
2 MARK QUESTIONS AND ANSWERS:
1. Define the term Embedded.
Ans: An embedded system is some combination of computer hardware and software,
either fixed in capability or programmable, that is specifically designed for a particular
function. Industrial machines, automobiles, medical equipment, cameras, household
appliances, airplanes, vending machines and toys (as well as the more obvious cellular
phone and PDA) are among the myriad possible hosts of an embedded system.
2. Give one difference between microcontroller and microprocessor?
Ans: Microprocessor is a also Known as 8085 IC . This 40 pin IC is use to perform many
Arithmetical and logical Operations. This IC is use to interface different IC's to perform
different work , For Example: Providing multiple interrupts using 8259 IC. Similarly we
can perform many other operation by interfacing with other IC's. This type of IC's are
used in Computers and Personal Uses.
Microcontroller is again an IC of family 8051 series. This is really specialized IC having
all the features available with 8085 and in addition to that other features like processor
core, memory, and programmable I/O peripherals. This type of IC is self sufficient, can
work solely without any help from other IC's . This Type of IC's are used in Automobile
companies, embedded systems , remote control devices.
This type of IC is usd to perform function on it's own , i.e. Automatic control is handled
here. This IC is most advance version of microprocessor which can control other process.
This IC has its own memory , I/O controls , interrupts Etc.
3. VLSI,DSP and embedded, what are the similarities between all these?
Ans:
DSP-the processing of analog signals and converting it into digital.
VLSI: Very-large-scale integration (VLSI) is the process of creating integrated circuits by
combining thousands of transistor-based circuits into a single chip. ...
Embedded: An embedded system is a computer system designed to perform one or a few
dedicated functions often with real-time computing constraints.
4. Where are Microcontrollers used?
Ans:
DVD, TV, VCR
XBOX, Nintendo, Game Boy
Carbon Monoxide Alarms
PDAs, cellphones
Automobiles
Garage door openers
Household appliances
Automatic pilot systems
Astronauts’ space suits
SECTION-B
1. Draw the architecture of Harvard and von Neumann.
2. Give the detailed difference between RISC AND CISC.
Ans:
1. RISC vs CISC
There is still considerable controversy among experts about which architecture is better.
Some say that RISC is cheaper and faster and therefor the architecture of the future.
Others note that by making the hardware simpler, RISC puts a greater burden on the
software. Software needs to become more complex. Software developers need to write
more lines for the same tasks.
Therefore they argue that RISC is not the architecture of the future, since conventional
CISC chips are becoming faster and cheaper anyway.
RISC has now existed more than 10 years and hasn't been able to kick CISC out of the
market. If we forget about the embedded market and mainly look at the market for PC's,
workstations and servers I guess a least 75% of the processors are based on the CISC
architecture. Most of them the x86 standard (Intel, AMD, etc.), but even in the mainframe
territory CISC is dominant via the IBM/390 chip. Looks like CISC is here to stay …
Is RISC than really not better? The answer isn't quite that simple. RISC and CISC
architectures are becoming more and more alike. Many of today's RISC chips support just
as many instructions as yesterday's CISC chips. The PowerPC 601, for example, supports
more instructions than the Pentium. Yet the 601 is considered a RISC chip, while the
Pentium is definitely CISC. Further more today's CISC chips use many techniques formerly
associated with RISC chips.
SECTION-C
1. Draw the block diagram of 8051.
2. Give a brief applications of Embeddeds systems in the presents trend.
Ans: An embedded system is a computer system designed to do one or a few dedicated and/or
specific functions often with real-time computing constraints. It is embedded as part of a
complete device often including hardware and mechanical parts. By contrast, a general-purpose
computer, such as a personal computer (PC), is designed to be flexible and to meet a wide range
of end-user needs. Embedded systems control many devices in common use today.
Embedded systems contain processing cores that are typically either microcontrollers or digital
signal processors (DSP). The key characteristic, however, is being dedicated to handle a
particular task. They may require very powerful processors and extensive communication, for
example air traffic control systems may usefully be viewed as embedded, even though they
involve mainframe computers and dedicated regional and national networks between airports and
radar sites (each radar probably includes one or more embedded systems of its own).
Since the embedded system is dedicated to specific tasks, design engineers can optimize it to
reduce the size and cost of the product and increase the reliability and performance. Some
embedded systems are mass-produced, benefiting from economies of scale.
UNIT-II
UNIT II: PIC 16F87X MICROCONTROLLERS
Device overview – architecture – memory organization – status register – option register – INTCON
register – PCON register – I/O ports – data EEPROM – instruction set: Byte oriented operations – Bit
oriented operations – Literal and Control operations
Section-A
1. What are the softwares used to build the pic programs. Name any 3.
•
•
Ans: MPLAB IDE v5.70
Programmer Software – Keil c
Programmer Firmware – ccs compiler
2. Define status register?
Ans: SR) Located inside the CPU and contains bits that are set or cleared based on the result of
an instruction.
3. Define option register?
Ans: The OPTION register in the PIC 16f84 microcontroller is a readable and writable register
which contains various control bits to configure the TMR0/WDT.
4. Abbriviate EEPROM?
Ans: Electrically erasable programmable read-only memory
SECTION-B
1. Explain the Pcon register.
PCON – Power
Control Register D7
D6
D5
D4
D3
D2
D1
D0
SMOD
x
x
x
GF1
GF0
PD
IDL
Address: 87H (not bit addressable)
SMOD – Serial mode bit used to determine the baud rate with Timer 1.
)]1(256[Hzin frequency Oscillator rate BaudTHN−=
If SMOD = 0 then N = 384. If SMOD = 1 then N = 192. TH1 is the high byte of timer 1 when it is in
8-bit autoreload mode.
GF1 and GF0 are General purpose flags not implemented on the standard device
PD is the power down bit. Not implemented on the standard device
IDL activate the idle mode to save power. Not implemented on the standard device.
2. Explain the INTCON register.
Ans: The INTCON Register
Bit7
Bit6
Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
GIE EEIE T0IE INTE RBIE T0IF INTF RBIF
The INTCON register is a readable and writable register which contains the
various enable bits for all interrupt sources.
The meaning of INTCON might be (though this is only me thinking) INTurrpt
CONtrol register. I have serached the net for the source of this acronym with
no avail; if you find it please e-mail me.
Anyway, interrupt flag bits get set when an interrupt condition occurs
regardless of the state of its corresponding enable bit or the global enable bit,
GIE (INTCON<7>).
This register is used to configure the interrupt control logic circuitry. Bits 0 to
6 are used to configure the interrupt enable/disable statuses and the interrupt
flags for the four interrupt sources. No interrupt to the CPU will result unless
the GIE bit is set. The GIE bit is the bit INTCON<7> and when set, enables all
un-masked interrupts.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
R = Readable bit
GIE EEIE T0IE INTE RBIE T0IF INTF RBIF
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
W= Writable bit
U = Unimplemented bit, read as
‘0’
-n= Value at POR reset
SECTION-C
1. Draw the architecture of PIC 16f87x
Ans:
Figure: PIC16F877 Block Diagram
2. Give the descriptions of Literal and Control operations?
Ans:
Literal and Control Operations:
For literal and control operations, 'k' represents an 8 or 9-bit constant or literal value. In the
machine code level in 14-bit word configuration, they are configured with 6 bits of Opcode
followed by 8 bit constant (or literal).
The table below lists the instructions words of the literal and control operations. As before, at
the last column of the table, but unlike the previous two operations, the number of bits assigned
to Opcode is fixed: some has 5, another 6, and others 3. The x marked bits in the Opcode are
don't care values (1 or 0). In most cases, the Opcode is followed by a 8 bit literal.
Table. Literal and Control Operations of 16F877 Instructions
Mnemonic Description T Flag Instruction word
(OPCODE+operand)
addlw k add k and W 1 C, Z 11 111x kkkk kkkk
andlw k and k and W 1 Z 11 1001 kkkk kkkk
call k call subroutine at address k 2 10 0kkk kkkk kkkk
clrwdt clear watchdog timer 1 00 0000 0110 0100
goto k go to address k 2 10 1kkk kkkk kkkk
iorlw k OR k with W 1 Z 11 1000 kkkk kkkk
movlw k move k to W (i.e., W=k) 1 11 00xx kkkk kkkk
retfie return from interrupt 2 00 0000 0000 1001
retlw k return with k in W 2 11 01xx kkkk kkkk
return return from subroutine 2 00 0000 0000 1000
sleep go into standby mode 1 00 0000 0110 0011
sublw k subtract W from k (i.e.,k-W) 1 C, Z 11 110x kkkk kkkk
xorlw k XOR k with W 1 Z 11 1010 kkkk kkkk
movlw 0x02, which loads a constant value of 2h to W register.
From the table, the Opcode for movlw is 110000, and the literal value component must be
00000010 (2h), which makes the corresponding machine code as 3002h.
UNIT-III
UNIT III: PERIPHERAL FEATURES OF 16F87X MICROCONTROLLERS
TIMER0 Module – TIMER1 Module – TIMER2 Module – Capture/Compare/PWM Modules – I2 C
transmission and reception – USART – ADC Module - Special features of the CPU : oscillator selection –
power on reset – power up timer – oscillator start up timer – brown out reset – interrupts – watchdog
timer
Section-A
1. Give one application of I2C?
Ans: I2C provides good support for communication with various slow, on-board peripheral
devices that are accessed intermittently, while being extremely modest in its hardware
resource needs. It is used in multimedia applications.
2. What is USART?
Ans: Universal Synchronous Asynchronous Receiver Transmitter. The USART is a full-duplex
synchronous/asynchronous receiver-transmitter proven in high-volume devices from National
Semiconductor.
3. What is function of oscillator in pic.
Ans: Using the internal 4MHz Oscillator. Depending on the PIC device programmer you're using,
there should be an option for setting the configuration-bits.
4. Name any 1 functions of interrupts?
Ans: PIC interrupt forces the microcontroller to suspend execution of the main program and immediately execute a
special set of instructions.
SECTION-B
1. Explain the timer0 module.
Ans: The Timer0 module timer/counter has the following
Features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
Additional information on the Timer0 module is
Available in the PICmicro® Mid-Range MCU Family
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0
Module will increment every instruction cycle (without
Prescaler). If the TMR0 register is written, the increment
Is inhibited for the following two instruction cycles.
The user can work around this by writing an adjusted
Value to the TMR0 register.
2. Explain the Timer1 module.
Ans: The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L) which are
readable and writable. The TMR1 register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 interrupt, if enabled,
is generated on overflow which is latched in interrupt
flag bit, TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit, TMR1IE (PIE1<0>).
Timer1 can operate in one of two modes:
• As a Timer
• As a Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
3. Draw the Timer2 module.
Ans:
U-0
—
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
R/W-0
T2CKPS0
bit 0
SECTION-C
1. Explain in detail about the Capture/compare/PWM Modules.
Ans:
Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
Both the CCP1 and CCP2 modules are identical in operation, with the exception being the operation of the
special event trigger. Table 8-1 and Table 8-2 show the resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module is described with respect to CCP1. CCP2 operates the
same as CCP1 except where noted.
CCP1 Module:
Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte).
The CCP1CON register controls the operation of CCP1. The special event trigger is
generated by a compare match and will reset Timer1.
Capture/Compare/PWM Register 2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is
generated by a compare match and will reset Timer1 and start an A/D conversion (if the A/D module is enable.
CCP MODE – TIMER
RESOURCES REQUIRED
CCP Mode Timer Resource
Capture
Timer1
Compare
PWM
Timer1
Timer2
2. Describe about the pwm and I2C?
Ans:
An Inter-IC bus is often used to communicate across circuit-board distances.
Here's a primer on the protocol.
At the low end of the spectrum of communication options for "inside the box"
communication is I2C ("eye-squared-see"). The name I2C is shorthand for a standard InterIC (integrated circuit) bus.
I2C provides good support for communication with various slow, on-board peripheral devices
that are accessed intermittently, while being extremely modest in its hardware resource
needs. It is a simple, low-bandwidth, short-distance protocol. Most available I2C devices
operate at speeds up to 400Kbps, with some venturing up into the low megahertz range. I2C
is easy to use to link multiple devices together since it has a built-in addressing scheme.
Philips originally developed I2C for communication between devices inside of a TV set.
Examples of simple I2C-compatible devices found in embedded systems include EEPROMs,
thermal sensors, and real-time clocks. I2C is also used as a control interface to signal
processing devices that have separate, application-specific data interfaces. For instance, it's
commonly used in multimedia applications, where typical devices include RF tuners, video
decoders and encoders, and audio processors. In all, Philips, National Semiconductor, Xicor,
Siemens, and other manufacturers offer hundreds of I2C-compatible devices.
Inside the box
I2C is appropriate for interfacing to devices on a single board, and can be stretched across
multiple boards inside a closed system, but not much further. An example is a host CPU on a
main embedded board using I2C to communicate with user interface devices located on a
separate front panel board. A second example is SDRAM DIMMs, which can feature an I2C
EEPROM containing parameters needed to correctly configure a memory controller for that
module.
I2C is a two-wire serial bus, as shown in Figure 1. There's no need for chip select or
arbitration logic, making it cheap and simple to implement in hardware.
The two I2C signals are serial data (SDA) and serial clock (SCL). Together, these signals
make it possible to support serial transmission of 8-bit bytes of data-7-bit device addresses
plus control bits-over the two-wire serial bus. The device that initiates a transaction on the
I2C bus is termed the master. The master normally controls the clock signal. A device being
addressed by the master is called a slave.
In a bind, an I2C slave can hold off the master in the middle of a transaction using what's
called clock stretching (the slave keeps SCL pulled low until it's ready to continue). Most I 2C
slave devices don't use this feature, but every master should support it.
The I2C protocol supports multiple masters, but most system designs include only one.
There may be one or more slaves on the bus. Both masters and slaves can receive and
transmit data bytes.
Each I2C-compatible hardware slave device comes with a predefined device address, the
lower bits of which may be configurable at the board level. The master transmits the device
address of the intended slave at the beginning of every transaction. Each slave is
responsible for monitoring the bus and responding only to its own address. This addressing
scheme limits the number of identical slave devices that can exist on an I 2C bus without
contention, with the limit set by the number of user-configurable address bits (typically two
bits, allowing up to four identical devices).
Communication
As you can see in Figure 2, the master begins the communication by issuing the start
condition (S). The master continues by sending a unique 7-bit slave device address, with the
most significant bit (MSB) first. The eighth bit after the start, read/not-write (), specifies
whether the slave is now to receive (0) or to transmit (1). This is followed by an ACK bit
issued by the receiver, acknowledging receipt of the previous byte. Then the transmitter
(slave or master, as indicated by the bit) transmits a byte of data starting with the MSB. At
the end of the byte, the receiver (whether master or slave) issues a new ACK bit. This 9-bit
pattern is repeated if more bytes need to be transmitted.
In a write transaction (slave receiving), when the master is done transmitting all of the data
bytes it wants to send, it monitors the last ACK and then issues the stop condition (P). In a
read transaction (slave transmitting), the master does not acknowledge the final byte it
receives. This tells the slave that its transmission is done. The master then issues the stop
condition.
3.
Describe the Watch dog timer?
Ans: For those embedded systems that can't be constantly watched by a human,
watchdog timers may be the solution.
Most embedded systems need to be self-reliant. It's not usually possible to wait for someone
to reboot them if the software hangs. Some embedded designs, such as space probes, are
simply not accessible to human operators. If their software ever hangs, such systems are
permanently disabled. In other cases, the speed with which a human operator might reset
the system would be too slow to meet the uptime requirements of the product.
A watchdog timer is a piece of hardware that can be used to automatically detect software
anomalies and reset the processor if any occur. Generally speaking, a watchdog timer is
based on a counter that counts down from some initial value to zero. The embedded
software selects the counter's initial value and periodically restarts it. If the counter ever
reaches zero before the software restarts it, the software is presumed to be malfunctioning
and the processor's reset signal is asserted. The processor (and the embedded software it's
running) will be restarted as if a human operator had cycled the power.
Figure 1 shows a typical arrangement. As shown, the watchdog timer is a chip external to
the processor. However, it could also be included within the same chip as the CPU. This is
done in many microcontrollers. In either case, the output from the watchdog timer is tied
directly to the processor's reset signal.
Kicking the dog
The process of restarting the watchdog timer's counter is sometimes called "kicking the
dog." The appropriate visual metaphor is that of a man being attacked by a vicious dog. If
he keeps kicking the dog, it can't ever bite him. But he must keep kicking the dog at regular
intervals to avoid a bite. Similarly, the software must restart the watchdog timer at a regular
rate, or risk being restarted.
A simple example is shown in Listing 1. Here we have a single infinite loop that controls the
entire behavior of the system. This software architecture is common in many embedded
systems with low-end processors and behaviors based on a single operational frequency.
The hardware implementation of this watchdog allows the counter value to be set via a
memory-mapped register.
Listing 1: Kicking the dog
uint16 volatile * pWatchdog =
(uint16 volatile *) 0xFF0000;
main(void)
{
hwinit();
for (;;)
{
*pWatchdog = 10000;
read_sensors();
control_motor();
display_status();
}
}
Suppose that the loop must execute at least once every five milliseconds. (Say the motor
must be fed new control parameters at least that often.) If the watchdog timer's counter is
initialized to a value that corresponds to five milliseconds of elapsed time, say 10,000, and
the software has no bugs, the watchdog timer will never expire; the software will always
restart the counter before it reaches zero.
Software anomalies
A watchdog timer can get a system out of a lot of dangerous situations. However, if it is to
be effective, resetting the watchdog timer must be considered within the overall software
design. Designers must know what kinds of things could go wrong with their software, and
ensure that the watchdog timer will detect them, if any occur.
Systems hang for any number of reasons. A logical fallacy resulting in the execution of an
infinite loop is the simplest. Suppose such a condition occurred within the read_sensors()
call in Listing 1. None of the other software (except ISRs, if interrupts are still enabled)
would get a chance to run again.
Another possibility is that an unusual number of interrupts arrives during one pass of the
loop. Any extra time spent in ISRs is time not spent executing the main loop. A dangerous
delay in feeding the motor new control instructions could result.
When multitasking kernels are used, deadlocks can occur. For example, a group of tasks
might get stuck waiting on each other and some external signal that one of them needs,
leaving the whole set of tasks hung indefinitely.
If such faults are transient, the system may function perfectly for some length of time after
each watchdog-induced reset. However, failed hardware could lead to a system that
constantly resets. For this reason it may be wise to count the number of watchdog-induced
resets, and give up trying after some fixed number of failures.
Karate lessons
An actual watchdog implementation would usually have an interface to the software that is
more complex than the one in Listing 1. When the set of instructions required to reset the
watchdog is very simple, it's possible that buggy software could perform this action by
accident. Consider a bug that causes the value 10,000 to be written to every location in
memory, over and over again. This code would regularly restart the watchdog counter, and
the watchdog might never bite. To prevent this, many watchdog implementations require
that a complex sequence of two or more consecutive writes be used to restart the watchdog
timer.
If the watchdog is built into your microcontroller, it may not be enabled automatically when
the device resets. You must be sure to enable it during hardware initialization. To provide
protection against a bug accidentally disabling the watchdog, the hardware design usually
makes it impossible to disable the watchdog timer once it has been enabled.
If your software can do a complete loop faster than the watchdog period, the structure in
Listing 1 may work fine for you. It gets more challenging if some part of your software takes
a long time to complete. Say you have a loop that waits for an element to heat to a certain
temperature before returning. Many watchdog timers have a maximum period of around two
seconds. If you are going to delay for more than that length of time, you may have to kick
the dog from within the waiting loop. If there are many such places in your software, control
of the watchdog can become problematic.
System initialization is a part of the code that often takes longer than the watchdog timer's
maximum period. Perhaps a memory test or ROM to RAM data transfer slows this down. For
this reason, some watchdogs can wait longer for their first kick than they do for subsequent
kicks.
As threads of control are added to software (in the form of ISRs and software tasks), it
becomes ineffective to have just one place in the code where the watchdog is kicked.
Choosing a proper kick interval is also an important issue, one that can only be addressed in
a system-specific manner. These and other issue of greater complexity are discussed in the
references listed at the end of this article.
Dog days
A watchdog timer is a useful tool in helping your system recover from transient failures.
Since it is so common to find watchdogs built into modern microcontrollers, the technique is
effectively free. If you are working on a mission-critical system, then either common sense
or a regulatory body will insist that you use a watchdog. It's always a good idea to make
your systems more self-reliant.
UNIT-IV
UNIT IV: REAL TIME OPERATING SYSTEMS
Definitions of process, tasks, and threads – Operating system services – goals – structures- kernel –
process management – memory management – device management – file system organization and
implementation – I/O sub systems – interrupt routine handling in RTOS – RTOS task scheduling models –
handling of task scheduling – latency – deadlines – round robin scheduling – cyclic scheduling –
preemptive – critical session – static real time scheduling – IPC and synchronization – use of semaphore
– priority inversion – deadlock – IPC using signals – mutex- flag- message queues – mailboxes – pipesvirtual sockets – remote procedure calls
SECTION-A
1. Define RTOS?
Ans: A real-time operating system (RTOS) is an operating system that guarantees a certain
capability within a specified time constraint. For example, an operating system might be
designed to ensure that a certain object was available for a robot on an assembly line. In what is
usually called a "hard" real-time operating system, if the calculation could not be performed for
making the object available at the designated time, the operating system would terminate with a
failure. In a "soft" real-time operating system, the assembly line would continue to function but
the production output might be lower as objects failed to appear at their designated time, causing
the robot to be temporarily unproductive.
2. What is memory management?
Ans: When preparing a server for production, you usually run the server through a series of
processes and procedures that are designed to keep it secure.
Section-B
1. Describe about the Real time kernel?
The heart of a real-time OS (and the heart of every OS, for that matter) is the kernel. A kernel is
the central core of an operating system, and it takes care of all the OS jobs:
1. Booting
2. Task Scheduling
3. Standard Function Libraries
Now, we will talk about booting and bootloaders later, and we will also devote several chapters
to task scheduling. So we should mention at least one thing about standard function libraries: In
an embedded system, there is rarely enough memory (if any) to maintain a large function library.
If functions are going to be included, they must be small, and important.
In an embedded system, frequently the kernel will boot the system, initialize the ports and the
global data items. Then, it will start the scheduler and instantiate any hardware timers that need to
be started. After all that, the Kernel basically gets dumped out of memory (except for the library
functions, if any), and the scheduler will start running the child tasks.
2. Describe the memory management in RTOS?
Memory management
An RTOS uses small memory size by including only the necessary functionality for an
application while discarding the rest. Below we discuss static and dynamic memory management
in RTOSs.
Static memory management provides tasks with temporary data space. The system’s free memory
is divided into a pool of fixed sized memory blocks, which can be requested by tasks. When a
task finishes using a memory block it must return it to the pool. Another way to provide
temporary space for tasks is via priorities. A pool of memory is dedicated to high priority tasks
and another to low priority tasks. The high-priority pool is sized to have the worst-case memory
demand of the system. The low priority pool is given the remaining free memory. If the low
priority tasks exhaust the low priority memory pool, they must wait for memory to be returned
to the pool before further execution.
Dynamic memory management employs memory swapping, overlays, multiprogramming with a
fixed number of tasks (MFT), multiprogramming with a variable number of tasks (MVT) and
demand paging.
Overlays allow programms larger than the available memory to be executed by partitioning the
code and swapping them from disk to memory. In MFT, a fixed number of equalized code parts
are in memory at the same time. As needed, the parts are overlaid from disk.
MVT is similar to MFT except that the size of the partition depends on the needs of the program
in MVT.
Demand paging systems have fixed-size pages that reside in non-contiguous memory, unlike
those in MFT and MVT [7]. In many embedded systems, the kernel and application programs
execute in the same space i.e., there is no memory protection.
3. Explain the round robin scheduling?
Ans:
In the round robin scheduling, processes are dispatched in a FIFO manner but are given a
limited amount of CPU time called a time-slice or a quantum.
If a process does not complete before its CPU-time expires, the CPU is preempted and given to
the next process waiting in a queue. The preempted process is then placed at the back of the
ready list.
Round Robin Scheduling is preemptive (at the end of time-slice) therefore it is effective in timesharing environments in which the system needs to guarantee reasonable response times for
interactive users.
The only interesting issue with round robin scheme is the length of the quantum. Setting the
quantum too short causes too many context switches and lower the CPU efficiency. On the other
hand, setting the quantum too long may cause poor response time and appoximates FCFS.
In any event, the average waiting time under round robin scheduling is often quite long.
SECTION - C
1. Write a simple program using the RTOS task?
Example Real Time Execution Profile
This section provides a simplistic example that demonstrates the principles of real time scheduling.
A hypothetical embedded system incorporates a keypad and LCD. A user must receive the visual
feedback of each key press within a reasonable period—if the user cannot see that the key press has
been accepted within this period the product will at best be awkward to use. If the longest acceptable
period is 100ms—any response between 0 and 100ms is acceptable. This functionality could be
implemented as an autonomous task with the following structure:
void vKeyHandlerTask( void *pvParameters )
{
/* Key handling is a continuous process and as such the task
is implemented using an infinite loop (as most tasks are). */
for( ;; )
{
[Suspend waiting for a key press]
[Process the key press]
}
}
Listing 1: Task that records key strokes
Now assume the software is also performing a control function that relies on a digitally filtered input. The input must be sampled,
filtered, and the control cycle executed every 2ms. For correct operation of the filter the temporal regularity of the sample must be
accurate to 0.5ms. This functionality could be implemented as an autonomous task with the following structure:
void vControlTask( void *pvParameters )
{
for( ;; )
{
[Suspend waiting for 2ms since the start of the previous
cycle]
[Sample the input]
[Filter the sampled input]
[Perform control algorithm]
[Output result]
}
}
2. Explain about the IPC and Synchronization?
Use of Multiple Semaphores for
Synchronizing the Tasks
Use of two semaphores for synchronizing
tasks I, J, K, L and M
, respect
3. Describe about the file system management?
Ans:
File-System Structure (1)
File

system resides on secondary storage
disks, diskette, CD-ROM, DVD

flash memory – with or without disk interfaces

virtual disk, or memory disk
File

system design problems
to define how the file system should look to the use
file and its attribute

operation or command allowed on a file


to design algorithm and data structure to map the
logical file system to the physical storage devices
File-System Structure (2)
File
system organized into layers.
I/O Control layer – consisting of device drivers and
interrupt handlers to transfer data b/w the main memory
and the storage system. It translates high- level
commands to low-level hardware-specific instructions

basic file system – to issue generic command to the
device driver

file-organization module – to translate a logical address
to a physical address, and free-space manager

logical file system – to manage metadata information
(file-system structure, but not the content), to manage
the directory system and symbolic file name, to
maintain file structure via file control block

File-System Structure (3)
control block – storage structure consisting of
information about a file.
File
ownership, permissions, location of the file
contents, …

Existing
file systems

UFS – Unix file system

ext, or ext2 – Linux file system

FAT, FAT32 – DOS file system

NTFS – Windows NT or its successors file
Systems
File-System Implementation (1)
file
system consists of on-disk structure and in-memory
Structure
on-disk
structure
boot control block – information needed by the system
to boot an OS from that disk. Typically the first block
of a partition. Called boot block in UFS; partition boot
sector in NTFS

partition control block – partition detail s.t. the # of
blocks, the size of the blocks, free-block count, freeblock
pointers, and so forth. superblock (in UFS) or
master file table (in NTFS)



directory structure
file control block – file’s detail. file permission,
ownership, size, location of the data block.
File-System Implementation (2)
in-memory
structure
used for file-system management and performance
improvement via caching

in- memory partition table – information about each
mounted partition

in- memory directory structure – holds the directory
information of recently accessed directories

system-wide open- file table – a copy of file control
block of each open file

per-process open- file table - has a pointer to the proper
entry in system-wide open- file table, a pointer to the
current location of the file for read/write operations

File-System Implementation (3)
to
creat a file

allocate a new FCB,

read the proper directory into memory

update it with the new file name and FCB

write it back to the disk
In
Unix, a directory is treated exactly as a file, but
in Windows, a directory is treated separate entities
from files.
In-Memory File System Structures
UNIT –V
UNIT V: RTOS Programming Tools: Micro C/OS-II and Vxworks
Study of Micro C/OS-II – VxWorks – other popular RTOS – RTOS system level functions – task service
functions – time delay functions – memory allocation related functions – semaphore related functions –
mailbox related functions – queue related functions case studies of programming with RTOS –
understanding case definition - multiple tasks and their functions – creating a list of tasks- functions and
IPCs – exemplary coding steps
Section-A
1. What is a Operating system?
Ans: An Operating System is a computer program that manages the resources of a computer.
It accepts keyboard or mouse inputs from users and displays the results of the actions and
allows the user to run applications, or communicate with other computers via networked
connections
2. Define Exemplary codings?
Ans: Understanding case definition – Multiple tasks and their functions. Creating a List of
Tasks, Functions and IPCs.
3. Give an applications of IPC’s.
Ans: With the IPC software, embedded developers can efficiently and better control their multicore processor implementation and common real-time.
Section-B
1.
Explain about the time delay functions?
Ans:
Embed <- function(x, m, d = 1, as.embed = TRUE) {
n <- length(x) - (m-1)*d
if(n <= 0)
stop("Insufficient observations for the requested embedding")
out <- matrix(rep(x[seq_len(n)], m), ncol = m)
out[,-1] <- out[,-1, drop = FALSE] +
rep(seq_len(m - 1) * d, each = nrow(out))
if(as.embed)
out <- out[, rev(seq_len(ncol(out)))]
out
}
Time delay embedding allows for additional delay between the lagged versions of the
original series. If d = 2, then each of the m - 1 new series is lagged by 2 time intervals.
This is shown in the final example above, with Embed(1:10, m = 4, d = 2), where the
entries within the rows are offset by 2. However, the embedded series now contain just
four observations.
2. Name any two queue related functions for the inter task communications.
Queue related functions includes
.Creating a queue for an IPC,
Waiting for an IPC messagea t a queue,
Emptying the Queue and Eliminating All the Message pointers,. Sendinga message-pointetor the
Queue,. Sending a message pointer and inserting at the Queue Front and Querying to Find the
Message and Enor Information for the Queue ECB.
To connect a message queue, or create it if it doesn\'t exist. The call to accomplish this is the
msgget() system call:
int msgget(key_t key, int msgflg);
SECTION-C
1. Explain about the multiple tasks and their functions?
Ans:
Multitasking using an operating
system (OS) and Real time operating system (RTOS), Concurrent Processes, tasks
or threads
A System is composed of twoor more concurrent processes that execute Operating
System
Multitasking (multiprocessing ormultithreaded) software Scheduling multiple tasks,
Processes, memory, device, ports,network, file system, timers, eventfunctions, inter
processorcommunication, shared memory,security, GUIs, ... management
Real Time Operating System (RTOS)
Embedded software is most often designedfor deterministic performance and task and ISR
latencies in addition to the OSfunctions
Performing multiple actions andcontrolling multiple devices and their ISRswith defined
real time constraints and with deadlines for these Task and ISRs priority allocations, their
processing and execution with hard(stringent) or soft timing requirements with priority allocation
and preemption.
RTOS is needed when the tasks for thesystem have real time constraints anddeadlines for
finishing the tasks
2. Describe about the memory management functions or memory allocation functions?
Ans:
Memory Management Functions
Memory allocation
when a process is created, the memory manager allocates the memory addresses (blocks) to
it by mapping the process address space.
Threads of a process share the memory space of the process
Memory manager of the OS─ secure, robust and well protected.
No memory leaks and stack overflows
Memory leaks means attempts to write in the memory block not allocated to a process or
data structure.
Stack overflow means that the stack exceeding the allocated memory block(s)
Memory Management after Initial Allocation
Memory Managing Strategy for a system
Fixed-blocks allocation
Dynamic -blocks Allocation
Dynamic Page-Allocation
Dynamic Data memory Allocation
Dynamic address-relocation
Multiprocessor Memory Allocation
Memory Protection to OS functions
Memory allocation in RTOSes
RTOS may disable the support to the dynamic block allocation, MMU support to dynamic
page allocation and dynamic binding as this increases the latency of servicing the tasks and
ISRs.
RTOS may not support to memory protection of the OS functions, as this increases the
latency of servicing the tasks and ISRs.
User functions are then can run in kernel space and run like kernel functions
RTOS may provide for disabling of the support to memory protection among the tasks as
this increases the memory requirement for each task
Memory Manager functions
(i)
use of memory address space by a process,
(ii) specific mechanisms to share the memory space and
specific mechanisms to restrict sharing of a given memory space
(iv) optimization of the access periods of a memory by using an hierarchy of memory (caches,
primary and external secondary magnetic and optical memories).
Remember that the access periods are in the following increasing order: caches, primary and
external secondary magnetic and then or optical.
Fragmentation Memory Allocation
Problems
Fragmented not continuous memory addresses in two blocks of a process
Time is spent in first locating next free memory address before allocating that to the
process.
A standard memory allocation scheme is to scan a linked list of indeterminate length to find
a suitable free memory block.
When one allotted block of memory is deallocated, the time is spent in first locating next
allocated memory block before deallocating that to the process.
the time for allocation and de-allocation of the memory and blocks are variable (not
deterministic) when the block sizes are variable and when the memory is fragmented.
In RTOS, this leads to unpredicatble task performance
Memory management Example
RTOS COS-II
Memory partitioning
A task must create a memory partition or several memory partitions by using function
OSMemCreate ( )
Then the task is permitted to use the partition or partitions.
A partition has several memory blocks.
Task consists of several fixed size memory blocks.
The fixed size memory blocks allocation and de-allocation time takes fixed time
(deterministic).
OSMemGet ( )
─ to provide a task a memory block or blocks from the partition
OSMemPut ( )
─ to release a memory block or blocks to the partition
3. Give a short note on semaphore related functions?
Ans:
Semaphore Functions
Provides for using same semaphorefunctions as an event signaling flagor mutex or counting
semaphore.
OSSemCreate (semVal)
OSSemPend (*eventPointer, timeOut,*SemErrPointer)
OSSemAccept (*eventPointer)
OSSemPost (*eventPointer)
OSSemQuery (*eventPointer