USB3.0 ReDriver PI3EQX7741AI_PI3EQX7841 co-design and Application Note
Measured by: YT, Anne, Jerry
Reported by: YT, Anne, Jerry
Rev B
Introduction
In Server/Workstation/PC/embedded application customer, the stability and performance quality margin will be the
most important point to their product. Therefore Pericom provide the different USB3.0 redriver solution for different
kind of application area to meet customer’s requirement. Suggest to use PI3EQX7741AI / PI3EQX7841 co-design
to optimize the compensation setting for performance and get better margin for system.

(A) Example why use Pericom PI3EQX7741AI/PI3EQX7841 USB3.0 ReDriver in Server/Workstation
Application (Include with USB3.0 MUX application)

(B) Different EQ vs same insertion lose

(C) Pericom PI3EQX7741AI/PI3EQX7841 USB3.0 redriver co-design guide

(D) USB3.0 SuperSpeed USB Layout Guideline
(A) Example why use Pericom PI3EQX7741AI/PI3EQX7841 USB3.0 ReDriver in
Server/Workstation Application
1. For USB3.0 long distance(maximum 20db lose) design Vth function benefit of PI3EQX7741AI/PI3EQX7841
After 20db loss Vpp
should be around 100mV
Server customer typical application
Host output 1.0V
PI3EQX7741AI/PI3EQX7841
AC Coupling Cap1
AC Coupling Cap3
HOST TX+
TX
TX
HOST TXAC Coupling Cap2
AC Coupling Cap4
AC Coupling Cap5
HOST RX+
RX
RX
HOST RXAC Coupling Cap6
20db loss
HOST
Controller
USB3.0 Connector
HOST
Controller
Vth set below 100mV
5db loss
PI3EQX7741AI/PI3EQX7841
USB3.0
Connector
Figure 1 Vth function Block Diagram of PI3EQX7741AI/PI3EQX7841
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2. PI3EQX7841 OS(output swing) set to 1200mV to get better performance margin
PI3EQX7841 Output Swing=1200mV
Server customer typical application
AC Coupling Cap1
AC Coupling Cap3
HOST TX+
TX
TX
HOST TXAC Coupling Cap2
AC Coupling Cap4
AC Coupling Cap5
HOST RX+
RX
RX
HOST RXAC Coupling Cap6
15db loss
HOST
Controller
USB3.0 Connector
PI3EQX7841
HOST
Controller
10db loss
PI3EQX7841
USB3.0
Connector
Figure 2 Output Swing improve Block Diagram of PI3EQX7841
3. PI3EQX7741/PI3EQX7841 with USB3.0 MUX insertion loss limit and placement suggestion application
Before Re-driver the maximum redriver insertion loss is about 16db@2.5GHZ
After Re-driver the maximum redriver insertion loss is about 4db@2.5GHZ
Figure 3 USB3.0 Mux with Re-driver application Block Diagram of PI3EQX7841/PI3EQX7741
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4. PI3EQX7841 can optimize EQ/DE/OS setting to meet customer’s loss compensation design
Redriver
Description
PI3EQX7741AI
PI3EQX7841
Setting
Equalizer
3-level by H/W (3 / 8.3 /11.7 db)
EQ_A/B
3-level (3/6/9 db)
compensation
16-level by I2C (0~15db)
De-emphasis
3-level by H/W (0/-3.5/-6 db)
DE_A/B
3-level(0/-3.5/-6 db)
compensation
4-level by I2C (0/-2/-3.5/-6 db)
Output Swing
3-level by H/W (900/1000/1200mV)
OS_A/B
NA
compensation
4-level by I2C (900/1000/1100/1200mV)
Below table is the loss in any conditions to ref.
Loss (db)
PCB Conditions
1 inch in FR4 trace
Via/AC cap
Connector
0.5 ~ 0.8 db (top side 7 mil is 0.5 db, internal 3.5 mil is 0.8db)
0.3 ~ 0.8 db (variation by via design)
1 ~ 2 db
Measurement the relation of the loss and the 2.5GHz CP1 Vpp
Channel loss after source
CP1 Vpp after the channel loss
0 db loss
1.0Vpp
6 db loss
0.5Vpp
12 db loss
0.25Vpp
18 db loss
0.125Vpp
20 db loss
0.1Vpp
(B) Different EQ vs same insertion lose
Typical Eye Diagram of different EQ setting with the same input trace loss
RedRiver EQ and
PCB Input
De-emphasis
TX eye diagram Result
trace loss
Setting
EQ=3db
DE=0db
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10 db loss
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Page 4 of 10
EQ=6db
DE=0db
10 db loss
EQ=9db
DE=0db
10 db loss
EQ=12db
DE=0db
10 db loss
Pericom Semiconductor Corp.
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2/8/2016
(C)Pericom PI3EQX7741AI/PI3EQX7841 USB3.0 redriver co-design guide
PI3EQX7741AI/PI3EQX7841 is a dual channel/one port (both TX± and RX±). Each channel offers selectable
equalization setting to compensate the different input trace loss. These two parts are pin compatible with each other
and can be co-designed, customer can test PI3EQX7741AI first, if the performance is not good enough, can replace
to PI3EQX7841 control by H/W or I2C to optimize EQ/DE/OS setting.
Figure 3-1 Pin Diagram of PI3EQX7741AI
Figure 3-2 Pin Diagram of PI3EQX7841
Figure 4-1 EQ/DE setting table of PI3EQX7741AI
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Figure 4-2 EQ/DE/OS setting table by H/W and I2C of PI3EQX7841
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Reference Co-Design for PI3EQX7741AI/PI3EQX7841
RXDET/OS_A/SCL R19
0 ohm
3.3V
HOST_SCL
3.3V
DE_A/SDA R20
0 ohm
HOST_SDA
3.3V
3.3V
3.3V
3.3V
R12
4.7K
R16
4.7K
R1
4.7K
Stuff R19 and R20 for PI3EQX7841 I2C mode
R3
4.7K
R8
4.7K
R10
4.7K
RXDET/OS_A/SCL
EQ_A
R17
4.7K
3.3V
C1
10uF
C2
DE_B/A0
DE_A/SDA
R2
4.7K
R4
4.7K
EQ_B
R9
4.7K
Vth/OS_B/A1
R11
4.7K
R6
4.7K
Reserved pin. Tie RES Pin
high for normal operation
R7
4.7K
Stuff R12 for PI3EQX7841 I2C
Enable.
EN_B#/I2C_EN
R13
4.7K
Stuff R13 for PI3EQX7741 pull
Low Enable CH B.
R14
4.7K
Stuff R14 for PI3EQX7841
Enable.
EN_A#/EN# GPIO control
R15
4.7K
Stuff R15 for PI3EQX7741 pull
Low Enable CH A.
C3
0.1uF
0.1uF
PI3EQX7741STZDE / PI3EQX7741I Colay PI3EQX7841ZDE @TQFN20
RXDET/OS_A/SCL
PHY
EN_A#/EN#
SSRXSSRX+
C6 0.1uF
C7 0.1uF
1
2 AI+
AI3
EN_A#/EN#
4
5 BOBO+
EQ_A
NC
C8 0.1uF
C9 0.1uF
USB3.0 Device
A type
Type A Connector use
15
AO+ 14
AO-
EN_B#/I2C_EN
Host
C4 0.1uF
C5 0.1uF
side pin define
USB3.0 RX+
USB3.0 RX-
EN_B#/I2C_EN
13
USB3.0 TX+
USB3.0 TX-
12
BI- 11
BI+
VDD3P3
SSTX+
SSTX-
NC
HGND
EQ_B
VDD3P3
DE_B / A0
RXDET/ OS_A/ SCL
Vth/OS_B/A1
DE_A/SDA
U1
USB3.0 Connector
3.3V
6
EQ_B
7
DE_B/A0
8
9
10
USB3.0 controller
21
20
19
18 DE_A/SDA
17
EQ_A
16
3.3V
USB3.0
3.3V
3.3V
D+ FS/HS/LS USB2.0
Vth/OS_B/A1
USB2.0 FS/HS/LS D+
D- FS/HS/LS PHY
PHY FS/HS/LS D-
NOTE: Type B Connector use DEVICE
side pin define
Figure 5:PI3EQX7741AI/PI3EQX7841 co-design circuit
PI3EQX7741AI_Colay_PI3EQX7841_Typ App schematic.zip
Page 7 of 10
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3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R1
4.7K
C1
10uF
C2
R3
4.7K
R8
4.7K
R10
4.7K
R6
4.7K
Reserved pin. Tie RES Pin
high for normal operation
C3
0.1uF
0.1uF
EQ_A
DE_B
DE_A
R2
4.7K
R4
4.7K
EQ_B
R9
4.7K
R5 NC
R7
4.7K
USB3.0 Connector
DE_A
EQ_A
3.3V
Vth
R11
4.7K
A type
C8 0.1uF
C9 0.1uF
PHY
C6 0.1uF
C7 0.1uF
AI+
AIEN_A#
BOBO+
6
EQ_B 7
DE_B 8
Vth
9
10
SSRXSSRX+
1
2
3
4
5
HGND
VDD3P3
RXDET
DE_A
EQ_A
NC
SSTX+
SSTX-
NC
EQ_B
DE_B
Vth
VDD3P3
USB3.0
21
20
19
18
17
16
USB3.0 controller
U1
USB3.0 Device
USB3.0 RX+
Type A Connector use
C4 0.1uF
AO+
AOEN_B#
BIBI+
15
14
13
12
11
Host
USB3.0 RX-
side pin define
C5 0.1uF
USB3.0 TX+
USB3.0 TX-
PI3EQX7741STZDE / PI3EQX7741I @TQFN20
3.3V
USB2.0 FS/HS/LS D+
PHY
FS/HS/LS D-
D+ FS/HS/LS
USB2.0
D- FS/HS/LS
PHY
NOTE:
Type B Connector use DEVICE
side pin define
NOTE:
After PCB layout, de-emphasis, and Equalizer should be fine tune
Output de-emphasis setting
DE_A/B
De-emphasis
Equalizer setting
Description
EQ_A/B
@2.5GHz
Description
0
0 dB
R3 & R8 NC, R4 & R9 on
0
3 dB
R1 & R10 NC, R2 & R11 on
open
-3.5 dB
R3 & R8 NC, R4 & R9 NC
open
6 dB
R1 & R10 NC, R2 & R11 NC
1
-6 dB
R3 & R8 on, R4 & R9 NC
1
9 dB
R1 & R10 on, R2 & R11 NC
EN_x#
RxDet
1
Input R
Output R
X
Hi-Z
Hi-Z
0
1
50 ohm / Hi-Z
50 ohm / Hi-Z
0
0
50 ohm
50 ohm
Figure 6:PI3EQX7741AI Typ App circuit
PI3EQX7741AI_USB3_Typ App Schematic.zip
Page 8 of 10
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Vdd=3.3V
Vdd=3.3V
R3
4.7K
R4
4.7K
Vdd=3.3V
Vdd=3.3V
R5
4.7K
Vdd=3.3V
Vdd=3.3V
Vdd=3.3V
R7
4.7K
R8
4.7K
R6
4.7K
NOTE:
After PCB layout, output swing, de-emphasis, and
Equalizer should be fine tune
Equalizer setting(pin strap control)
EQ_A
DE_A/SDA
C3
0.1uF
Vdd=3.3V
USB3.0 controller
U1
USB3.0
SSTX+
SSTX-
PHY
SSRXSSRX+
1
2
EN# GPIO control 3
4
5
C7 0.1uF
OS_A/SCL
R14
4.7K
EQ_B
R15
4.7K
AI+
AIEN#
BOBO+
C8 0.1uF
AO+
AOI2C_EN
BIBI+
DE_B/A0
R16
4.7K
21
20
19 OS_A/SCL
18 DE_A/SDA
EQ_A
17
16
R13
4.7K
HGND
VDD33
OS_A/SCL
DE_A/SDA
EQ_A
DNC
C2
0.1uF
DNC
EQ_B
DE_B/A0
OS_B/A1
VDD33
C1
10uF
OS_B/A1
R17
4.7K
OS_A/SCL R19
0 ohm
DE_A/SDA R20
0 ohm
R18
4.7K
USB3.0 Connector
HOST_SCL
EQ_A/B
Equalizer
Description
HOST_SDA
0
3.3 dB
R3 & R6 NC,
R13 & R16 on
open
8.1 dB
R3 & R6 NC,
R13 & R16 NC
1
11.7 dB
R3 & R6 on,
R13 & R16 NC
USB3.0 Device
Output de-emphasis setting (pin strap control)
A type
C5 0.1uF
C6 0.1uF
15
14
13
12
11
Type A Connector use
Host
side pin define
USB3.0 RX+
DE_A/B
USB3.0 RX-
De-emphasis
Description
0
0 dB
R4 & R7 NC, R14 & R17 on
open
-3.5 dB
R4 & R7 NC, R14 & R17 NC
1
-6 dB
R4 & R7 on, R14 & R17 NC
Vdd=3.3V
R21
USB3.0 TX+
4.7K
USB3.0 TX-
6
7
8
9
10
PI3EQX7841ZDE@TQFN20
Vdd=3.3V
EQ_B
DE_B/A0
OS_B/A1
Output Swing setting (pin strap control)
NOTE:
USB2.0 FS/HS/LS D+
PHY
FS/HS/LS D-
Type B Connector use DEVICE
side pin define
D+ FS/HS/LS
D- FS/HS/LS
OS_A/B
output swing
Description
0
900 mVppd
R5 & R8 NC, R15 & R18 on
open
1000 mVppd
R5 & R8 NC, R15 & R18 NC
1
1200 mVppd
R5 & R8 on, R15 & R18 NC
USB2.0
PHY
Pin function description
Pin Name
Pin strap control
I2C control
I2C_EN = Low (R21=NC)
I2C_EN = High (R21=ON)
DE_B / A0
B_DE = CHB De-emphasis Selection, Adjustment by R7 & R17
See the configuration table of de-emphasis
A0 = I2C programmable address bit A0
Adjustment by R7 & R17
OS_B / A1
B_OS = CHB Swing Selection, Adjustment by R8 & R18
See the configuration table of Swing
A1 = I2C programmable address bit A1
Adjustment by R8 & R18
R20 = NC
A_DE = CHA De-emphasis Selection, Adjustment by R4 & R14
See the configuration table of de-emphasis
R20 = ON, R4=NC, R14=NC
SDA = Data line for I2C programming
R19=NC
A_OS = CHA Swing Selection, Adjustment by R5 & R15
See the configuration table of Swing
R19 = ON, R5=NC, R15=NC
SCL = Clock line for I2C programming
DE_A / SDA
OS_A / SCL
Figure 7: PI3EQX7841 Typ App circuit
PI3EQX7841_USB3_Typ App Schematic.zip
Page 9 of 10
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2/8/2016
(D)USB3.0 SuperSpeed USB Layout Guideline
A. PCB differential Impedance 72~98 ohm define in USB-IF
B. Decoupling capacitor of VDD
It is recommended to put 0.1uF decoupling capacitor at each VDD pin of Pericom IC. Below is a layout reference of
decoupling capacitor placement on a PI3EQX7741AI/PI3EQX7841 demo board. Two decoupling capacitors circled in
pink below are located next to the four VDD pins (pins 10 and 20) of PI3EQX7741AI.
Figure 8: Decoupling Capacitor Placement on PI3EQX7741ST
C. PCB layers
It is recommended to use at least four layers PCB for SuperSpeed USB design. Every data signal trace should be
routed entirely over the ground plane on an adjacent layer.
Recommendation on 4-layer PCB setting:
Layer
Top
2nd
3rd
Bottom
Page 10 of 10
Setting 1
Data signal, Clock
GND
Power, GND
Power, Control signal
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Setting 2
Power, Control Signal
Power, GND
GND
Data signal, Clock
2/8/2016