International Journal of Advanced Computer Engineering and Communication Technology (IJACECT)
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Nanometric 4-Bit Binary Counter with Parallel Load Using Reversible
Logic
Bhagyashree Ashok Gavhane1 & Prashant Vitthalrao Kathole2
M. Tech VLSI System Design, Nishitha College of Engineering & Technology, Lemoor, Hyderabad
Email: bhagyashree.gavhane@gmail.com, prashant.kathole@gmail.com
Abstract – In recent years, reversible logic has considered
as an efficient computing method having its applications in
quantum
computing,
low
power
computing,
nanotechnology and DNA computing. All of the Boolean
functions can be implemented using reversible gates. In
this paper, we propose a reversible 4-Bit binary counter
with parallel load. It has minimum complexity and
quantum cost considerably. Counter is essentially a
register that goes through a predetermined sequence of
states. The reversible gates in the counter are connected in
such a way as to produce the prescribed sequence of binary
states. This counter receives a 4-Bit data from input and
delivers data to D Flip Flop in next cycle. The reversible
gates used for our reversible logic synthesis are Feynman
gate, Peres gate and Fredkin gate. The resulting reversible
circuit is the first attempt and leads to an efficient state for
a nano-metric reversible 4-Bit binary counter. More
complex systems can also be constructed using the
proposed methodology, which supports minimum number
of the garbage outputs and constant inputs.
Keywords – DNA Computing, Reversible Logic,
Nanometric binary counter, Quantum Computing, Qubits,
Quantum cost, Nanotechnology.
I. INTRODUCTION
Power dissipation is one of the most important factors in
VLSI circuit design. It has been already proven that zero
energy dissipation is possible only if the gating network
consists of reversible gates. Thus reversibility will
become future trends towards low power dissipating
circuit design. Conventional logic gates are having
certain inadequacy that they are responsible for making
more power dissipation by introducing larger gate count
in the digital circuits. One has to consider this issue in
the design of complex sequential circuits, where limited
power resources are present. As discussed earlier,
Reversible gates (Also known as Quantum Gates) are
the solution for this problem. Because, Irreversible logic
circuits dissipates kT*log 2 Joule (k is the Boltzmann
constant and T is the absolute temperature) heat for
every bit of information that is lost irrespective of their
implementation technologies which are used in
conventional logic gates circuits. Information is lost
when the input vectors cannot be recovered from
circuit’s output vectors. Reversible logic naturally takes
care of heating since in reversible circuits the input
vectors can be uniquely recovered from its
corresponding output vectors.
II. METHODOLOGY
A. Fan-out in Digital Electronics
In digital electronics, the fan-out of a logic gate output is
the number of gate inputs it can feed or connect to. In
most designs, logic gates are connected to form more
complex circuits. While no more than one logic gate
output is connected to any single input, it is common for
one output to be connected to several inputs. The
technology used to implement logic gates usually allows
a certain number of gate inputs to be wired directly
together without additional interfacing circuitry.
The maximum fan-out of an output measures its loaddriving capability: it is the greatest number of inputs of
gates of the same type to which the output can be safely
connected. The larger Fan-out of a gate can cause the
signal propagation delays in the digital circuits.
Reversible Gates or Quantum Gates are restricted for the
larger fan-out. This is the reason why the Reversible
Gates has less propagation delay. Also one more
advantage is that the Power consumption can also be
minimized because of the less Gate Count used to
implement any digital circuit.
B. Reversible Circuits
To implement reversible computation, estimate its cost,
and to judge its limits, it is formalized it in terms of
gate-level circuits. For example, the inverter (logic
gate) (NOT) gate is reversible because it can be undone.
The exclusive or (XOR) gate is irreversible because its
inputs cannot be unambiguously reconstructed from an
output value. However, a reversible version of the XOR
gate the controlled NOT gate (CNOT) can be defined by
preserving one of the inputs. The three-input variant of
the CNOT gate is called the Toffoli gate. It preserves
two of its inputs a, b and replaces the third c by c xr
(a.b). With c=0, this gives the AND function, and with a.
b =1 this gives the NOT function. Thus, the Toffoli gate
is universal and can implement any reversible Boolean
function (given enough zero-initialized ancillary bits).
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International Journal of Advanced Computer Engineering and Communication Technology (IJACECT)
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More generally, reversible gates have the same number
of inputs and outputs. A reversible circuit connects
reversible gates without fan-outs and loops. Therefore,
such circuits contain equal numbers of input and output
wires, each going through an entire circuit. Reversible
logic circuits have been first motivated in the 1960s by
theoretical considerations of zero-energy computation as
well
as
practical
improvement
of bit
manipulation transforms in cryptography and computer
graphics. Since the 1980s, reversible circuits have
attracted interest as components of quantum algorithms,
and more recently in photonic and nano-computing
technologies where some switching devices offer
no signal gain.
C. Quantum Computation
A quantum computer (also known as a quantum
supercomputer) is a computation device that makes
direct use of quantum-mechanical phenomena, such as
superposition and entanglement, to perform operations
on data. Quantum computers are different from digital
computers based on transistors. Whereas digital
computers require data to be encoded into binary digits
(bits), quantum computation uses quantum properties to
represent data and perform operations on these data. A
theoretical model is the quantum Turing machine, also
known as the universal quantum computer. Quantum
computers share theoretical similarities with nondeterministic and probabilistic computers. One example
is the ability to be in more than one state simultaneously.
The field of quantum computing was first introduced by
Yuri Manin in 1980 and Richard Feynman in 1982. A
quantum computer with spins as quantum bits was also
formulated for use as a quantum space–time in 1969.
As of 2014 quantum computing is still in its infancy but
experiments have been carried out in which quantum
computational operations were executed on a very small
number of qubits (quantum bits). Both practical and
theoretical research continues, and many national
governments and military funding agencies support
quantum computing research to develop quantum
computers for both civilian and national security
purposes, such as cryptanalysis. In quantum computing
and specifically the quantum circuit model of
computation, a quantum gate (or quantum logic gate) is
a basic quantum circuit operating on a small number of
qubits. They are the building blocks of quantum circuits,
like classical logic gates are for conventional digital
circuits.
Fig 1. Operation Using Qubits
Garbage output is some of the inputs that are not used
for further computations (Thapliyal Himanshu,2005).
Constant input is some of the inputs that are added to an
nxk function. It cause to make the circuits as reversible
state (Saiful Islam, 2005). A circuit with flip-flops is
considered a sequential circuit even in the absence of
combinational logic. Circuits that include flip-flops are
usually classified by the function of them. Comparison
between Reversible Gates & Conventional Gates is
given below.
Fig 2. Conventional Logic Gate Vs Reversible Logic
Gate
E. Feynman gate (FG)
Feynman gate also known as controlled-not gate (1CNOT). It is a 2×2 reversible gate that can be explained
by the equations: P = A and Q = AxrB, 'A' is a control
bit and 'B' is the data bit. If control input bit is "1", the
output bit (Q) is NOT of B; otherwise, it is B. If the B
input be "0" then the output bits (P, Q) are equal to A.
that is the Feynman gate can be used to copy a input bit.
However, we can use the Feynman gate for copy a
signal. In fact, it is a fan-out gate. Quantum cost of its
circuit is 1. The Feynman gate can be presented as:
Iv = (A, B)
D. Qubits
Ov= (P = A, Q = AxrB)
Qubits are made up of controlled particles and the
means of control (e.g. devices that trap particles and
switch them from one state to another.
Iv and Ov are input and output vectors respectively.
The Feynman gate is a 2*2 reversible gate with
Quantum Cost of one having mapping input (A, B) to
output (P = A, Q = AxrB) is as shown in the Figure
below.
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International Journal of Advanced Computer Engineering and Communication Technology (IJACECT)
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Iv = (A, B, C)
Ov= (P = A, Q = A'BxrAC, R = A'CxrAB)
Iv and Ov are input and output vectors respectively.
Conservator property is one of the Fredkin gate
characteristic. Its input vector has the hamming weight
that is equal to hamming weight of its output vector.
Reversible 3*3 gate maps inputs (A, B, C) to outputs
(P=A, Q=A'B+AC, R=AB+A'C) having Quantum cost
of 5 and it requires two dotted rectangles, is equivalent
to a 2*2 Feynman gate with Quantum cost of each
dotted rectangle is 1, 1 V and 2 CNOT gates. Fredkin
gate and its Quantum implementations are shown in
Figures below.
Fig 3. Feynman gate & Its truth table
F. Peres gate (PG)
Fig 6. Fredkin gate
.
Peres gate also known as New Toffoli Gate (NTG). It is
constructed of Toffoli Gate and Feynman Gate. The
Peres gate is also a 3×3 reversible gate. It is equal to the
produced evolution by a Toffoli gate followed by a
Feynman gate. The Peres gate is also universal gate. It is
more sophisticated than the Toffoli gate. Its quantum
cost is 4 that is less than quantum cost of the Toffoli
gate. This gate can be used in synthesis of all reversible
circuits. The Peres gate can be described as follows.
Iv= (A, B, C)
Ov= (P = A, Q = AxrB, R = ABxrC)
Iv and Ov are input and output vectors orderly.The
three inputs and three outputs i.e., 3*3 reversible gate
having inputs (A, B, C) mapping to outputs (P = A, Q =
AxrB, R = (A.B) xr C). Since it requires 2 V+, 1 V and 1
CNOT gate, it has the Quantum cost of 4. The Peres gate
and is as shown in the figure below.
Fig 4. Peres gate
The Quantum implementation of Peres gate is as shown
in figure below.
Table 1. Truth table for Fredkin gate.
H. Quantum Cost
The Quantum Cost of a Reversible gate is calculated by
counting the number of V, V+ and CNOT gates.
I. D Flip Flop
The reversible D Flip Flop consists of one Fredkin gate
plus one Feynman gate which is later used to design the
complex sequential circuits. It is a reversible MasterSlave D Flip Flop (Lukac, 2003). The D Flip Flop gate
is shown in Fig..
Fig 5. Quantum implementation of Peres gate
G. Fredkin gate (FRG)
Fredkin gate also known as controlled permutation gate.
It is a 3×3 reversible gate that can be described by some
of the equations.It is a universal gate for circuit design
and is directly onto quantum logic gates. Quantum cost
of its circuit is 5. FRG can be implemented by other
gates.
Fig 7. D Flip flop
The characteristic equation of the D Flip Flop used one
Fredkin gate plus one Feynman gate. The Feynman gate
is used to copy the output bit. It has highly optimized in
the number of reversible gates, constant inputs and
garbage outputs. CP refers to the clock pulse. It can be
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International Journal of Advanced Computer Engineering and Communication Technology (IJACECT)
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easily verified that the constructions meets the desired
characteristics of the positive edge triggered D Flip
Flop. The feedback connection from output to input is
necessary because the D Flip Flop does not have a “No
Change” condition. The construction of the D Flip Flop
is shown in Figure below. Quantum cost (QC) of the
D Flip Flop circuit is asC (D-FF)
=
QC (FRG)
+
QC (FG) = 5 + 1 = 6
Fig.(b) 4-Bit Counter Using the Clear Input
K. Proposed reversible circuit
Fig 8. Reversible Master-Slave D Flip-Flop.
J. Binary Counting
The construction and operations of a 4-Bit binary
counter with parallel load is shown in Fig.3.1.The
important reversible gates used for our reversible logic
synthesis are Feynman gate, Peres gate and Fredkin
gate.
To convert a binary number to a decimal, we use a
simple system. Each digit or ‘bit’ of the binary number
represents a power of two. All you need to do to convert
from binary to decimal is add up the applicable powers
of 2. In the example below, we find that the binary
number 10110111 is equal to 183.
Fig 9. Binary Counting
Counter is essentially a register that goes through a
predetermined sequence of states. The gates in the
counter are connected in such a way as to produce the
prescribed sequence of binary states. These gates
construct a counter circuit. A counter with parallel load
can be used to create any desired count sequence. A 4bit counter with parallel load can be used to generate a
BCD count in two ways -
Using the load input: Overview of this design is
shown in Fig.(a)

Using the clear input: Overview of this design is
shown in Fig.(b)
Fig.(a) 4-bit Counter using Load input
Fig. 10 Proposed 4-bit counter using Reversible Logic
It has minimum number of reversible gates, constant
inputs and garbage outputs. Our proposed circuit has
minimum value of the quantum cost.
The proposed reversible circuit has two sections. First,
the computing operations are performed on inputs or
feedback data. This section is constructed of the Peres
gates and the Feynman gates. Second, D Flip Flop stores
the entered data and then feedback them to the circuit
inputs.
We have implemented the computing operations using
Peres gate instead of the other gates because it cause to
our proposed circuit be optimal. The Peres gate has
some of the computation features with minimum
quantum cost. We have performed XOR, AND, OR
operations using Peres gates. in the second approach, we
have used D Flip Flop to stores the entered or
incremented data. In addition, it needs four Feynman
gates to copy the outputs data and feedback them to the
circuit inputs.
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International Journal of Advanced Computer Engineering and Communication Technology (IJACECT)
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III. RESULTS
A. Comparison of Reversible Counter Vs Basic
Counter
PARAMETER
COUNTER
(BASIC
GATES)
COUNTER
(REVERSIBLE
GATES)
Reduction
POWER
455mW
335mW
73.62
DELAY
20.1932ns
5.247ns
25.98
4 I/P LUTs
8 out of
4896 - 1%
1 out of
4896 - 0%
12.5
BONDED
IOBs
13 out of
172 - 7%
5 out of
172 - 2%
38.46
No. OF
SLICES
4 out of
3584 - 1%
1 out of
2448 - 0%
25
%
From above discussion, we can summarize the
mentioned reversible circuit is the first attempt and
optimal state for a 4-Bit binary counter with parallel
load. Reversible logic is used for low power
computation and used for nano-scale and high speed
computation due to less gate count. So, these proposed
gates can be used for the design of large and complex
combinational and sequential circuits.
Some of the techniques to reduce the constant inputs and
garbage outputs might be possible. In addition, some
other optimization techniques like genetic algorithm
may be utilize to reduce the quantum cost of the circuit.
V. REFERENCES
Table 2. Comparison of Reversible Counter Vs Basic
Counter
B. Comparison between various Reversible Logic
Gate parameters
GATE NAME
POWER
CONSUMPTIO
N(MW)
DELA
Y
(NS)
INPU
TS
OUTPU
TS
TOFOLLI
24
6.236
3
3
FREDKIN
18
6.320
3
3
FEYNMAN
18
6.209
2
2
PERES
24
6.236
3
3
NEW
24
6.236
3
3
HNG
24
6.236
4
4
Table 3. Comparison of various Reversible Logic gate
parameters
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IV. CONCLUSION & FUTURE SCOPE
In this paper, we proposed a robust reversible circuit for
a 4-Bit binary counter with parallel load. The proposed
reversible circuit is the first attempt of designing the
mentioned counter. It has minimum complexity and
quantum cost considerably. Table 2 demonstrates that
the proposed reversible circuit is an efficient design in
terms of hardware complexity, constant inputs, garbage
outputs and number of gates. However, restrictions of
the reversible circuits were avoided in an excellent way.
More complex systems can be also developed using our
proposed approach.
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