Ari Mahpour
ECE 526
Homework #2
1. Code a Verilog module that will:
Output 1 if preset is low and reset is high
Output 0 if reset is low and preset is high
Output an X if both preset and reset are low
Toggle states on the clock rising edge if both preset and reset are high.
module question_one(OUTPUT, PRESET, RESET, CLOCK);
output OUTPUT;
input PRESET, RESET, CLOCK;
reg OUT;
reg TOGGLE;
//Sets the toggle state
always @(posedge CLOCK) begin
TOGGLE = ~OUTPUT;
end
always @(PRESET or RESET) begin
//Output 1 if preset is low and reset is high
if (!PRESET || RESET)
OUTPUT = 1’b1;
//Output 0 if reset is low and preset is high
else if (!RESET && PRESET)
OUTPUT = 1’b1;
//Output an X if both preset and reset are low
else if (!RESET && !PRESET)
OUTPUT = 1’bx;
// Toggle states on the clock rising edge if both preset and reset are high.
else if (RESET && RESET)
OUTPUT = TOGGLE;
else
//Do nothing
end
endmodule
Ari Mahpour
ECE 526
2a. Using structural Verilog and gate-level operators, write a Verilog module to implement a
two-bit magnitude comparator. This comparator should have three active-high outputs: one for
equal, one for A > B and one for B > A.
module comparator_primitive(EQUALTO, GREATERTHAN, LESSTHAN, A, B)
output EQUALTO, GREATERTHAN, LESSTHAN;
input [1:0] A, B;
wire OR_OUTPUT, EQUAL;
wire [1:0] A_BAR, OR;
wire [3:0} NAND_OUTPUT
not (A_BAR[0], A[0]);
not (A_BAR[1], A[1]);
xor (OR[0], A[0], B[0]);
xor (OR[1], A[1], B[1]);
or (OR_OUTPUT, OR[0], OR[1]);
not (EQUAL, OR_OUTPUT);
nand (NAND_OUTPUT[0], A_BAR[1], B[1]);
nand (NAND_OUTPUT[1], A_BAR[0], A_BAR[1], OR_OUTPUT);
nand (NAND_OUTPUT[2], B[0]; B[1]; OR_OUTPUT);
nand (NAND_OUTPUT[3], NAND_OUTPUT[0], NAND_OUTPUT[1], NAND_OUTPUT[2]);
buf (EQUALTO, EQUAL);
buf (LESSTHAN, NAND_OUTPUT[3]);
nor (GREATERTHAN, EQUAL, NAND_OUTPUT[3]);
endmodule
Ari Mahpour
ECE 526
2b. Implement the same function in behavioral Verilog.
Module comparator_behavioral(EQUALTO, GREATERTHAN, LESSTHAN, A, B)
output EQUALTO, GREATERTHAN, LESSTHAN;
input [1:0] A, B;
always @(A or B) begin
if (A == B) begin
EQUALTO = 1’b1;
GREATERTHAN = 1’b0;
LESSTHAN = 1’b0;
end
else if (A > B) begin
EQUALTO = 1’b0;
GREATERTHAN = 1’b1;
LESSTHAN = 1’b0;
end
else if (A < B) begin
EQUALTO = 1’b0;
GREATERTHAN = 1’b0;
LESSTHAN = 1’b1;
end
end
endmodule
Ari Mahpour
3. Sketch the hardware that would result from synthesizing this code:
module homework(MY_OUT, IN1, IN2, CLK);
output [3:0] MY_OUT;
input [3:0] IN1, IN2;
input CLK;
reg [3:0] MY_OUT;
reg [3:0] TEMP;
always @(posedge CLK) begin
TEMP = IN1 + IN2;
MY_OUT = TEMP + IN1;
end
endmodule
Make your sketch at a high level of abstraction, that is, using registers and arithmetic
operators rather than Boolean gates.
ECE 526