vedic and reversible architectures
advertisement
S3 INFOTECH +919884848198 VLSI Titles for ME & M.Tech, VEDIC AND REVERSIBLE ARCHITECTURES: PROJECT CODE EPVVR-001 NAME OF THE PROJECTS Low power Square and Cube Architectures Using Vedic Sutras IEEE 2014 EPVVR-002 High Speed Vedic Multiplier Designs IEEE 2014 EPVVR-003 Binary Division Power Models for High-Level Power Estimation of FPGABased DSP Circuits IEEE 2014 EPVVR-004 Design of Dedicated Reversible Quantum Circuitry for Square Computation IEEE 2014 EPVVR-005 ASIC Design of Reversible Multiplier Circuit IEEE 2014 EPVVR-006 All Optical Reversible Multiplexer Design using Mach-Zehnder Interferometer IEEE 2014 EPVVR-007 Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing IEEE 2014 Ancilla and Garbage Bits EPVVR-008 Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata IEEE 2014 EPVVR-009 Eliminating Synchronization Latency Using Sequenced Latching IEEE 2014 EPVVR-010 Area-Delay Efficient Binary Adders in QCA IEEE 2014 EPVVR-011 Design and Performance Analysis of Reversible Logic based ALU using Hybrid Single Electron Transistor IEEE 2014 # 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198. www.s3computers.com E-Mail: info@s3computers.com YEAR S3 INFOTECH +919884848198 EPVVR-012 Synthesis of ESOP-based Reversible Logic using Negative Polarity ReedMuller Form IEEE 2014 EPVVR-013 An Optimized Design of Reversible Quantum Comparator IEEE 2014 EPVVR-014 Approach to design a compact reversible low power binary comparator IEEE 2014 EPVVR-015 Realization of 2:4 reversible decoder and its applications IEEE 2014 EPVVR-016 Novel High Speed Vedic Mathematics Multiplier using Compressors IEEE 2013 EPVVR-017 Performance Evaluation of FFT Processor Using Conventional and Vedic Algorithm IEEE 2013 EPVVR-018 Design a DSP Operations using Vedic Mathematics IEEE 2013 EPVVR-019 Design of High Speed Low Power Multiplier using Reversible logic: a Vedic IEEE 2013 Mathematical Approach Optimized Reversible Vedic Multipliers for High Speed Low Power Operations IEEE 2013 EPVVR-020 EPVVR-021 Design of Low Logical Cost Adders using Novel Parity Conserving Toffoli Gate IEEE 2013 EPVVR-022 Design of Testable Reversible Sequential Circuits IEEE 2013 EPVVR-023 Reversible Logic Synthesis of k-Input, m-Output Lookup Tables IEEE 2013 EPVVR-024 Analysis and Improvement of Transformation-based Reversible Logic Synthesis IEEE 2013 EPVVR-025 Reversible Logic Implementation of AES Algorithm IEEE 2013 EPVVR-026 Energy Efficient Code Converters using Reversible Logic Gates IEEE 2013 EPVVR-027 Efficient Approaches to Design a Reversible Floating Point Divider IEEE 2013 EPVVR-028 Parity Preserving Logic based Fault Tolerant Reversible ALU IEEE 2013 EPVVR-029 Design of Low Power Comparator Circuit Based on Reversible Logic Technology IEEE 2013 EPVVR-030 An Optimal Design of a Fault Tolerant Reversible Multiplier IEEE 2013 # 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198. www.s3computers.com E-Mail: info@s3computers.com S3 INFOTECH +919884848198 EPVVR-031 Behavioral Model of Integrated Qubit Gates for Quantum Reversible Logic Design IEEE 2013 EPVVR-032 A Novel Optimization Method for Reversible Logic Circuit Minimization IEEE 2013 EPVVR-033 Optimized Power Performance and Simulation of Reversible Logic Multiplexer IEEE 2013 EPVVR-034 Design and Implementation of Fast FPGA Based Architecture for Reversible Watermarking IEEE 2013 EPVVR-035 Cycle based Reversible Logic Synthesis Approach IEEE 2013 EPVVR-036 Contemplation of Synchronous Gray Code Counter and its Variants using Reversible Logic Gates IEEE 2013 EPVVR-037 An Evolutionary Approach to Reversible Logic Synthesis using Output Permutation IEEE 2013 EPVVR-038 Design and Implementation of Logical Cost Efficient Nanometric Fault Tolerant Reversible BCD Adder IEEE 2013 EPVVR-039 Optical logic circuits using double controlled logic gate IEEE 2013 EPVVR-040 High Performance Vedic BCD Multiplier and Modified Binary to BCD Converter IEEE 2013 EPVVR-041 Vedic Divider - A High Performance Computing algorithm for VLSI Applications IEEE 2013 EPVVR-042 Reciprocal unit based on Vedic mathematics for signal processing applications IEEE 2013 EPVVR-043 Design And FPGA Implementation Of Binary Squarer Using Vedic Mathematics IEEE 2013 # 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198. www.s3computers.com E-Mail: info@s3computers.com S3 INFOTECH +919884848198 REAL TIME SIMULATION: PROJECT NAME OF THE PROJECTS CODE EPVRT-001 Simulation of energy efficient Bi-directional Visitor Counting Machine on FPGA YEAR IEEE 2014 EPVRT-002 Using FPGA to Control a Virtual Sorting System IEEE 2014 EPVRT-003 FPGA Implementation of Advanced Health Care system using Zig-Bee enabled RFID Technology IEEE 2014 EPVRT-004 FPGA-Based Design of Grid Friendly Appliance Controller IEEE 2014 EPVRT-005 Embedded System for Home Automation Using SMS IEEE 2014 EPVRT-006 Design of an Academic Microcontroller and its Application to Authenticated Encryption IEEE 2014 EPVRT-007 Mapping Complex Algorithm into FPGA with High Level Synthesis Reconfigurable chips with High Level Synthesis compared with CPU, GPGPU IEEE 2014 SIGNAL PROCESSING APPLICATION: PROJECT CODE EPVSP-001 NAME OF THE PROJECTS YEAR FPGA based Partial Reconfigurable FIR Filter Design IEEE 2014 EPVSP-002 FPGA Based Implementation of High Speed Tunable Notch Filter Using Pipelining and Unfolding IEEE 2014 EPVSP-003 Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology IEEE 2014 EPVSP-004 High Speed Multiplier for FIR Filter Design using Window IEEE 2014 EPVSP-005 Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation IEEE 2014 # 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198. www.s3computers.com E-Mail: info@s3computers.com S3 INFOTECH +919884848198 EPVSP-006 Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems IEEE 2014 EPVSP-007 Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count IEEE 2014 EPVSP-008 Scalable low power FFT/IFFT architecture with dynamic bit width configurability IEEE 2014 EPVSP-009 A Power Efficient Video Encoder using Reconfigurable Approximate Arithmetic Units IEEE 2014 EPVSP-010 Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters IEEE 2014 EPVSP-011 Scaled Radix-2/8 Algorithm for Efficient Computation of Length-N=2m DFTs IEEE 2014 EPVSP-012 FPGA Based Implementation & Power Analysis of Parameterized Walsh Sequences IEEE 2014 EPVSP-013 Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions IEEE 2014 EPVSP-014 An Efficient Hardware Based MAC Design in Digital Filters with Complex Numbers IEEE 2014 EPVSP-015 Razor Based Programmable Truncated Multiply and Accumulate, EnergyReduction for Efficient Digital Signal Processing IEEE 2014 EPVSP-016 Design and Implementation of an MSI number based Image Watermarking Architecture in Transform Domain High throughput pipelined 2D Discrete cosine transform for video compression IEEE 2014 EPVSP-018 Efficient FPGA and ASIC Realizations of DA-Based Reconfigurable FIR Digital Filter IEEE 2014 EPVSP-019 A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT IEEE 2014 EPVSP-020 Power Evaluation of Sobel Filter on Xilinx Platform IEEE 2014 EPVSP-021 Improved matrix multiplier design for high-speed digital signal processing applications IEEE 2014 EPVSP-017 # 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198. www.s3computers.com E-Mail: info@s3computers.com IEEE 2014 S3 INFOTECH +919884848198 EPVSP-022 Embedded Complex Floating Point Hardware Accelerator IEEE 2014 EPVSP-023 An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC IEEE 2014 EPVSP-024 Area Efficient High Speed Low Power Multiplier Architecture For Multirate Filter Design IEEE 2013 EPVSP-025 The Implementation of FIR Low-pass Filter Based on FPGA and DA IEEE 2013 EPVSP-026 Design and Implementation of a 1024-point High-speed FFT Processor Based on the FPGA IEEE 2013 EPVSP-027 Processor Arrays Generation for Matrix Algorithms Used in Embedded Platforms IEEE 2013 EPVSP-028 MIN-MAX: A Counter-Based Algorithm for Regular Expression Matching IEEE 2013 EPVSP-029 Multiplier-less VLSI Architecture of 1-D Hilbert Transform pair using Biorthogonal Wavelets IEEE 2013 EPVSP-030 Design of Optimized CIC Decimator and Interpolator in FPGA IEEE 2013 EPVSP-031 FPGA based Architectures for High Performance Adaptive FIR Filter Systems IEEE 2013 EPVSP-032 An Efficient Implementation of Synthesis Filter Bank and Digital Spectrum Processing on Xilinx Virtex-5 FPGA for Onboard Transparent Processor IEEE 2013 EPVSP-033 Design and FPGA Implementation of an 2D Gaussian Surround Function with Reduced On-Chip Memory Utilization IEEE 2013 EPVSP-034 Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation IEEE 2013 EPVSP-035 Low Power Multiply Accumulate Unit (MAC) for Future Wireless Sensor Networks IEEE 2013 EPVSP-036 VLSI Architecture of Multiplierless DWT Image Processor IEEE 2013 EPVSP-037 High performance and low-power finite impulse response filter based on ring topology with modified retiming serial multiplier on FPGA IEEE 2013 # 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198. www.s3computers.com E-Mail: info@s3computers.com S3 INFOTECH +919884848198 EPVSP-038 An FPGA Based Low Power Multiplier for FFT in OFDM Systems Using Precomputations IEEE 2013 EPVSP-039 New Approximate Multiplier for Low Power Digital Signal Processing IEEE 2013 ARCHITECTURE: PROJECT CODE EPVAR-001 NAME OF THE PROJECTS YEAR Design of a Low-Error Fixed-Width Radix-8 Booth Multiplier IEEE 2014 EPVAR-002 Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits IEEE 2014 EPVAR-003 Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating IEEE 2014 EPVAR-004 Power- and Area-Efficient Approximate Wallace Tree Multiplier for ErrorResilient Systems IEEE 2014 EPVAR-005 A Novel Parallel Multiplier for 2’s Complement Numbers Using Booth’s Recoding Algorithm IEEE 2014 EPVAR-006 4-2 Compressor Design with New XOR-XNOR Module IEEE 2014 EPVAR-007 Design and Estimation of delay, power and area for Parallel prefix adders IEEE 2014 EPVAR-008 Fast Radix-10 Multiplication Using Redundant BCD Codes IEEE 2014 EPVAR-009 CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities IEEE 2014 EPVAR-010 A New Design of Low Power High speed CMOS Full Adder IEEE 2014 EPVAR-011 Improved design of high-frequency sequential decimal multipliers IEEE 2014 EPVAR-012 A Decimal / Binary Multi-operand Adder using a Fast Binary to Decimal Converter IEEE 2014 # 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198. www.s3computers.com E-Mail: info@s3computers.com S3 INFOTECH +919884848198 EPVAR-013 Shift Register Design Using Two Bit Flip-Flop IEEE 2014 EPVAR-014 Implementation Of Floating Point Mac Using Residue Number System IEEE 2014 EPVAR-015 Design and Implementation of a BIST Embedded Inter Integrated Circuit Bus Protocol over FPGA IEEE 2014 EPVAR-016 Data Encoding Techniques for Reducing Energy Consumption in Network-onChip IEEE 2014 EPVAR-017 Color Pass: An Intelligent User Interface to Resist Shoulder Surfing Attack IEEE 2014 EPVAR-018 On-Chip Codeword Generation to Cope With Crosstalk IEEE 2014 EPVAR-019 Multifunction Residue Architectures for Cryptography IEEE 2014 EPVAR-020 Low-Latency, Low- Area Overhead and High Throughput NoC Architecture for FPGA Based Computing System IEEE 2014 EPVAR-021 Dual-Basis Super-serial Multipliers for Secure Applications and Lightweight Cryptographic Architectures IEEE 2014 EPVAR-022 Mapping Loop Structures onto Parametrized Hardware Pipelines IEEE 2014 EPVAR-023 Universal Set of CMOS Gates for the Synthesis of Multiple Valued Logic Digital Circuits IEEE 2014 EPVAR-024 An Optimized Modified Booth Re-coder for Efficient Design of the AddMultiply Operator IEEE 2014 EPVAR-025 32 Bit×32 Bit Multi-precision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler IEEE 2014 EPVAR-026 Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations IEEE 2014 EPVAR-027 HDL Based Implementation of NxN Bit-Serial Multiplier IEEE 2014 EPVAR-028 Multiplication Acceleration Through Quarter Precision Wallace Tree Multiplier IEEE 2014 EPVAR-029 Design and Implementation of Modified Signed-Digit Adder # 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198. www.s3computers.com E-Mail: info@s3computers.com IEEE 2014 S3 INFOTECH +919884848198 EPVAR-030 Comments on “Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding” IEEE 2014 EPVAR-031 Formal Verification and Debugging of Array Dividers With Auto-Correction Mechanism IEEE 2014 EPVAR-032 Power-Delay Optimized 32 Bit Radix-4, Sparse-4 Prefix Adder IEEE 2014 EPVAR-033 Design and Estimation of delay, power and area for Parallel prefix adders IEEE 2014 EPVAR-034 Area–Delay–Power Efficient Carry-Select Adder IEEE 2014 EPVAR-035 Hardware Acceleration with Pipelined Adder for Support Vector Machine Classifier IEEE 2014 EPVAR-036 Reviewing High-Radix Signed-Digit Adders IEEE 2014 EPVAR-037 EPVAR-038 High-Performance 64-Bit Binary Comparator VLSI Design of Parallel Sorter based on Modified PCM Algorithm and Batcher’s Odd-Even Mergesort IEEE 2014 IEEE 2013 EPVAR-039 A Space/Time Tradeoff Methodology Using Higher-Order Function IEEE 2013 EPVAR-040 An Improved Design of Combinational Digital Circuits with Multiplexers using IEEE 2013 Genetic Algorithm EPVAR-041 ACMA: Accuracy-Configurable Multiplier Architecture for Error-Resilient System-on-Chip EPVAR-042 Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip- IEEE 2013 Flops EPVAR-043 Multioperand Redundant Adders on FPGAs IEEE 2013 EPVAR-044 Approximate XOR/XNOR-based Adders for Inexact Computing IEEE 2013 EPVAR-045 Multipliers using low power adder cells using 180nm Technology IEEE 2013 EPVAR-046 The Optimum Booth Radix for Low Power Integer Multipliers IEEE 2013 EPVAR-047 Multiple Constant Multiplication with Ternary Adders IEEE 2013 # 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198. www.s3computers.com E-Mail: info@s3computers.com IEEE 2013 S3 INFOTECH +919884848198 EPVAR-048 Hardware Implementation of Truncated Multiplier Based on Multiplexer Using FPGA IEEE 2013 EPVAR-049 Low Power Self-Timed Carry Lookahead Adders IEEE 2013 EPVAR-050 Comparative analysis for Hardware Circuit architecture of Wallace tree Multiplier IEEE 2013 EPVAR-051 Implementation Of High Speed And Low Power Hybrid Adder Based Novel Radix 4 Booth Multiplier IEEE 2013 # 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198. www.s3computers.com E-Mail: info@s3computers.com
