Multi-Channel Coincidence Unit
v3
User’s Manual
Institute of Experimental and Applied Physics
Petr Mašek
Description
Multi-channel Coincidence Unit is universal device designated for coincidence measurements and
synchronization needs. The Unit has signal inputs with inhibiting feature. Outputs are dependent on
mode of operation. Time-to-digital converter (TDC) is implemented for measurement of time distance
of input signal arrival. TDC data can be read through USB or discarded when not needed or when
reduction of dead time preferred.
Up to eight inputs could be used. Each o them can be temporarily inhibited by busy signal. Eight reset
signals and eight trigger signals are configurable through the settings and can be used independently
on employed inputs. Both input and output signals can be delayed. Input delay allows to compensate
external delay caused by setup or cabling. Output delay can postpone the output signal. Auxiliary
inputs and outputs, each per three independent paths, are used for interfacing internal signals.
Configuration setting adapts the Unit according to the particular needs. After power-up, configuration
is loaded from internal EEPROM if stored, so the Unit can work as a standalone device without need
of initial configuration through the computer. Without view of that fact, configuration can be changed
anytime through PC and eventually updated in the EEPROM for further use.
Internal signal generator with variable period can replace input signal for testing needs.
Controls and operation
The Unit is provided in two forms – assembled board with header connections or board supplemented
by BNC adapter mounted in plastic box. The adapter has no impact on signal definition and
parameters except additional delay between BNC connector and internal electronics.
Picture 1: The Unit with header connections covered by plexi glass.
Picture 2: The Unit in plastic box supplemented by BNC adapter.
Input: The Input signal is logic signal which is to be investigated. The Input can be sensitive on rising
or falling edge and high or low level. Its internal processing is postponed by adjustable delay. Internal
termination of 50Ω is offered. Logic level is weakly set when signal enabled and nothing is connected
so the Input is always defined as inactive. Input can be enabled or disabled. When enabled, it can be in
coincidence or anticoincidence or even ignored for coincidence condition (check Theory of operation
for more information).
Busy: The Busy signal is a logic signal which can temporarily inhibit Input signal. For safe function,
active level of Busy signal has to arrive at least 5 ns before Input. Active level of Busy signal can be
chosen as high or low.
Reset: The Reset signal is available at the end of coincidence window or postponed by delay. Busy
signal can postpone it too until active level of Busy ends. Behavior of Reset signal can be different for
valid and invalid coincidence condition fulfillment. Polarity and length of Reset signal is variable.
Response by Busy signal can be enforced so the Unit is blocked until response arrives.
Trigger: The Trigger signal is available at the end of coincidence window or postponed by delay only
when the coincidence condition is fulfilled. Polarity and length of Trigger signal is variable. Response
by Busy signal can be enforced so the Unit is blocked until response arrives.
Aux output: This signal is multi-purpose output with variable source which can be chosen in settings.
For instance, signal of coincidence window or system busy.
Aux input: This signal is multi-purpose input with variable usage. Influenced features can be chosen
in settings.
LED lights: LED lights indicate current status of the Unit.
Power-On (green):
Light is turned on when the Unit is supplied properly.
High Drive (red):
Light is turned on when high-current output drivers are used.
Measure (green):
Light is turned on while measurement in progress.
Coincidence (yellow): Light blinks when coincidence window starts. Higher blinking up to
constant light signalizes higher rate.
Conf/Valid (red):
While the Unit is idle, this light is on if the Unit is properly
configured. During measurement, light blinks when coincidence
condition fulfilled. Higher blinking up to constant light signalizes
higher rate.
PLL (red):
Light is turned on when internal PLL is locked. When the light is off
while the Unit is measuring, operation and results will be invalid and
the Unit should be checked.
Power input: The plug for power supply adapter.
USB connector: Configuration and data transfer between PC and the Unit.
Input/output specification
The unit is powered by external adapter with direct voltage output in range from =5 V (recommended)
to =12 V. At least 1 A adapter recommended.
Inputs are strictly digital, working in CMOS 3.3 V standard. Threshold level about 2.2 V (defined by
FPGA manufacturer). Signal and busy inputs can be terminated to ground by 50 Ω while chosen in
configuration settings otherwise are weakly pull-downed/-uped to inactive state by 33 kΩ. Auxiliary
inputs are terminated by 1 kΩ. All inputs are ESD protected. Clamping diodes protect inputs against
overvoltage and undervoltage with current strength of 100 mA. Exceeding the value could have fatal
impact on the electronics. No series resistor implemented.
Outputs are strictly digital, working in CMOS 3.3 V standard. Output strength is version dependent
and is visualized by LED (check Controls and operation – LED lights). Typically 25 mA is provided
so minimum load is 132 Ω at 3.3 V. Extended drive capability increases output current over 1 A. This
configuration allows 50 Ω load. The limiting value is supply current provided by source which needs
to be able to supply the total current from all outputs. Drive capability influences rising and falling
edges of the output signal, as shown in Table 1 and following pictures. Outputs are ESD protected.
Short circuit protection is not guaranteed.
Table 1: Time parameters of signal edges.
Picture 3: Time waveforms of output signals (low driving strength). Measured by 10MΩ+12pF probe
(left picture). When terminated by 270Ω+150pF (right picture).
Picture 4: Time waveforms of output signals (high driving strength). Measured by 10MΩ+12pF
probe. Rising edge (left picture) and falling edge (right picture).
It is obvious that driving strength limits signals despite of settings. Furthermore, cable connection and
proper termination influences the system. It is recommended not to use lower time values than 50 ns
when signals are led out outside of the system. Time parameters and Coincidence unit integration has
to be always tested directly in the application.
Theory of operation
Picture 5 below schematically shows the simplified internal structure.
Picture 5: Schematic structure of the Unit.
Input and Busy signals lead to Channel n block. If the Input is enabled, not blocked by Busy signal and
valid state met (edge or level), internal delay (16-bit value) starts to count down. After the delay pass
away, internal signal is generated and divided into two branches leading to Start block and TDC n
block. First signal getting to Start block kicks off a coincidence window (16-bit value). The
coincidence window enables counter (16-bit value) in TDC n block which is stopped by output signal
from Channel n block. At the end of the coincidence window incoming signals are evaluated in Coinc
matrix block. A vector of incoming signals is compared to a required vector. The required vector can
be changed by user in the PC application. Three different possibilities are provided for each channel. It
can be used in coincidence, anticoincidence or ignored. If the channel considered as ignored but it is
enabled, input signal is processed, starts the coincidence window but does not influence anyhow the
result of coincidence condition. Examples of coincidence settings with resulting values for two
channels are shown in Table 2.
Table 2: Examples of possible setting for two channels of the Unit.
At the end of the coincidence window resulting signal from Coinc matrix block is evaluated. Further
processing is dependent on whether the coincidence condition was or wasn’t met.
ResOut n block generates Reset signal at the end of coincidence window when the output enabled.
Reset signal can wait on Busy signal before or after so synchronization with external device is
guaranteed. Signal can be internally postponed (16-bit value). The length of the signal is variable (8-
bit value). TrigOut n block works equally to the ResOut n block with the only one difference – Trigger
signal is generated only when the coincidence condition met.
The response to Reset and Trigger signals is optional. If used, timeout can be set and missing response
is indicated in transferred data packet.
The design works with frequency 250 MHz, i.e. 4ns. Absolute time values can be calculated as a
product of multiplication of the range and the period.
Rough timestamp is provided by 40 MHz counter. It can help to synchronize events with external
devices. Counter can be cleared by software or by external signal.
Internal pulse generator is used for testing purposes. It can replace any of Input signals so the whole
setup can be tuned for proper response in real experiment without signals from detector. The period of
internal generator can be widely changed.
Dead time
The dead time of the Unit consists of few parts which will be discussed. Fixed values are stated
otherwise can be influenced by user. The first component of the resulting dead time is input signal
synchronization and evaluation (20 ns) and internal delay of input signal. The internal delay is
implemented as a counter which is fired by input signal. After the delay, internal signal is passed on in
the logical structure. Pulses incoming while the counter is counting are ignored. Next significant part
of the dead time is length of the coincidence window. Output signals (both Resets and Triggers)
contribute to the dead time by the amount of time equal to the longest one. The response of the
external system by busy signal if required needs to be added too. Optional part of the dead time is
caused by TDC data transfer (200 μs). This part is in parallel to output signals and response dead time.
The equation of the total dead time is shown for estimation.
τdead = τsynceval + τdelay + τwindow + max((τoutprep + τoutput); τdatatransfer)
τdead
τsynceval
τdelay
τwindow
τoutprep
τoutput
τdatatransfer
…total dead time
…input signal synchronization and evaluation (~20 ns)
…input signal delay
…coincidence window length
…output signal preparation (~8 ns)
…output puls duration
…TDC data transfer (200 μs)
Example: The minimum dead time of the system with 10 ns coincidence window and the shortest
output signal of 4 ns is theoretically 42 ns. Further delay is caused by processing of real signals,
particularly when high drive buffers are used. More information is in next chapter.
Propagation delay
Reaction time from Input signal to outputs is limited by the system as described in chapter Dead time.
Following pictures illustrates the operation with high drive buffers. The Unit starts when falling edge
of Input signal (green) met. After synchronization and evaluation, a coincidence window (red) is
generated. Attention should be paid to the length of the window when signal is to be used outside of
the system. The difference can be seen between Pictures 6 with 12 ns coincidence window, which
violates signal integrity, and Picture 7 with 100 ns coincidence window. Output signals, like Trigger
(blue) and Reset (yellow), are generated after coincidence window. High drive buffer delays have to be
taken into account. While internal signals start in same time, their high drive images do not.
Picture 6: Example of operation. Green signal is Input. Red signal is coincidence window (12 ns).
Yellow and blue signals are Reset and Trigger respectively starting in same time with length of 60 ns.
Picture 7: Example of operation. Green signal is Input. Red signal is coincidence window (100 ns).
Yellow and blue signals are Reset and Trigger respectively starting in same time with length of 60 ns.
Getting started
Software tool is designed for Windows platform. After connecting to PC, drivers are required. If
drivers are not installed automatically, manual installation has to be performed.
D2XX drivers from FTDI need to be found. Google search for “d2xx drivers ftdi” can be used.
Validity of direct link is not guaranteed.
http://www.ftdichip.com/Drivers/D2XX.htm
When the software is started the Unit is initialized.
Proper configuration is confirmed by disabling the choosing box and signed by messages in the Log,
correct values for register lengths (920 bits for configuration register and 320 bits for event register).
Configuration table appears.
Configuration can be loaded from (File – Open) or stored to (File – Save) file. Changes can be made
directly in configuration table (not recommended) or through configuration form (Edit – Graphical
Config).
Configuration can be read from EEPROM (Command – Read Memory). Before saving to memory
(Command – Store to Memory), the memory has to be erased (Command – Erase Memory).
Prepared configuration has to be loaded to hardware (Command – Configure).
During the measurement accepted data blocks are parsed and shown at the bottom of window. Data are
synchronized once per second so not all blocks can be shown. All data can be stored for offline
analysis. Incomplete operation is detected by timeout expiration. Log messages appear at the right.
The source of timeout is shown.
File format
Data can be stored in text file for further processing. Besides, data file with auto-generated name and
byte-to-byte record is generated for debugging (this feature can be disabled anytime).
Debug file
Byte-to-byte ASCII format, supplemented by total count of accepted bytes between delimiters
Data file – event is stored only when packet correctly parsed
Index (continuously incremented with overflow), timestamp , count8, count7,...count1 (number of
accepted pulses), hitmap (mask of detected inputs during coincidence window, MSb = channel 8, LSb
= channel 1), delay8, delay7,...delay1 (number of clock periods from beginning of coincidence
window to detection of valid event in the channel), computer timestamp