7.2.2. The Tuned Cascode Amplifier
A cascode circuit loaded with a parallel resonance circuit is shown in Fig. 7.16.
M1 and M2 are biased in the saturation region with VG1 and VG2. The load of M1 is the
input impedance of M2, operating as a common gate circuit.
We know
that
+VDD
C’
L
Cdg
Cc
Ci2
RS
+
vS
Reff
+
RG
ri2
vo
RS
+
vS
vi
Cgs
gmvgs
C
L
vo
+VG
Figure 7.13. (a) Schematic diagram of a tuned common source amplifier. (b) The small-signal equivalent
circuit. C represent the total capacitance ( the sum of the external capacitor C’, the output capacitance of
the transistor, the input capacitance of the following stage and the parasitics). Reff is the parallel equivalent
of the output resistance of the transistor, the input resistance of the following stage and the parallel
resistance corresponding the losses of the resonance circuit.
Av  
g m  sCdg
(5.2)
Yo
where Yo represents the total output load admittance, that is the parallel equivalent of C, L
and Reff for our circuit1:
g m  Cdg
Av  
(7.28)
1
sC   Geff
sL
To derive the variations of the magnitude and the phase of the gain with
frequency, it is possible to write (7.28) in the frequency domain, or to use the pole-zero
diagram of the gain function. We’ll prefer the second way:
(7.28) can be arranged in terms of its poles and zero as
1
It is obvious that for
0Cdg
g m , the voltage gain can be written as Av   g m / Y0   g m Z 0 .
Consequently the frequency characteristic and the –3dB frequencies of the amplifier are same as of the total
load impedance, Z0. Here a less straightforward approach will be used to enable to discuss the effects of the
“zero” of the gain function and to prepare the reader to the concepts that will be used to investigate the
stagerred tuning in Part 7-3.
Av 
s ( s  s0 )
C ( s  s p1 )( s  s p 2 )
Cdg
G
g
s0   m , s p1, p 2 =  eff
Cdg
2C
where
(7.29)
1  Geff 
j


LC  2C 
2
(7.30)
and with

Geff
2C

0
2Qeff
and
02 
1
LC
gm
(7.30-a)
, s p1, p 2 =   j 02   2
Cdg
The pole-zero diagram of the gain function is given in Fig. 7.14-a. For any ω value the
magnitude and phase of the gain can be obtained as
s0  
A
Cdg
s s  s0
(7.31)
C s  s p1 s  s p 2
  s  ( s s0 )  ( s s p1 )  ( s s p 2 )
(7.32)
jω
jω
sp1
( s  s p1 )
0
( s  s p1 )
ω
( s  s0 )
0 / 2Qeff
(s  s p 2 )
sp2
ω0
sp1
s
s0
Δω
σ
σ
0
Figure 7.14. (a) The pole-zero diagram of the gain function of a tuned amplifier,
(b) its simplified form for the vicinity of the resonance frequency (note that (s-sp1) is
drawn for the upper 3 dB frequency of the gain).
Provided that s0
0 and 0  , that are valid for most practical cases, for the
vicinity ω0 the magnitude and phase can be approximated as
A
Cdg

 s0
C s  s p1 20

2

    ( s  s p1 ) 
gm
2C s  s p1

2
(7.31-a)
    ( s  s p1 )
(7.32-a)
The simplified form of the pole-zero diagram of the amplifier corresponding to (7.31-a)
and (7.32-a), valid for and around of the resonance frequency is shown in Fig. 7.14-b.
From this figure the 3 dB frequencies and the band-width of the amplifier can be found as
f0
2Qeff
that are same as of a parallel resonance circuit.
f ( 3dB )  f0  f  f0 
, B  2f 
f0
Qeff
(7.33)
The magnitude of the gain corresponding to the resonance frequency can be
calculated from (7.31-a) with s  s p1    0 / 2Qeff
A(0 )  g m
Qeff
0C
 g m Reff
(7.34)
and similarly the phase angle for ω0
 0   
(7.35)
Along the calculations above we assumed that the zero of the voltage gain related
to the drain-gate capacitance is far away on the right half-plane and therefore negligible.
This assumption corresponds to 0Cdg g m , that is usually valid. Under this assumption
the voltage gain (2.28) can be written as
g
A( )   m   g m Z 0
(7.36)
Y0
where Z0 is the effective impedance of the parallel resonance circuit.
-------------------------Example 7.2.
Check the validity of the assumption of 0Cdg g m for a ST 0.13 micron NMOS
transistor operating in the velocity saturation regime. The operating frequency of the
amplifier is 3 GHz.
Under the velocity saturation, (that is the case for a 0.13 micron transistor as
shown in Part-1) the transconductance is g m ( v  sat )  kWCox vsat and the drain-gate
capacitance Cdg = W×CDGW. Therefore
0Cdg
gm

0  CDGW
Cox vsat
that is independent of the gate width. The related parameter values for the ST 0.13
micron technology are tox=2.3×10-9 [m] (that correspond to Cox = 15×10-3 f/m2), and
CDGW=5.18×10-10 [f/m]. The saturation velocity of electrons in the channel was given in
Part-1 as 6.5×104 [m/s]. Therefore
0Cdg
gm
2  (3 109 )  (5.18 1010 )

 102
3
4
(15 10 )  (6.5 10 )
that corresponds to an error of 1% on the magnitude of the gain and an excess phase shift
of only 0.57º.
-------------------------Problem 7.4.
An amplifier tuned to 1GHz is designed with a AMS 035 NMOS transistor with
W=100 m and L=0.35 m. The drain current is 5 mA. Calculate the gain and phase
errors of this amplifier if the effects of Cdg are neglected.
-------------------------The numerical results of this example show that the effects of the drain-gate
capacitance is negligibly small. Then why this capacitance is known (famous) with its
adverse effects on tuned amplifiers? The answer is related to the effects of Cgs on the
input admittance of the amplifier.
The input admittance of a common source amplifier was found as
yi  s(Cgs  Cdg )  ymi  s(Cgs  Cdg )  sCdg
g m  sCdg
(5.3-a)
Yo
The first term is apparently capacitive, but the second term (the Miller component) needs
to be investigated. Let us to write the Miller admittance in frequency domain, and then
calculate the real and imaginary parts:
ymi ( )  jCdg
g m  jCdg
 g m  jCdg
  2 LCdg
1
(1   2 LC )  j LG
G  jC 
j L
Re  ymi  
 / 0 
2
1   /   
Im  ymi  
 / 0 
2




2
2 Cdg
G  (7.37)
  g m 1   / 0    / 0 
C 
  2 L2G 2 
C
2 2
0
Cdg
Cdg
C
2
1   / 0 2    2 L2G 2



2
 Cdg 1   / 0    LGg m



(7.38)
From (7.38) it is possible to see that;
- At the resonance frequency (for ω = ω0 ) the input conductance is
Re  ymi (0 ) 
02Cdg2
G
that strongly depends on Cdg.
- Above the resonance frequency (where the load impedance is capacitive), the
input conductance is positive and is a function of frequency.
- Below the resonance frequency (where the load impedance is inductive), the
input conductance has a dominant negative component and changes with frequency.
This frequency dependent input conductance and especially its negativity below
the ω0 resonance frequency of the output load is important from different points of view:
- In case of a non-ideal input signal source (that is the realistic case), the signal
voltage on the gate of the transistor changes with frequency. Therefore the overall
frequency characteristic is determined not only by the output load, but also by the internal
impedance of the signal source.
- If a tuned circuit exists in parallel to the input, due to the positive parallel
conductance above ω0 and the negative parallel conductance below ω0, the quality factor
of this circuit decreases above ω0 and increases below ω0. The result is the skew of the
frequency characteristic of the input resonance circuit, that affects the overall frequency
characteristic of the circuit.
- The negative conductance component of the input admittance can overcompensate the losses of the input resonance circuit and can lead the circuit to oscillate.
According to (7.37) the imaginary part of the input admittance of a tuned
amplifier is also depends on the frequency. This is not severe as the varying, even
negative input conductance. It only acts on the tuning of the input resonance circuit, if
there is any.
To exemplify these results the PSpice simulation results of a simple tuned
amplifier are given in Fig. 7.15. Transistor is a AMS 035 NMOS transistor with L = 0.35
m and W = 200 m. D.C. supplies are VDD = 3 V and VG = 0.8 V. L =10 nH and C is
trimmed to 2.34 pF to tune the circuit to f0 = 1 GHz. The parallel resistance representing
the total losses of the resonance circuit is 1 k ohm, that corresponds to Q = 15.9.
Curve-A and B show the variations of the input capacitance and the input
conductance, respectively. The negative input conductance below f0 and positive input
conductance above f0 are obviously seen from curve-B. The maximum values of the input
conductance are 1.2 mS and correspond approximately to the 3 dB frequencies of the
gain that is plotted as curve-C.
These dramatic variations of the input admittance of a tuned MOS amplifier are
obviously due o the drain-gate capacitance of the device, that is unavoidable and its
adverse effects increase with frequency. Consequently a circuit as shown in Fig. 7. 13 can
be used only at the lower end of the RF spectrum. For high frequency RF amplifiers, the
extensively used solution is the “cascode” circuit that was investigated in general in
Section 5.4.
gin (S)
Cin (F)
A
1.0p
0.8p
B
2.0m
1.0m
A(dB)
C
25
20
B
C
0.6p
0
15
A
0.4p
-1.0m
0.2p
-2.0m
10
5
0.8G
0.9G
1.0G
Frequency (Hz)
1.1G
1.2G
Figure 7.15. Variations of the input capacitance (A), the input conductance (B) and the
voltage gain of the amplifier (C). Note the fluctuations of the input capacitance and the
input conductance, and especially negativity of the input conductance below the
resonance frequency.
the input impedance of a common gate circuit is approximately equal to the
parallel equivalent of 1/gm and Csg. Consequently the voltage gain of M1 is low and
equal to ( gm1 / gm 2 ) up to the frequencies close to g m 2 / Csg 2 . Therefore the
Miller component of the input admittance of M1 is smaller compared to that of a high
gain common source amplifier. In addition, since the output resistance of a cascode
circuit is higher than the output resistance of a common source circuit, the effective Q of
the load becomes higher.
+VDD
C’
L
+VG2
M2
vo
Cc
RS
+
vS
M1
+
vi
RG
+VG1
Figure 7.16. Schematic diagram of a tuned cascode amplifier.
To visualize the benefits of the cascode configuration, the simulation results of a
cascode amplifier is given in Fig. 7.17. The parameters of the circuit are same as the
parameters of the common source amplifier, whose simulation results were given in Fig.
7.15:
M1 and M2: AMS 035 NMOS transistor. L = 0.35 m, W = 200 m.
D.C. supplies: VDD = 3 V and VG1 = 0.8 V, VG2 = 1.5 V
L = 10 nH, C’ = 2.34 pF (f0 = 1 GHz)
Parallel resistance representing the total losses of L and C is 1 k ohm.
To ease the comparison, the vertical axes in Fig. 7.17 are intentionally chosen as
same as that of the Fig. 7.15. The obvious advantages of the cascode circuit can be
summarized as follows:
- The input capacitance is almost constant in the whole frequency band and equal
to the input capacitance of M1.
- The input conductance is positive and almost constant in the whole frequency
band. These mean that the input of the circuit is a well defined load for the driving signal
source and has no adverse effect if there is another tuned circuit parallel to the input.
- The band-width of the gain is smaller (the effective Q is higher) compared to
that of the reference common source circuit. This is the result of the high output
resistance of the common gate output transistor M2, as expected.
Cin (F)
A
1.0p
gin (S)
B
2.0m
A(dB)
C
25
C
0.8p
1.0m
20
0.6p
0
15
0.4p
-1.0m
B
10
A
0.2p
-2.0m
5
0.8G
0.9G
1.0G
1.1G
1.2G
Frequency (Hz)
Figure 7.17. Variations of the input capacitance (A), the input conductance (B) and the
voltage gain (C).of the tuned cascode amplifier. Note the almost constant input
capacitance and the input conductance.