Effects of Gate Oxide traps
Silicon di oxide is used as a gate oxide in fabrication of
electron devices. The thickness, quality and method of
preparation of the oxide layer decide the behavior of the
device. The electron and hole traps
characteristics and gain much
affect the I-V
more importance in sub micron
device fabrication techniques.
Traps in Silicon Di oxide
There are various trap states present in oxide layer. They are
as follows 1) Extrinsic trap states – These are related to impurities such
as Sodium and heavy metals
2) Semi- intrinsic trap states- These are generated by water or
hydrogen related species
3) Intrinsic trap states – These are induced by Si-Si
stretched bonds or oxygen vacancy in SiO2 gate oxide.
Due to developments in oxidation processes the first type of
states are not observed. But the second and the third type of
trap states are observed and depend upon the oxidation and
annealing processes which determine the percentage of hydrogen
and oxygen atoms. The presence of oxygen and hydrogen atoms in
the oxide layer greatly affects its behavior under certain
conditions.
Through various electron and hole injection techniques such as
applying high field density, increasing charge and current
densities, charge pumping techniques, it is observed that the
density of trap states generated during hole injection is more
in SiO2 layers that are produced by wet oxidation as compared
to ultra dry oxide films. Ultra dry gate oxides have two times
as many hole traps as wet oxides. Annealing of dry films leads
to increase in density of hole traps. The electron trap density
and hole trap densities have a trade off relationship with
amount of water or hydrogen related defects present. Presence
of hydrogen related species affect the charge trapping in SiO2
in two ways –

Trapping of electrons in the oxide layer.

Relaxation of stress of stretched bonds built near the SiSiO2 interface and termination of bonds with unpaired
electrons.
Dry oxidation atmosphere is prone to development of hole
traps. Ultra dry films are tougher to interface states. The
generation of interface states can be explained with two
models
1) Neutral Species Model – In this model a neutral species such
as activated hydrogen atom is released in an Electrochemical reaction such as
SiOH + e-
(SiO)- + H
This diffuses to Si- SiO2 interface to form traps.
2) The Hole injection model – In this model the injected holes
break the Si–Si bonds at the Si-SiO2 interfaces to produce
interface states.
Ultra dry oxide films have small as density of as grown
electron traps as detectable less than 1011/cm2. They have hole
traps greater than 2.6 + 0.1 x 1012 /cm2 .
Degradation of Thin films SiO2 layers
Integrity of thermal oxide reduces with the decrease in film
thickness while the reliability improves as thickness
decreases. Catastrophic breakdown of very thin oxides is
preceded by an excessive leakage current. This happens at low
fields after high field stress has been applied. Such leakage
current is independent of the interface from which electrons
are injected in to oxide. Also the leakage current is not
affected by any thermal stresses.
In case of devices such as DRAM and EEPROM a failure may occur
due to presence of leakage currents when oxide becomes
sufficiently leaky. This oxide leakage occurs before
destructive breakdown and hence is the main reason for failure
in oxides. Stress induced oxide leakage originates from
localized defect related weak spots where insulator has
experienced substantial degradation from electron stress. This
type of deterioration is not chemical in nature but is
physical or chemical in nature because the oxide leakage is
permanent and stable with respect to time and thermal
annealing. Localized weak spots are present in very thin
oxides due to imperfections such submicrometer particles,
small scale surface roughness on silicon surface before
oxidation, particulate contamination, crystalline defects in
substrate. This also give rise to higher localized fields,
higher trap rate or high local current density. A high field
stress destroys the integrity of such weak spots causing a
physical and/or chemical change. This leads to reduction in
tunneling barrier leading to local increase in tunneling
current. The leakage originates from localized defect related
weak spots, which become more conducive due to low interface
barrier.
The oxide leakage is sensitive to temperature at low fields.
At high tunneling transmission coefficients are very large and
distributed of injected electrons is less dependent on energy
of electrons.
The leakage current shows weaker field
dependence at higher temperatures while temperature effects
tend to disappear at higher fields. This current depends upon
the positive side of the anode interface rather than the
cathode interface. This current increases with the stress and
acts as a positive feedback. This enhanced current generates
more positive charge which further increases the current.This
gives rise to an exponential increase in the current. Thus the
rate of rise with, respect to time, of this leakage current
increases at high speed due to the feedback effect and
exponential nature. This leads to a breakdown.
The weak spots that are created tend to propagate laterally
enlarging the defect area instead of penetrating through the
oxide film. The barrier height is almost constant during
evolution of weak spots. The total defect area widens with
time but tends to saturate with time.
Defect density is dependent on starting substrate, cleanliness
of processing environment and oxidizing and annealing
conditions.
If Tbd = time to breakdown
Xox = effective oxide thinning at localized defect spot
A = oxide area
Vox = voltage across the oxide
S = measure of degree of clustering
Then percentage failure rate can be given as
F ( A, Vox, Tbd) =
1-
1/(1+A(a1b1Xox + a2eb2Xox).S)1/s
Where a1, b1, a2, b2 are constants.
Defects can be decreased by proper substrate preparation
followed by freeing the surface from oxygen. Also CVD can be
deposited to avoid the breakdown sensitivity and substrate
defects.
Electron and Hole traps
Hot carrier effect is one of the most serious problems, which
arises from proximity of drain and source regions leading to
rise in temperature of inversion layer. And thus causes damage
to oxide. This is believed to be caused by creation of
interface states, which are formed when an electron is
injected into the oxide and trapped in the region close to SiSiO2 interface. At Vg=Vd/2 both the electrons and holes are
injected into the oxide. When Vg > Vd/2 current is mostly due
to electrons while below Vd/2 it is due to holes.
AT low gate voltages around Vg=Vd/5 three types of damages
occur.
1) Small quantity of interface states
2) Hole oxide traps
3) Electron oxide traps
4)
When a device damaged due to creation of hole oxide traps is
subjected to electron injection, the positive holes are
neutralized and electron traps are filled up. This is similar
to the case ,when MOS capacitors are subjected to FowlerNordhum stressing, a phenomenon called as neutral electron
trap generation is observed where the electron traps are
caused by hole trapping in the oxide, a SiO2 bond is broken in
the process leaving a trivalent Si atom at the hole trap site
and non bridging oxygen atoms as neutral electron traps. Thus
this cerates equal amount of electron and hole traps formed by
trapped holes.
A testing of a n channel MOS transistor with boron
implantation through oxide(40nm) was compared with another
similar device having oxide thickness 10nm. An initial stress
in the form of appropriate Vd and Vg voltages is applied to
the first device. The Id Vs Vs characteristics are shown in
the figure. A shift is observed in the IV characteristics.
This is possibly due to emptying and filling up of traps in
oxide. Some interpretations of from the graph are as follows

Shift from a to b is due trapping of holes in the oxide
which are localized close to drain junction.

Shift from a to c is present due to neutral electron traps
.The sift between curves b and c is due to neutralization of
holes which mask the interface state effects.
It might also happen that due to incomplete emptying of traps
by holes followed by filling of electrons, the maximum hole
current may not be equal to the maximum electron current.
The
time needed to fill/empty hole traps is greater for hole
injection. The difference b-a in the figure represents the
quantity of oxide traps created.
At high drain voltages oxide trap damage is pre dominant. In
estimation of carrier lifetime both the interface state damage
and oxide trap creation must be taken into account. The point
of crossing of two lines as shown in figure 3 denotes the
point where one mechanism takes over another. At lower
voltages oxide trap creation is dominant while at higher
voltages interface state creation is dominant. Thus maximum
electron trap creation occurs at Vg=Vd/5. Filling of these
traps occurs at Vg = Vd. Holes that may be injected due to
impact ionization are responsible for not only creating hole
traps but also electron traps.
Thus various types of traps are observed in oxide gate layer.
References:
1) The Generation and Characterization of Electron and Hole
Traps created by hole injection during Low Gate Hote Carrier
stressing of n-mos transistors.
IEEE Transactions on Electron Devices, Vol 37, Aug 1990
2) High Field Degradation in Ultra Thin SiO2 Films
IEEE Transactions on Electron Devices, Vol 35, Dec 1988
3) Performance and Reliability Design Issues for Deep
submicrometer MOSFETs
IEEE Transactions on Electron Devices, Vol 38, Mar 1991
4) Electron And Hole Traps in SiO2 Films thermally grown on Si
substrates in Ultra thin Dry oxygen
IEEE Transactions on Electron Devices, Vol 35, Dec 1988
5)Modeling and Characterization of Gate oxide reliability
IEEE Transactions on Electron Devices, Vol 35, Dec 1988