1. PatternInformation block - extensions to IEEE Std 1450.6-2005, Chapter
16
1.1 General
The Compatibility block is a new top-level block of the
PatternInformation block already defined in IEEE Std 1450.6-2005, Chapter
16. Its purpose is to describe the effects of executing two different
Procedure or Macro blocks on the same design component. The tests can be
specified as simultaneous, overlapping or consecutive. The side-effects
can be specified, or the combination of tests can be forbidden.
There may be as many Compatibility blocks as combinations of test Macro
and Procedure blocks, combined with the number of unique Vector offsets
that must be described.
1.2 Compatibility syntax
compatibility_enum=
< Simultaneous
| Offset INTEGER
| Order >
address_difference_enum=
< DiffMoreThan INTEGER
| DiffLessThan INTEGER >
result_location_enum=
< Memory
| Port INTEGER >
result_enum=
< OldData
| NewData
| XMemory
| XWord
| XDifferences >
Environment { CTLMode (CTLMODE_NAME) { PatternInformation {
(Compatibility compatibility_enum {
(Macro MACRO_NAME ({ Address address_difference_enum ;}) ;)*
(Procedure PROC_NAME ({ Address address_difference_enum ;}) ;)*
(NotMacro MACRO_NAME ({ Address address_difference_enum ;}) ;)*
(NotProcedure PROC_NAME ({ Address address_difference_enum ;}) ;)*
(Result result_location_enum result_enum ;)*
})*
}}} // end Environment, CTLMode, PatternInformation
1.3 Compatibility block syntax descriptions
Compatibility compatibility_enum: This statement begins the block of
statements that contains the compatibility information for Macros and
Procedures in the current configuration of the design. The
compatibility_enum refers to the offset in number of Vectors relative to
the first-defined Macro or Procedure. Simultaneous means that subsequent
Macros or Procedures start with no offset. Offset INTEGER means that
subsequent Macros or Procedures start after exactly INTEGER Vector
statements. Order means that the first Macro or Vector completes before
subsequent ones are applied.
Macro MACRO_NAME| Procedure PROC_NAME | NotMacro MACRO_NAME |
NotProcedure PROC_NAME: These statements refer to Macros or Procedures of
the current mode. The MACRO_NAME or PROC_NAME of this statement is
expected to be a valid construct in the current CTL. At least one Macro
or Procedure statement is required, and the first one in the block must
not have an Address sub-statement. Subsequent statements refer to the
first one. The NotMacro and NotProcedure statements differ from the
others in that they forbid the combination of tests (not all usages will
support this function).
Address address_difference_enum: This sub-statement qualifies the
statement that it is appended to, so that the Result (or forbidding of
the operation) only applies if this condition is met. The INTEGER is the
difference between the address used for the current Macro or Procedure
compared to that of the first one listed in the current Compatibility
block, and applies to both positive and negative differences in address.
Result result_location_enum result_enum: This statement specifies the
consequences of applying the Marcos and Procedures as per the
specification in the Compatibility block. A separate Result statement may
be used for the data inside the memory and for each read port. If the
Result block is not specified for the memory or for a particular read
port, all operations specified in the Macros and Procedures are completed
successfully for the missing locations. Results may be specified even for
forbidden operations, since some usages may be unable to avoid them.
1.4 Compatibility block examples
1.4.1 Basic Operations
This example is for a 3-port memory with 2 read and 1 write ports.
Simultaneous read and write to the same address is forbidden, but
simultaneous reads from different ports are allowed. Read and write
operations require one Vector, so any operation beginning before a second
starts is already completed and overlapping is impossible. Bypass mode is
for ATPG and invalidates the memory contents.
PatternInformation {
Procedure read_cycle_R1 { Purpose MemoryRead }
Procedure read_cycle_R2 { Purpose MemoryRead }
Procedure write_cycle { Purpose MemoryWrite }
Procedure mem_bypass { Purpose Transparent; }
Compatibility Simultaneous {
Procedure write_cycle;
NotProcedure read_cycle_R1 {DiffLessThan 1;} ;
// The NotProcedure statement forbids the operation to MBIST & ATPG,
// but simulation of outside patterns requires results.
Result Memory NewData;
Result Port 0 XWord;
}
Compatibility Simultaneous {
Procedure write_cycle;
NotProcedure read_cycle_R2 {DiffLessThan 1;} ;
// The NotProcedure statement forbids the operation to MBIST & ATPG,
// but simulation of outside patterns requires results.
Result Memory NewData;
Result Port 1 XWord;
}
// This block isn’t needed because these are the expected results.
//
Compatibility Simultaneous {
//
Procedure read_cycle_R1;
//
Procedure read_cycle_R2 {DiffLessThan 1;} ;
//
Result Memory OldData;
//
Result Port 0 OldData;
//
Result Port 1 OldData;
//
}
Compatibility Order {
Procedure write_cycle;
NotProcedure mem_bypass;
Procedure read_cycle_R1;
Result Memory XMemory;
Result Port 0 XWord
}
Compatibility Order {
Procedure write_cycle;
NotProcedure mem_bypass;
Procedure read_cycle_R2;
Result Memory XMemory;
Result Port 1 XWord
}
} // End of PatternInformation block
1.4.2 Simultaneous Read and Write Operations
When simultaneous operations give ambiguous results, the Compatibility
block can provide the needed information. This example of a 2-port (1
read, 1 write) memory allows the same address to be written to and read
from in the same Vector.
PatternInformation {
Procedure read_cycle { Purpose MemoryRead }
Procedure write_cycle { Purpose MemoryWrite }
Compatibility Simultaneous {
Procedure write_cycle;
Procedure read_cycle {DiffLessThan 1;} ;
Result Memory NewData;
Result Port 0 OldData;
// This means that the read data is the pre-write data.
// To specify that post-write data is read, use:
//
Result Port 0 NewData;
}
} // End of PatternInformation block
1.4.3 Pipelined Read and Write Operations
Memories with pipeline stages may have operations start while other
operations are still in progress. The Offset argument is required to
specify the results. This example is for a 2-port (1 read, 1 write)
memory with a 3 Vector write operation and a 2 Vector read operation.
PatternInformation {
Procedure read_cycle { Purpose MemoryRead }
Procedure write_cycle { Purpose MemoryWrite }
// Simultaneous read & write is ambiguous because of the pipeline.
// The results must be specified.
Compatibility Simultaneous {
Procedure write_cycle;
Procedure read_cycle;
// Note that the result is the same regardless of address differences.
Result Memory NewData;
Result Port 0 OldData;
}
// Starting with a write and following 1 Vector later with a read
// causes a conflict inside the memory and is not allowed.
Compatibility Offset 1 {
Procedure write_cycle;
NotProcedure read_cycle {DiffLessThan 1;} ;
Result Memory NewData;
Result Port 0 XWord;
}
// Starting with a write and following 2 Vectors later with a read
// is allowed, but this result needs no specification.
//
Compatibility Offset 2 {
//
Procedure write_cycle;
//
Procedure read_cycle;
//
Result Memory NewData;
//
Result Port 0 NewData;
//
}
// Starting with a read and following 1 Vector later with a write
// is allowed, but this result needs no specification.
//
Compatibility Offset 1 {
//
Procedure read_cycle;
//
Procedure write_cycle;
//
Result Memory NewData;
//
Result Port 0 OldData;
//
}
} // End of PatternInformation block