Lab10: Design of Finite State Machines
Experiment dates 2/14/08-2/21/08
Charles Turner
Tom Lesperance
Report written 2/27/08
Purpose:
The purpose of this lab was to design, build and test a overlapping sequence detector that
would detect the input sequences of 01001 and 01101. To do this a finite state machine is
to be designed using D flip-flops, the FSM (finite state machine) can be either a Mealy or
a Moore type machine. The lab is meant to familiarize the experimenter with the design
and construction of FSMs.
Procedure:
To start the lab a state diagram has to be drawn that shows the transitions between each
state depending on the input, W, and the present state. The type of machine described in
this report is a Mealy machine, in that the output, Z, depends on the input and the present
state.
Figure 1 unsimplified mealy state diagram
The initial state diagram is shown above, from that diagram a state table can be made.
The state table should then be used to optimize the design by combining redundant states.
It can be seen from the table that states G and H are identical and states I and J are
identical, so they are combined into states G and I respectively. A simplified state
transition diagram can now be drawn, the simplified diagram contains only 7 states, and
now state assignments are made. Each state was assigned a three bit binary number,
starting with 000 which was assigned to state A. Each state was assigned the next
number in the sequence until state I was assigned 110. A new state transition table was
then made with the state assignments substituted in for the state’s name. From this table
Karnaugh maps were made for the output Z and the inputs to the flip-flops D2, D1 and
D0. The Karnaugh maps allow for the “next state logic” portion of the finite state
machines to be designed. A combination of Multiplexers and gates were used to
implement the next sate logic. A Shannon’s expansion was done around W and Q0 for
each of the K maps to implement each flip-flop input, D2, D1, D0, with a 4:1 mux. With
W and Q0 as the select bits to the three muxs an OR gate is also needed to OR Q1 and Q2
together as an input to two of the muxs. In addition to the OR gate an AND gate is
needed to AND together Q2 and Q1 to get the output Z (this Boolean expression comes
from the Karnaugh map for Z). After coming up with the next state logic the FSM
schematic was made in Quartus. Two 74153 chips were used for the three muxs needed
for the machine, two 7474 chips were used for the two D flip-flops, a chip for the OR
gate and a chip for the AND gate and finally a 555 timer chip was used for the clock,
totaling 7 chips used in the FSM. It should be noted that the 7 state machine presented in
this report is not necessarily the least amount of states possible to implement this device.
Figure 2 The complete schematic for the FSM (minus the timer circuit)
Figure 2 shown above, shows the assembled FSM schematic made using Quartus with the
aforementioned chips. The schematic was then compiled and simulated in Quartus to
produce a vector waveform file that shows the output Z with the clock pulse and input W.
Since the clear and preset inputs are active low they were tied to a logic value of 1 for the
simulation so not to interfere with the output data.
Figure 3 The vector waveform file showing the schematic functions as an overlapping sequence detector
The vector waveform file shown above shows the circuits functionality with the test input
sequence of 11101101001000. The circuit was then assembled on the proto board with
particular attention paid to the amount of wires used to connect the pins of the chips. The
two flip-flop chips were placed next to each other vertically as were the two mux chips,
this was done in a attempt minimize the amount of wire used. The 555 timer circuit was
then assembled on the board according to the following schematic.
Figure 4 shows the schematic for the 555 timer circuit with equations to find the clock period
A time period for the clock cycle large enough to allow for the W input to be changed
was needed, a period of about 1.8 seconds was chosen. This gives resistor A to be about
680Kohms, resistor B to be about 1Mohms and a capacitor value to be 1uf. An
oscilloscope was used to test the assembled circuit, one channel was hooked up to the
clock and the other to the output. The input test sequence provided for W was the entered
via the pushbutton switch built for the W input. While entering in the test sequence the
output waveform was watched to ensure that Z went high at the appropriate time. A logic
analyzer was then used to view each waveform (clock, output, input) over a set amount of
time. This is done to further ensure that the circuit is working properly. The analyzer’s
reserved pins for ground and clock were then hooked to the circuits ground and clock
pins, and the W and Z pins were attached to the analyzer’s pins 1 and 2.
Results:
According to the readouts of the oscilloscope and logic analyzer the circuit made in this
lab works correctly as an overlapping sequence detector.
Figure 5 The Logic analyzer screen showing the clock, input (W), and output (Z) waveforms
From figure 5 the correct output sequence for the given input sequence can be seen, Z
goes high twice at the correct input values, after a small delay. I n addition to working
correctly with the given input sequence the circuit also produced the correct output levels
for different variations of input sequences. The sequences tested all included the
01001and 01101 sequences which the circuit was built to detect. The wire weight for this
circuit came out to be 7.156g.
Conclusion:
The 7.156g wire weight for circuit presented is a fairly average value when compared to
other lab results. The wire weight could have been lessened if fewer chips were used to
construct the circuit or if the chip layout on the proto board were changed. The Logic
Analyzer was introduced in this lab, the logic analyzer is a useful alternative to the
oscilloscope to view logic waveforms. Using a logic analyzer a complete output
waveform can be seen with the clock and input waveform. Using the oscilloscope the
output waveform can be seen going to a logic high value but a complete output waveform
is more difficult to view.
References:
1.
2.
3.
4.
74ABT74 Dual D-type Flip-Flops data sheet, Phillips Semiconductors.
74F153 Dual4-line to 1-line multiplexer data sheet, Phillips Semiconductors
74ABT08 Quad 2 input AND gate data sheet, Phillips Semiconductors.
74ABT32 Quad 2 input OR gate data sheet, Phillips Semiconductors.