14:332:331 Midterm Exam II
14:332:331
Midterm Examination #2
Fall 2002
Name: __________________________________________
S.S.#: _______________________________
1
40
2
30
3
30
Total
100
Instructions:
This exam contains 3 questions. It is closed book and notes. Calculators are
allowed. Do all of your work on the attached sheets.
Please make sure that you finish all the questions.
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14:332:331 Midterm Exam II
(31 pts) 1. Short Answer
A. (5 pt) Describe the condition for an overflow to occur when executing MIPS
instruction add $s0, $s1, $s2 .
CarryIn MSB is not equal to CarryOut MSB
B. (10 pt) Instead of using a special hardware multiplier, it is possible to multiply
using shift instructions and add instructions. This is particularly attractive
when multiplying by small constants. Suppose we want to put 9 times the value
of $s2 into $s3 ignoring any overflow that may occur. Give the minimal
sequence of MIPS instructions to perform $s3  $s2 * 9 using only add
instructions and shift instructions. As a reminder the syntax for the MIPS
shift left logical (sll) instruction is
sll
C.
$t2, $s0, 8
#$t2 = $s0 << 8 bits
sll
$s3, $s2, 3
add
$s3, $s3, $s2
(10 pt) For the VHDL implementation of a full adder shown below, when do
the outputs cout and S settle at their final values (consider the worst case
timing path with the worst case inputs)?
architecture concurrent_behavior of full_adder is
signal t1, t2, t3, t4, t5: std_logic;
begin
t1 <= not A after 1 ns;
t2 <= not cin after 1 ns;
t4 <= not((A or cin) and B) after 2 ns;
t3 <= not((t1 or t2) and (A or cin)) after 2 ns;
t5 <= t3 nand B after 2 ns;
S <= not((B or t3) and t5) after 2 ns;
cout <= not(t1 or t2) and t4) after 2 ns;
end concurrent_behavior;
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14:332:331 Midterm Exam II
cout – 4ns
S – 7ns
D. (3 pt) Give the key disadvantage of the single cycle MIPS datapath design?
Not all the instructions have the same length. Single cycle datapath imposes a
uniform clock cycle time, which should be the slowest instruction execution length.
E.
(3 pt) What decimal number does this two’s complement binary number
represent: 1111 1111 1111 1111 1111 1111 1111 1111two?
-1
F.
(9 pt) Assume that the operation times for the major functional units in the
single-cycle implementation of the MIPS datapath are the following:
 Memory Units: 2ns
 ALU: 2ns
 Adder for PC+4: 1ns
 Adder for branch address computation: 8ns
Assuming that the multiplexors, control unit, PC accesses, sign extension unit,
and wires have no delay, what would be the minimum cycle time? (Hint: You
may want to refer to the datapath shown on page 8).
The minimum cycle time = longest instruction execution length
R-type instructions : 8 ns
lw instruction: 10 ns
sw instruction: 6 ns
beq instruction: 9 ns
j instruction: 2
as a result, the minimum cycle time = 10 ns.
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14:332:331 Midterm Exam II
(30 pts) 3. ALU Design
Consider a 4-bit version of MIPS ALU shown on the next page. Here add/subt
determines whether an addition (add/subt = 0) or subtraction (add/subt = 1) takes
place and op selects the multiplexor output (assume that the top input is selected by
an op of 000, etc.). Assume that it takes
2
4
6
8
ticks for a 2-input and, or, xor, nor to settle at its final output
ticks for a 4-input nor to settle at its final output
ticks for a 6-input multiplexor to settle at its final output
ticks from the latest arriving input for the sum and carry outputs
of a 1-bit full adder to settle at their final output
When do the result outputs settle at their final values for the inputs shown below
(ignoring the test for zero and for overflow)?
add/subt = 0
op = 000
A = 1111
B = 0001
outputs settle at tick _____10________ (3 pt)
To what MIPS instruction does this control setting correspond to? (You do not need
to write down the formal instruction, rather, something like A+B will do)
____________________________A AND B __________________________(3 pt)
When do the result outputs settle at their final values for the inputs shown below
(ignoring the test for zero and for overflow)?
add/subt = 0
op = 100
A = 1111
B = 0001
outputs settle at tick ______40_______ (3 pt)
What is the zero output value for this set of inputs? ____1_____________ (3 pt)
Does this operation overflow? ___NO______
If so, why; if not, why not?(3 pt)
 carry into MSB = 1 and carry out of MSB = 1
 adding a negative (-1) and positive (1) cannot overflow.
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14:332:331 Midterm Exam II
op
add/subt
A0
result0
+
B0
less
A1
result1
+
B1
0
zero
less
A2
+
B2
0
result2
less
A3
result3
+
B3
0
less
overflow
set
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14:332:331 Midterm Exam II
When do the result outputs settle at their final values for the inputs shown below
(ignoring the test for zero and for overflow)?
add/subt = 1
op = 101
A = 1111
B = 0000
outputs settle at tick ________40_____ (3 pt)
What is the zero output value for this set of inputs? ________0___________ (2 pt)
To what MIPS instruction does this control setting correspond to?
___________________slt_________________________________________ (3 pt)
With the ALU design described in class (and shown in its 4-bit version on the
previous page) we assumed that a subtraction operation had to be performed as part
of the beq instruction. This would mean that we would have to wait for the
subtraction operation to complete before selecting the output of the adder (through
the multiplexor) and then testing the result bits for all zero.
Is there a way to do it faster (with the hardware shown)? ____yes_________ (1 pt)
If so, what would be the control bit setting for your new approach? (3 pt)
add/subt = 0
op = 010
With the timing model given, how long would it take for the zero output to settle
using your new approach to beq? (3pt)
outputs settle at tick ___________14______
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14:332:331 Midterm Exam II
(30 pts) 4. Single Cycle Datapath Design
Give the setting for the control signals for the single cycle datapath shown on the
next page when executing a sw instruction. (10 pt)
Control Signal
RegDst
Jump
Branch
MemRead
MemtoReg
Setting
X
0
0
X
X
Control Signal
ALUOp1
ALUOp0
MemWrite
ALUSrc
RegWrite
Setting
0
0
1
1
0
Your task is now to augment this single cycle MIPS datapath so that it can also
perform the instruction jalr (jump and link register) as defined below.
jalr
001111
rs
rs, rd
00000
rd
00000
000000
Its functioning is to cause the datapath to unconditionally jump to the instruction
whose address is in register rs and to save the address of the next instruction (the
instruction following the jalr instruction in the code) in the register rd.
Augment the single cycle MIPS datapath shown on the next page to also handle the
jalr instruction. You may only use additional 2-to-1 multiplexors, additional data
interconnects, and additional 1-bit control signals. Mark a line that is no longer
connected with an X somewhere along its length where the disconnect should occur.
(7pt) on figure
What new control signal(s) did you need to add and explain their basic function.
(3 pt)
jalr control signal that selects the correct input to the two additional muxes
when the instruction is a jalr (src1 from the RegFile to PC and PC+4 to
write data input of the RegFile)
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Page 8 of 9
PC
Give the setting for all the control signals (both previously existing and the one(s)
you added) to execute the jalr. (10 pt)
Read
Address
Instr[31-0]
Instruction
Memory
1
Instr[15-0]
Instr[15 11]
1
0
Instr[20-16]
32
16
Write Data
Instr[5-0]
32
Read
Data 2
Sign
Extend
Register
Read Addr 2
File
Write Addr
Read
Data 1
RegWrite
ALUSrc
Jump
PC+4[31 -28]
Branch
28
Read Addr 1
Control
Instr[25-21]
RegDst
Instr[31-26]
ALUOp
Shift
left 2
x
4
Add
26
Instr[25-0]
1
0
Add
ALU
control
ALU
zero
overflow
Shift
left 2
0
Write Data
Data
Memory
Address
MemRead
Read Data
MemtoReg
PCSrc
MemWrite
1
0
1
1
0
1
14:332:331 Midterm Exam II
x
14:332:331 Midterm Exam II
Control Signal
RegDst
Jump
Branch
MemRead
MemtoReg
ALUOp1
ALUOp0
Setting
1
X
X
X
X
X
X
Control Signal
MemWrite
ALUSrc
RegWrite
Page 9 of 9
Setting
0
X
1
1