MEMORY, DEFINITENESS AND INFORMATION LOSSLESSNESS
OF FINITE AUTOMATA
(Chapter 14, Kohavi)
OVERVIEW:
We’ll consider five kinds of finite memory span: Here is a “schematic” summary:
[++++++++ denotes a known (or observable) sequence. * denotes the state identified as a result. “” means “the least value
making this possible is ” ]
1) Finite (input/output) memory (FM):
[Every input sequence of length  is a homing sequence, at least one input sequence of length
x: ++++++++++++
*
z: ++++++++++++

1 is not an HS]
2) Finite input memory (FIM):
[Every input sequence of length  is a synchronizing sequence, at least one input sequence of length
1 is not an SS]

x: ++++++++++++
*
3) Finite output memory (FOM):
*
z: ++++++++++++

4) Finite output memory for final state (FOMF):
*
z: ++++++++++++

5) Definitely diagnosable (DD)
[Every input sequence of length  is a distinguishing sequence, at least one input sequence of length
1 is not a DS]
x: ++++++++++++
*
z: ++++++++++++

SECTION 1 – FINITE (input/output) MEMORY MACHINES (FM)
Definition: A finite-state machine M is defined as a finite memory machine of order , if  is the least integer, so that the
present state of M can be determined uniquely from the knowledge of the last  inputs and the corresponding  outputs.
[“FM” or “FM-”]
In other words: A machine is finite memory of order  iff every input sequence of lenth  is a homing sequence, and  is
the least integer making this possible.
To test whether a given machine M is FM or not, we may use the homing tree: If all the nodes on some level of the tree are
associated with homogeneous vectors (i.e. correspond to HS’s) then M is FM. The order  is the level number of the
uppermost level for which all nodes are homogeneous. This test is easy, but it is useless if we don’t have a bound for ,
because in this case we won’t know when to stop.
1
EXAMPLE 1: M1 [M1 in Kohavi, table 14-1]
A
B
C
D
x=0
B,0
D,0
D,0
C,0
x=1
C,1
C,0
B,1
A,0
Homing tree:
(ABCD)
------x=0------------------------1-----------(BCDD)
(AC)(BC)
----0--------------1----(CCDD)
(AAC)(B)
--0-----1-(CCDD)
(AA)(BB)
----0--------------1----(BD)(DD)
(BC)(C)(B)
--0------1--(BBD)(D)
(BCC)(C)
--0------1-(CD)(CC)
(AC)(AA)
---0--------1--(DD)(D)(D)
(C)(B)(B)(C)
HS
HS
HS
With this tree we shall never come to a level for which all nodes are homogeneous (i.e. M1 is not FM), but since we don’t
know this, we have to continue forever. Hence this “method” is no good, unless we have a bound on the level-number.
Note the components shown bold in the above tree: (AC)  (BD)  (AC) ... This shows that this chain will go forever,
preventing any level to be all homogeneous. Similarly for (CCDD)  (CCDD) 
TESTING TABLE AND TESTING GRAPH FOR FM
Testing table for FM is made up of two parts:
a) Upper table is the singleton input/output successor table for given machine, hence having n rows.
b) Lower table having one row for each unordered pair of distinct states, these pairs (uncertainties) are made row headings
(hence there are [n (n 1)] / 2 rows). The entries of the lower table are i/o successors of the row headings.
Testing graph for FM is obtained from the lower table. There are exactly [n (n – 1)] / 2 nodes, one node for each unordered
distinct pair. Directed arcs indicate successor relationship, and carry the label x/z.
EXAMPLE (M1, continued)
M1
A
B
0/0
B
D
0/1
-
1/1
C
-
1/0
C
C
D
AB
AC
AD
D
C
BD
BD
BC
-
B
BC
-
A
-
BC
BD
CD
DD
CD
CD
-
-
AC
-
0/0
AB
loop

0/0
BD

CD 
0/0loop
1/00/0
AC

1/1
BC

0/0
AD
THEOREM: M is finite memory if and only if its testing graph (G) is loop-free.
Proof: (a) If M is finite memory then G is loop-free. Let’s prove “If G has a loop, then M is not finite memory”.
Graph has a loop. Apply the input symbols corresponding the labels of the arcs in the loop repeatedly. Result: An
arbitrarily long input sequence cannot resolve the uncertainty regarding the final state. M is not finite memory.
(b) If G is loop-free then M is finite memory. Let’s prove “If M is not finite memory, then G has a loop”.
M is not finite memory. Hence there must exist an arbitrarily long path in G corresponding to some input sequence
X and some pair (Si, Sj) so that the ambiguity can not be resolved. But this is possible only G has a loop, since G
has n (n  1) / 2 nodes in G, the longest path, if there are no loops, can be at most [n (n – 1) / 2]  1 long. QED.
COROLLARY: Let G be a loop-free testing graph for M. If the length of the longest path in G is L, then
Proof: See Kohavi.
 = L + 1.
G has exactly n (n – 1) / 2 vertices. If G is loop-free, the length of the longest path can be at most [n(n – 1) / 2]  1.
 can be at most n (n – 1) / 2. Hence a machine is either not FM, or it is FM- where   n (n – 1) / 2.
2
The testing graph for M1 has two loops, one is (BD)  (AC) (BD)  (AC)  (BD) … Hence if we apply the
arbitrarily long input sequence 10101010… when M1 is in an uncertainty containing BD, the uncertainty regarding the
final state will never be resolved. The other loop is (CD)  (CD)  (CD) … Same considerations for the arbitrarily
long input sequence 00000… and pair (CD).
EXAMPLE 2: M2 [M2 in Kohavi, Table 14-3]
M2
x=0 x=1
A
B,0 D,0
B
C,0 C,0
C
D,0 A,0
D
D,0 A,1
-------------
Testing table:
0/0 0/1 1/1 1/0
A
B
D
B
C
C
C
D
A
D
D
A
----------------------AB
BC
CD
AC
BD
AD
AD
BD
BC
CD
AC
BD
CD
CD
DD
----------------------
Graph:
0/0
AB

1/0
BC

AC
1/0
CD

0/0
BD

AD
0/0
No loops: M2 is FM-
L = 5,  = L + 1 = 6
From the testing graph we see that it is loop free.  M is finite memory.
Find the length of the longest path (there may be more than one longest path, although in this example there is just one).
This path corresponds to (AB)  (BC)  (AC)  (AD)  (BD)  (CD).
L = 5, hence  = 6. Note that 6 is the upper bound for .
If we construct the homing tree for M2, we see that all nodes on the 6th level are associated with homogeneous vectors, and
this level is the uppermost such level.
Our next topic will be: The problem of testing a directed graph to see whether it is loop-free or not, and if loop-free, finding
the length of the longest path.
ALGORITHM TO DETERMINE WHETHER A DIRECTED GRAPH IS LOOP-FREE
We note the following [a sink is a node from which no arcs emanate]:
[(G is loop-free)  (G has one or more sinks)]  [(G has no sinks)  (G is not loop-free)]
(G is loop-free)  (The subgraph resulting from the removal of a sink and all arcs to it is also loop-free)
Consider the following: The connection matrix for a graph G having p vertices is a pp matrix where (i, j)th entry is 1 if
there is an arc from vertex i to vertex j, and 0 otherwise. A row with all zeros in C corresponds to a sink in G. Removal of a
sink and all arcs coming to it corresponds to removal of the row and the column corresponding to that sink.
ALGORITHM
1. Given graph G, construct its connection matrix C. Set k = 0.
2. If there is no all-zero row go to 4, otherwise go to 3. [if no sinks: go to 4, if there is a sink: go to 3]
3. Delete all of the all-zero rows and corresponding columns. Increment k. Go to 2. [remove all sinks, k := k+1, go to 2]
4. If C has not vanished then G has loops. Otherwise G is loop-free. [“vanished” = “there remains no rows, no columns”]
5.  = k
EXAMPLE 2 (continued): Applying the algorithm to M2
AB
AC
AD
BC
BD
CD
000101
001010
000010
010001
000001
000000
delete AC:
k=4
delete CD:
k=1
AB 01
BC 00
AB
AC
AD
BC
BD
00010
00101
00001
01000
00000
delete BC:
k=5
delete BD:
k=2
AB 0
AB
AC
AD
BC
0001
0010
0000
0100
delete AB:
k=6
delete AD:
k=3
AB 001
AC 000
BC 010
Matrix vanished.
Hence: G is loop-free
= k = 6 M2 is FM-6.
3
SECTION 2 – FINITE INPUT MEMORY ( = DEFINITE) MACHINES (FIM)
Definition: A finite-state machine M is defined as a finite input memory of order , or definite of order  (-definite) if
 is the least integer, so that the present state of M can be determined uniquely from the knowledge of the last  inputs to
M. [“FIM” or “FIM-”]
In other words: A machine is finite input memory of order  iff every input sequence of length  is a synchronizing
sequence, and  is the least integer making this possible.
To test whether a given machine M is FIM or not, we may use the synch tree: If all the nodes on some level of the tree are
associated with singletons, i.e. correspond to SS’s) then M is FIM. The order  is the level number of the uppermost level
for which all nodes are singletons. This test is easy, but we must have a bound for , in order it to be applicable.
TESTING TABLE AND TESTING GRAPH FOR FIM
Testing table for FIM is made up of two parts:
a) Upper table is the singleton input successor table for given machine, hence having n rows.
b) Lower table having one row for each unordered pair of distinct states, these pairs (uncertainties) are made row headings
(hence there are [n (n 1)] / 2 rows). The entries of the lower table are input successors of the row headings.
Testing graph for FIM is obtained from the lower table. There are exactly [n (n – 1)] / 2 nodes, one node for each unordered
distinct pair. Directed arcs indicate successor relationship, and carry the label x.
THEOREM: M is finite input memory if and only if its testing graph for FIM (G) is loop-free.
COROLLARY: Let G be a loop-free testing graph for M. If the length of the longest path in G is L, then
 = L + 1.
EXAMPLE 3: M3 [M3 in Kohavi, Table 14-5]
A
B
C
D
x=0
A,0
C,0
A,1
C,1
x=1
B,0
B,1
D,0
B,1
A
B
C
D
x=0
A
C
A
C
x=1
B
B
D
B
--------------AB
AC
BB
AC
AA
BD
AD
AC
BB
BC
AC
BD
BD
CC
BB
CD
AC
BD
---------------
AB
BC
 0 0
1
AC
0 0 1
AD
CD

BD
1
L = 2 (examples: AD-AC-BD, CD-AC-BD, ...)
 = L+1 = 3, i.e. M3 is FIM-3 (“3-definite”).
THEOREM: If a machine is FIM-, than   n – 1. (i.e. M is either not FM, or if it is, it’s order  is at most n – 1.)
Proof uses “the state-table contraction method” to test FIM. See Kohavi.
CANONICAL FORM (INPUT-SHIFT-REGISTER REALIZATION)
The knowledge of last  input values is always sufficient to completely specify the present state of a -definite machine.
Therefore any -definite machine can be realized using a –bit shift register: This shift register at any time instant contains
the last  input values, hence information regarding the state of M at that instant, i.e. the present state. This, together with
the present input, is sufficient to determine the present output and the next state.
Canonical form for a -definite machine (for M3,  = 3):
4
EXAMPLE 3 (ctd). Canonical form for M3 which is FIM-3 is shown above. Now let’s design the combinational logic.
The synchronizing tree for M3 (at third level all nodes are singletons):
ABCD
-----------------------------------------AC
BD
x3
x2
A
x1
x3x2x1
-------------------BD
--------A
B
000
001
--------C
B
010
011
C
--------------------B
---------A
D
100
101
--------C
B
110
111
State table where states are expressed in terms of state variables (x3, x2, x1):
PS
NS,z
x=0
x=1
x3x2x1
x2 x1x
z
x2 x1x
z
0 0 0 A
0 0 0 A 0
0 0 1 B 0
0 0 1 B
0 1 0 C 0
0 1 1 B 1
0 1 0 C
1 0 0 A 1
1 0 1 D 0
0 1 1 B
1 1 0 C 0
1 1 1 B 1
1 0 0 A
0 0 0 A 0
0 0 1 B 0
1 0 1 D
0 1 0 C 1
0 1 1 B 1
1 1 0 C
1 0 0 A 1
1 0 1 D 0
1 1 1 B
1 1 0 C 0
1 1 1 B 1
---------------------------------Truth table of the combinational circuit:
x3 x2x1 x z
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
-----------
Hence,
Karnaugh map for z = z (x3, x2, x1, x):
z(x3,x2,x1,x) = x1x + x2x1’x’ + x3x2’x1
(three AND gates, one OR gate)
Note that since n = 4, two delay elements are sufficient for conventional design.
Also note that  = n – 1 = 3 is the highest value attainable by 
5
Conventional design for M3
Since we have 4 states, 2 flip-flops are required (assume D flip-flops). Let’s call them (i.e. the state variables) K, L.
1) State assignment: Let’s assign A to KL = 00, B to KL = 01, C to KL = 10, and D to KL = 11.
2)
State table
state table in terms of state variables truth table for “next K” [K], “next L” [L], and z
PS
NS,z
PS
NS,z
K L x
[K] [L] z
x=0
x=1
KL
x=0 x=1
0 0 0
0
0
0
A
A,0
B,0
00
00,0 01,0
0 0 1
0
1
0
B
C,0
B,1
01
10,0 01,1
0 1 0
1
0
0
C
A,1
D,0
10
00,1 11,0
0 1 1
0
1
1
D
C,1
B,1
11
10,1 01,1
1 0 0
0
0
1
1 0 1
1
1
0
1 1 0
1
0
1
1 1 1
0
1
1
3) From Karnaugh maps for [K], [L], and z, we find:
[K] = L x’ + K L’ X
[L] = x
z = K x’ + K L + L x
For a D flip-flop, say K, the Dinput DK is equal to [K]. Hence design procedure is finished.
EXAMPLE 4: M4
x=0
x=1
A
B
B
B
C
B
C
D
A
D
A
C
--------------AB
BC
BB
AC
BD
AB
AD
AB
BC
BC
CD
AB
BD
AC
BC
CD
AD
AC
--------------
Construct the testing graph. There are many loops.
Some of them:
AB – BC – AB -...
AC – AB – BC – CD – AC -...
AD – BC – CD – AD -...
AC – BD – BC – CD – AC -...
AC – BD – AC -...
M4 is not FIM
SECTION 3 – FINITE OUTPUT MEMORY MACHINES (FOM)
Definition: A finite-state machine M is defined as a finite output memory machine of order , if  is the least integer, so
that the the knowledge of the last  outputs suffices to determine the state of M at some time during the last  transitions.
EXAMPLE 5: M5 [M5 in Kohavi, Table 14-10]
State table:
Singleton output successor table:
(not necessarily single-valued)
A
x=0
B,0
x=1
D,1
B
C
C,1
B,0
A,1
C,0
D
C,0
C,1
----------------
A
z=0
B
z=1
D
B
C
BC
AC
-
D
C
C
-------------------------AB
(AD)(CC)
AC
(BB)(BC)
AD
(BC)
(CD)
BC
BD
(AC)(CC)
Testing graph [labels are outputs (z)]:
AB
1
1

AD
BD
 1 01
CD
0

BC
0
AC
No loops. M is FOM-
L = 3 (AB1AD1CD0BC)
CD
(BC)(CC)
 = 4
------------------------Worst case (longest path in G): z = 110. Observing the output z = 110 is not sufficient. We need the fourth output bit in
order to identify a state (not necessarily the final state):
6
z:
0
0
 B]
If the fourth
symbol were 1:
C  B




B
 A  D


C
C]
C]

D
 




Ambiguity resolved at this time instant only
A
1

D
1

1
B

A

C]

C
C

Note that after observing z = 1100 or z = 1101, not the final state, but “a state at some time” during the experiment (in this
example the state before the last, shown ) is determined.
EXAMPLE 6: M6 [Problem 14-7b, Kohavi]
x=0
x=1
A
C,0
C,0
B
D,1
A,0
C
C,1
B,0
D
D,1
D,1
---------------
z=0
z=1
A
CC
B
A
D
C
B
C
D
DD
--------------AB
AC
AC
BC
AD
BC
AB
CD
BD
DD
CD
CD
---------------
AB
0

AC
0
0
loop
AD
BC
 1
BD
CD
1
loop

There are loops in the graph: M6 is not FOM. There are for which the ambiguity won’t resolve:
Upper loop:
Lower loop:
z: 0
0
0
0
...
z:
1
1
1
1
1
...
A
C
B
A
C ...
A]
B
A
C
B
A ...
B
D
D
D
D
D ...
C
B
A
C
B ...
C
C
C
C
C
C ...
D]
D
D
D
D
D
D ...
SECTION 4 – FINITE-OUTPUT-FOR-FINAL-STATE-MEMORY MACHINES (FOMF)
Definition: A finite-state machine M is defined as a finite-output-memory-for-final-state machine of order 
FOMF, if  is the least integer, so that the knowledge of the last  outputs suffices to determine the final state of M.
(See problem 14-8, Kohavi).
Test for FOMF: M is FOMF- iff
a) M’s singleton output predecessor table must be single-valued, and
b) M’s testing graph must be loop-free.
If both conditions are satisfied then M is FOMF-, where  = L + 1.
CANONICAL FORM FOR A FOMF- MACHINE
The knowledge of last  output values is always sufficient to completely specify the present state of a FOMF- machine.
Therefore any FOMF- machine can be realized using a –bit shift register: Shift register at any time instant contains last
 output values, hence information regarding the state of M at that instant, i.e. the present state. This, together with the
present input, is sufficient to determine the present output and the next state.
7
EXAMPLE 7. M7
x=0
x=1
A
D,0
E,1
B
B,1
A,0
C
C,0
B,1
D
B,1
C,0
E
A,0
B,1
z=0
z=1
A
D
E
B
A
B
C
C
B
D
C
B
E
A
B
AB
AD
BE
AC
CD
BE
AD
CD
BE
AE
AD
BE
BC
AC
BB
BD
AC
BB
BE
AA
BB
CD
CC
BB
CE
AC
BB
DE
AC
BB
---------------
Draw the testing graph G.
There are no loops in G.
L = 2,  = L+1 = 3  FOMF-3
Some of the longest paths:
AB-AD-BE
AE-AD-BE
AB-AD-CD
BD-AC-CD
There are two sinks: BE and CD.
Every longest path ends up at
a sink.
Output-successor tree:
z3
z2
z1
ABCDE
z=0
z=1
-------------------------------ACD
BE
------------------------------CD
BE
A
B
------------------------C
B
A
B
D
E
A
B

z3z2z1 = 001
level
1
2
3
State Table in terms of the state variables z3, z2, z1:
NS, z
C
B
A
B
D
E
A
B
PS
z3z2z1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
x = 0
z2z1z
0 0 0
0 1 1
1 0 0
1 1 1
0 0 1
0 1 0
1 0 0
1 1 1
C
B
D
B
B
A
D
B
z
0
1
0
1
1
0
0
1
x = 1
z2z1z
0 0 1
0 1 0
1 0 1
1 1 0
0 0 0
0 1 1
1 0 1
1 1 0
B
A
E
A
C
B
E
A
z
1
0
1
0
0
1
1
0
Design proceeds with finding the Boolean function z = f(z3, z2, z1, x). From the above table obtaining the truth table for z,
and using a Karnaugh map (or a suitable algorithm), one finds: z = (z3 z2’) (z1 x)
[AND, Exclusive OR]
An example input-output sequence pair:
x:
0
A
z:
1
D
0
Show the following:
0
C
0
1
C
0
0
B
1
1
B
1
1
A
0
0
E
1
1
A
0
1
E
1
1
B
1
0
A
0
0
D
0
B
1
(a) If M is FIM-m, then it is FM-k where k m,
(b) If M is FOMF than it is FM, (c) If M is FOMF then it is FOM.
EXAMPLE 8. M8
A
B
C
D
x=0
B,0
C,0
A,1
C,1
x=1
D,1
B,1
D,0
B,0
8
M8 is not FIM, this is obvious if one notes the loop AB 0 BC 0 AC 0 AB.
Hence input shift register form does not exist.
M8 is not FOMF either, this is obvious if one notes the loop: AB 0 BC 1 AB.
Hence an output shift register form does not exist.
But M8 is FM-2:
0/0
0/0
0/1
1/0
1/1
A
B
D
B
C
B
C
A
D
D
C
B

AB
BC
BD
AC
AD
BC
BD
CD
AC
BD

AB

BC

1/1
BD
1/0

CD

AC
0/1
L = 1,  = 2
 FM-2
Input/output successor tree
ABCD
-------------------------------------------------------------0/0
x2/z2
0/1
BC
x1/z1 0/0
0/1
1/0
AC
1/1
BD
BD
1/0 1/1
------------C
A
D
B
------------B
A
D
D
------------C
C
B
B

x2z2x1z1=1001
------------C
C
B
B
The input-output shift register form ( = 2 for M8)
First four rows of the 16-row-state table in terms of the state variables x2, z2, x1, z1:
NS, z
PS
x2 z2
C
0 0
A
0 0
D
0 0
B
0 0
..........
x1
0
0
1
1
z1
0
1
0
1
A
B
C
C
x
x1 z1
0 0
0 1
1 0
1 1
= 0
x z
0 1
0 0
0 1
0 0
z
1
0
1
0
D
D
B
B
x1
0
0
1
1
x
z1
0
1
0
1
= 1
x z
1 0
1 1
1 0
1 1
z
0
1
0
1
Details of the design is too long to include here.
The output function z = z(x2, z2, x1, z1, x) is found to be:
z = x2x1x + x2x1’x’ + x2’x1z1’x’ + z2’x1’z1’x’ + x2’z2’z1x + x2’z2x1x’ + x2’z2x1’x.
9
SECTION 5 – DEFINITELY DIAGNOSABLE MACHINES (DD)
Definition: A machine M is said to be diagnosable if it possesses one or more distinguishing sequences.
Definition: A machine M is defined as a definitely diagnosable machine of order  (DD-) if  is the least integer, so
that every input sequence of length  is a distinguishing sequence for M.
In other words, a machine is definitely diagnosable of order  if every node in level  of the distinguishing tree is
associated with a trivial vector, and -th level is the first such level.
Testing table (same as the testing table for FM):
a) Upper table is the singleton input-output successor table,
b) Lower table having one row for each unordered pair of distinct states, these pairs (uncertainties) are made row headings
(hence there are [n (n 1)] / 2 rows). The entries of the lower table are input successors of the row headings.
Testing graph obtained from the lower table. There are exactly [n (n – 1)] / 2 nodes, one node for each unordered distinct
pair. Directed arcs indicate successor relationship, and carry the label x/z. (Same as the testing graph for FM).
Theorem: A machine M is definitely diagnosable if and only if
a) Its testing graph is loop-free, and
b) No repeated entries exist in the testing table. [Proof: Kohavi, p. 428]
Corollary: Let the testing table of machine M be free of repeated entries, and let G be a loop-free testing graph for M. If the
length of the longest path in G is L, then  = L + 1. [Proof: Kohavi, p. 429]
Corollary: A machine is either not DD or it is DD- where   n (n 1)/2.
Possessing a DS is a useful feature since making use of a DS we can readily design fault-detection experiments for the
machine. Given a machine M which does not possess a DS, it seems beneficial to find a method for modifying the design of
M in such a way that it will possess a DS. Instead of modifying M so that it becomes diagnosable, we shall modify it so that
it becomes definitely diagnosable. While modifying M we must not change its original operation. The modification
procedure depends upon addition of one or more output terminals. In “normal” operation these added output terminals are
ignored; they are used only for fault detection or similar tasks.
Fact: To every reduced machine M there corresponds a definitely diagnosable machine M ’, which is obtained from M by
the addition of one or more output terminals.
Fact: For any 2k -state machine, the addition of k outut terminals is sufficient to convert it into a definitely diagnosable
machine (see Kohavi)
EXAMPLE 9. M9 is minimal but it does not possess a DS, we shall modify it (add output terminals) so that it becomes DD.
State table (M9)
PS
NS,z
x=0
A
B,0
B
A,0
C
D,1
D
D,1
Distinguishing tree (M9)
x=1
D,0
B,0
A,0
C,0
Testing Table (M9)
ABCD
-----------(AB)(DD)
(ABCD)
multiple
repeat
No DS!
a) There are three loops in G:
loop 1: AB – AB...
loop 2: AB – BD – BC...
loop 3: AC – AD – CD...
b) There is a repeated entry DD in the table.
AD
0/0
0/1
1/0
1/1
A
B
D
B
A
B
C
D
A
D
D
C
--------------------------AB
AB
BD
AC
AD
CD
BC
AB
BD
BC
CD
DD
AC
-------------------------
10
State table for M9’:
A
NS, z1 z2
x = 0
x = 1
B, 0 1b
D, 0 0d
B
A, 0
0b
B, 0
0c
C
D, 1
0a
A, 0
1f
D
D, 1 1a
C, 0 1c d
-----------------------------------------Note the following:
1. Let’s rename the already existing output z as z1.
2. Let’s add another output z2. We are to design z2.
3. a,a: These should be different to remove DD from the testing table.
4. b,b: These should be different to remove loop 1 [cut AB-AB]
5. c,c: These should be different to remove loop 2 [cut BD-BC]
6. d,d: These should be different to remove loop 3 {cut AD-CD]
7. f: This z2 entry is “free” to chose.
BUT: If we choose this entry as 0, then we have L = 2,  = 3.
If we choose 1, then we have L = 1,  = 2 (better)!
Note that we have here 4 = 22 states. According to the fact cited above, k = 2 and adding at most two output terminals
would be sufficient. But actually adding just one extra output terminal proved to be sufficient (we are lucky).
The distinguishing tree for M9’:
(ABCD)
--------------------------------------(A)(B)(D)(D)
(BD)(AC)
-----------------(B)(A)(D)(D)
(D)(B)(C)(C)
DS
------------------(A)(D)(B)(D)
(B)(C)(D)(A)
DS
DS
DS
---*---
11