Lecture 8: Embedded
Processor Issues
Embedded Computing Systems
Mikko Lipasti, adapted from M. Schulte
Based on slides and textbook from Wayne Wolf
High Performance Embedded Computing
© 2007 Elsevier
Topics
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Bus encoding.
Security-oriented architectures.
CPU simulation.
Configurable processors.
© 2006 Elsevier
Bus encoding
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Encode information on bus
to reduce toggles and
dynamic energy
consumption.
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Count energy consumption
by toggle counts.
encoded
bus
mem
Bus encoding is invisible to
rest of architecture.
Some schemes transmit
side information about
encoding.
© 2006 Elsevier
enc
dec
side
information
CPU
Bus-invert coding
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Stan and Burleson: take
advantage of correlation
between successive bus
values.
Choose sending true or
complement form of bus
values to minimize toggles.
 Why might this approach
work well?
Can break bus into fields
and apply bus-invert coding
to each field.
 How might the bus be
divided?
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Working zone encoding
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Mussoll et al.:
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Used to encode address buses
Uses the observation that the majority of the execution
time for a program is spent in a small range of addresses
Divides addresses into sets called working-zone
Address in a working zone is sent as an offset from the
base in a one-hot code.
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Why is a one-hot code used?
Addresses that are not in a working zone have the entire
value sent.
Compared to bus-invert coding, what would you expect
to be the advantages and disadvantages of this
approach?
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Address bus encoding
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Benini et al: cluster correlated address bits and
then encode clusters
Compute correlation coefficients of transition
variables to determine clusters:
Need to ensure clusters don’t become too large,
since this can increase encode/decode logic.
Use logic synthesis to design encoders and
decoders for each cluster
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Benini et al. results
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What important tradeoffs of the address encoding
technique are not shown in the table below?
[Ben98] © 1998 IEEE
© 2006 Elsevier
Dictionary-based encoding
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Takes advantage of the observation that many values
are repeated on buses.
© 2006 Elsevier
Dictionary-based encoding
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Takes advantage of the observation that many values
are repeated on buses.
Divides bus into three parts:
Only the upper bits of the bus are stored in the
dictionary and used to match dictionary values that
are indexed by the index part.
When the upper bits match, they are put in a high-Z
state and the remaining bits are sent; otherwise all
bits are sent.
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Lv et al. dictionary-based architecture
© 2006 Elsevier
[Lv03] © 2003 IEEE
Lv et al. energy savings
© 2006 Elsevier
[Lv03] © 2003 IEEE
Security-oriented architectures
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There are a variety of security attacks:
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Typical desktop/server attacks, such as Trojan
horses and viruses.
Physical access allows side channel attacks.
Cryptographic instruction sets have been
developed for several architectures.
Embedded systems architecture must add
protection for side effects, consider energy
consumption.
© 2006 Elsevier
Secure architectures
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SmartMIPS and ARM SecureCore offer
security extensions
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Include encryption instructions, specialized
memory management units, etc.
SAFE-OPS
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Designed to protect against software modification
Compiler embeds a watermark into code based
on register assignment.
FPGA accelerator checks the validity of the
watermark during execution.
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Power attacks
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Kocher et al.:
Adversary can observe
power consumption at
pins and deduce data,
instructions within CPU.
Yang et al.: Dynamic
voltage/frequency
scaling (DVFS) can be
used as a
countermeasure.
© 2006 Elsevier
[Yan05] © 2005 ACM Press
CPU simulation
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Performance vs. energy/power simulation.
Temporal accuracy.
Trace vs. execution.
Simulation vs. direct execution.
Simulate using appropriate benchmarks for
embedded systems
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Don’t use SPEC CPU Benchmarks!
Embedded Benchmarks include EEMBC,
MediaBench, MiBench
Benchmarks often should be domain-specific
© 2006 Elsevier
Trace-based analysis
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Instrumentation
generates side
information.
PC-sampling checks
PC value during
execution.
Can measure control
flow, memory
accesses.
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Program counter (PC) sampling
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Example: Unix prof.
Interrupts are used to sample PC periodically.
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Must run on the platform.
Doesn’t provide complete trace.
Subject to sampling problems: undersampling,
periodicity problems.
Generates a call-graph report that indicates the
percentage execution time spent in each
program.
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Program instrumentation
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Example: dinero.
Modify the program to
write trace information.
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Track entry into basic
blocks.
Requires editing object
files.
Provides complete trace.
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Microarchitecture-modeling simulators
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Varying levels of detail:
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Instruction scheduler is not cycle-accurate.
Cycle timers are cycle-accurate.
Can simulate for performance or
energy/power.
Typically written in general-purpose
programming language (e.g., C), not
hardware description language.
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Cycle-accurate simulator
Models the
microarchitecture.
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I-box
Simulating one instruction
requires executing routines for
instruction fetch, decode,
execute, etc.
Models pipeline state.
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Microarchitectural registers are
exposed to the simulator.
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IR
PC
reg
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Trace-based vs. execution-based
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Trace-based:
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Gather trace first, then
generate timing
information.
Basic timing information is
simpler to generate.
Full timing information may
require regenerating
information from the
original execution.
Requires owning the
platform.
© 2006 Elsevier
Execution-based:
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Simulator fully executes the
instruction.
Requires a more complex
simulator.
Requires explicit
knowledge of the
microarchitecture, not just
instruction execution times.
Power simulation
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Model capacitance in the processor.
Keep track of activity in the processor.
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Requires full simulation.
Activity determines capacitive
charge/discharge, which determines power
consumption.
CPU Power Simulators include:
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Simple Power and Wattch for embedded GP
Trimaran with EPIC Explorer for embedded VLIW
© 2006 Elsevier
Automated CPU design
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Customize aspects of CPU for application:
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Instruction set.
Functional units.
Memory system (including register files).
Busses, I/O, and peripherals.
Tools help design and implement custom CPUs.
FPGAs make it easier to implement custom CPUs.
Application-specific instruction processor (ASIP) has
custom instruction set.
Configurable processor is generated by a tool set.
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Techniques
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Architecture optimization tools help choose
the instruction set and microarchitecture.
Configuration tools implement the
microarchitecture (and perhaps compiler).
Early example: MIMOLA [1984] analyzed
programs, created microarchitecture and
instructions, synthesized logic.
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CPU configuration process
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Tensilica configuration options
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© 2004 Tensilica
Tensilica EEMBC comparison
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© 2004 Tensilica
Tensilica energy consumption by subsystem
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© 2006 Tensilica
Toshiba MePcore
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LISA language
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[Hof01] © 2001 IEEE
LISA descriptions and generation
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Memory model includes registers and other
memories.
Uses clause binds operations to hardware.
Timing specified by PIPELINE, IN,
ACTIVATION, ENTITY.
Generates hierarchical VHDL design.
© 2006 Elsevier
PEAS-III
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Synthesis driven by:
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Architectural parameters
such as number of pipeline
stages.
Declaration of function
units.
Instruction format
definitions.
Interrupt conditions and
timing.
Micro-operations for
instructions and interrupts.
Generates both simulation
and synthesis models in
VHDL.
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Instruction set synthesis
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Generate instruction set
from application
program, other
requirements.
Sun et al. analyzed
design space for simple
BYTESWAP() program.
[Sun04] © 2004 IEEE
© 2006 Elsevier
Complex function definition
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Atasu et al. try to
combine many
operations into an
instruction:
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Disjoint operator graphs.
Multi-output instructions.
Operator graph must be
convex---value cannot
leave, then re-enter the
instruction.
Textbook discusses
several other
approaches
© 2006 Elsevier
[Ata03] © 2003 ACM Press
Limited-precision arithmetic
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Fang et al. used affine
arithmetic to analyze
numerical characteristics of
algorithms.
Mahlke synthesize variable
bit-width architectures given
bit-width requirements.
Cluster operations to find a
small number of distinct bit
widths.
What advantages and
disadvantages might this
approach have?
[Mah01] © 2001 IEEE
© 2006 Elsevier