Welcome to IC Mask Design
Training
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Fabrication Process
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Agenda
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What we want!!!!
Steps involved in the fabrication process
N-Well Process
P-Well Process
Twin Tub Process
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What we want!!!!!
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Lets fabricate this first!!!!!
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Steps involved in the fabrication
process
Crystal Growth
Epitaxial Growth
Film Formation
Lithography
Etching
Impurity Doping
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Crystal Growth
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Techniques for
growing single
crystals of Silicon to
form a Wafer.
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General Procedure
Starting Material
Polycrystalline Semiconductor
Single Crystal
Wafer
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Single Crystal Silicon growth
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Czochralski method
Silicon crystal growth from the Melt
> 90 % of the the semiconductor
industry use this option.
Starting Material : Quartzite – Pure form
of Sand (SiO2)
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Czochralski Method (Contd)
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SiO2 is heated in a furnace along with
various forms of carbon like coal, coke
and wood chips
SiC + SiO2  Si + SiO + CO
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This produces a metallurgical- grade
Silicon with a purity of about 98 %
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Czochralski Method (Contd)
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Solid Silicon is pulverized and treated with
Hydrogen Chloride (HCl)
Si + 3HCl  SiHCl3 + H2
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TriChloroSaline (SiHCl3) is liquid at room
temperature
Fractional distillation removes unwanted
impurities
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Czochralski Method (Contd)
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Electronic – grade Silicon (EGS) is got
by hydrogen reduction of SiHCl3
SiHCl3 + H2  Si + 3HCl
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This reaction takes place in a reactor
with resistance-heated Silicon rod on
which the deposition takes place.
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Czochralski Method (Contd)
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ECG is a polycrystalline material of high
purity (impurity concentration is in the
order of parts-per-billion) is the raw
material for device-quality single crystal
Silicon
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Czochralski Method (Contd)
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Crystal Puller
Three main parts
A furnace – which includes a fusedsilicon (SiO2) crucible , a graphite
susceptor, a rotation mechanism , a
heating element and a power supply
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Czochralski Method (Contd)
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A crystal pulling mechanism – contains
a seed holder and a counter-clockwise
rotating mechanism
An Ambient control – a gas source
(argon), a flow control and a exhaust
system
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Czochralski Method (Contd)
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Crystal growing process
- Polycrystalline Silicon (EGS) is placed
in the crucible and heated to its melting
point
- A suitably oriented seed-crystal is is
suspended in the crucible
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Czochralski Method (Contd)
- the seed crystal is slowly withdrawn
- Progressive freezing at the solid-liquid
interface yields a large, single crystal called
Ingot
- typical pull rate is a few millimeters per
minute
- a know amount of dopant is added to the
melt to obtain the desired doping
concentration
- For Silicon born and phosphorus are the
common dopants for p and n type materials
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Material Characterization
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Wafer Shaping
Crystal characterization
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Material Characterization (Contd)
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Wafer Shaping
- the two ends are removed
- the surface is grinded to to give the
required diameter
- one or more flat regions grounded
along the length of the ingot
- ingots are diamond sawed to give
wafers
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Material Characterization (Contd)
- Slicing determines four wafer
parameter
Surface orientation
Thickness (0.5-0.7 mm)
Taper
Bow
- both the sides are lapped with a
mixture of Al2O3 and glycerin
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Material Characterization (Contd)
- the damaged and contaminated
regions are removed using chemical
etching
- polished – to provide a smooth and
specular surface
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Material Characterization (Contd)
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Crystal characterization
- Crystal defects
- Material properties
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Material Characterization (Contd)
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Crystal Defects
- Point defects
- Line defects
- Area defects
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Material Characterization (Contd)
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Material Properties
- Resistivity
- Minority carrier lifetime
- Trace impurities such as oxygen and carbon
- Surface flatness
- Slice Taper
- Slice Bow
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Epitaxial Growth
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Growth of crystal of one mineral on
another to achieve same structural
orientation
Methods
- Chemical-Vapor Deposition
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Chemical-Vapor Deposition
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Also know as Vapor-Phase epitaxy
Silicon Tetrachloride (SiCl4),
Dichlorosilane (SiH2Cl2), trichlorosilane
(SiHCl3) and Silane (SiH4) are used
SiCl4 + 2H2  Si + 4HCl
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Chemical-Vapor Deposition
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A competing reaction also takes place
SiCl4 + Si  2SiCl2
Etching will take place if the
concentration is too high.
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Chemical-Vapor Deposition
(Contd)
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Diborane (B2H6) is used as p-type
dopant
Phospine (PH3) or Arsine (AsH3) is used
for n-type
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Film Formation
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Several different layers of thin film need to be
fabricated during IC fabrication
Thin films can be classified as
- Thermal Oxides
- Dielectric layers
- Polycrystalline Silicon
- Metal Films
Chemical-Mechanical Polishing
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Film Formation (Contd)
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Thermal Oxidation
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Gate-oxide and Field-oxide fall are grown
using this technique
Gate-Oxide is the layer below which a
conducting channel is formed between source
and drain
Field-Oxide provides isolation from other
devices
Gate-Oxide and Field-Oxide are grown using
thermal oxidation
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Thermal Oxidation (Contd)
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Setup of Thermal Oxidation
- Filtered flow of air is maintained is
maintained at one end of the cylindrical tube.
This minimizes dust and particulate matters in
the air surrounding the wafers and minimize
contamination during wafer loading
- Oxidation temperature is generally 9000c –
12000c
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Thermal Oxidation (Contd)
- Oxidation system uses microcomputers to
regulate the gas flow sequence, automatic
insertion and removal of wafers, to ramp
temperature, to maintain the oxidation
temperature
- Dry Oxidation
Si + O2  SiO2
- Wet Oxidation
Si + 2H2O  SiO2 +2H2
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Dielectric Deposition
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Used for deposition of insulation layer
and the passivation layer
Three commonly used methods
- Atmosphere-pressure CVD
- Low-Pressure CVD
- Plasma-enhanced CVD
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Dielectric Deposition (Contd)
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Setup of Atmospheric-Pressure CVD and LowPressure CVD are similar to the Thermal
oxidation chamber. The gases used are
different.
Setup of Plasma-Enhanced CVD
- RF voltage causes the plasma discharge
- Temperature is maintained at 100-4000c
using resistance heater
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Silicon Dioxide Deposition
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Used to insulate multilevel metallization,
to mask ion implantation diffusion and
to increase the thickness of the
thermally grown SiO2
For low temperature (300-5000C)
deposition, film is formed by reacting
Silane (SiH4) and oxygen
SiH4 + O2  SiO2 +2H2
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Silicon Dioxide Deposition (Contd)
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For intermediate temperature (500-8000C)
deposition, TetraEthylOrthoSilicate
(Si(OC2H5)4) is decomposed in a LPCVD
Si(OC2H5)4  SiO2 + by-products
For high temperature (9000C) deposition,
SiO2 is deposited by reacting DiChloroSilane
(SiCl2H2) with Nitrous oxide (N2O)
SiCl2H2 + 2N2O  SiO2 + 2N2 +2HCl
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Silicon Nitride Deposition
Acts as good barrier for water and
sodium, excellent scratch protection, as
mask for selective oxidation of silicon
 In LCPVD process, DiChloroSilane and
ammonia react at 700-8000C to deposit
Silicon Nitride
3SiCl2H2 + 4NH3  Si3N4 + 6HCl + 6H2
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Silicon Nitride Deposition (Contd)
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Silicon Nitride is formed by reacting
Silane and ammonia in an argon
discharge or Nitrogen discharge PlasmaEnhanced CVD
SiH4 + NH3  SiNH + 3H2
2SiH4 + N2  2SiNH + 3H2
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PolySilicon Deposition
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Used as gate electrode, high value
resistor and also as conductor for shot
length
LPCVD operating at 600-6500C is used
to react pyrolyzing silane according to
the following reaction
SiH4  Si + 2H2
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Metallization
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Physical vapor deposition
- Evaporation and E-Beam Evaporation
When a source of material is heated above its
melting evaporation occurs. The evaporated
atoms travel at high velocity and gets settled
on the wafer surface. The heating is done
through resistance heating, rf heating or
through the use of electron beam
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Metallization (Contd)
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- Ion Beam Sputtering
A source of Ion beam is accelerated and
impinged on the surface of the
semiconductor wafer. Magnetic field is
used to increase the efficiency
Chemical vapor deposition (CVD) is also
used for certain metals
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Chemical-Mechanical Polishing
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Used for global planarization
It consists of the sample surface against a
pad that carries slurry between them
Abrasive materials in the slurry cause
mechanical damage on the sample surface
loosening the material for enhanced chemical
attack or fracturing of the pieces of the
surface into slurry where they dissolved or
swept away
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Lithography
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Lithography is the process of transferring
patterns of geometric shapes on a mask to a
thin layer of radiation-sensitive material called
photo-resist covering the surface of a
semiconductor wafer. These patterns define
the various regions of a integrated circuit
And you as a IC Layout mask designer will be
defining these mask
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Optical Lithography
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Vast majority of lithographic
equipments for IC fabrication is Optical
equipments using ultraviolet light
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The Clean Room
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Clean rooms are necessary because dust
particles in the air can settle on
semiconductor wafers and the lithographic
masks and can cause defects in the devices,
which will result in the circuit failure
The total number of dust particles, the
temperature and the humidity are controlled
in a clean room
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The Clean Room (Contd)
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Two systems to define a clean room
1. English system – the numerical
designation of the class is taken from the
maximum allowable number of particles
0.5µm and larger, per cubic foot
2. Metric system – the class is taken form
the logarithm (base 10) of the maximum
allowable number of particles 0.5µm and
larger, per cubic meter
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Exposure Tools
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The pattern transfer process is
accomplished by using a lithographic
exposure tool
Three parameters define the
performance
- Resolution
- Registration
- Throughput
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Exposure Tools (Contd)
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Resolution – is the minimum feature
dimension that can be transferred with high
fidelity to a resist film on a semiconductor
wafer
Registration – is a measure of how accurately
patterns on successive masks can be aligned
(or overlaid) with respect to the previously
defined patterns on wafer
Throughput – is the number of wafers that
can be exposed per hour for a given mask
level
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Exposure Tools (Contd)
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Two optical methods
- Shadow printing
- Projection printing
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Exposure Tools (Contd)
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Shadow printing
- Contact printing – The mask and
the wafer are in direct contact
- Proximity printing - The mask and
the wafer are in close proximity
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Exposure Tools (Contd)
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Projection printing
- The mask patterns are projected on to the
resisted-coated wafer many centimeters away
form the mask
- To increase resolution only a small portion
of the mask is exposed at a time and the area
is scanned or stepped over the wafer to cover
the entire surface
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Exposure Tools (Contd)
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Four methods
- Annual-field wafer scan
- 1:1 Step-and-Repeat
- M:1 reduction step-and-repeat
- M:1 reduction step-and-scan
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Exposure Tools (Contd)
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Ultraviolet source
- High-pressure mercury-arc lamp is
widely used – 436nm – 0.3µm
- KrF excimer laser – 248nm – 0.18µm
- ArF excimer laser – 193nm – 0.10µm
- F2 excimer laser – 157nm – 0.07µm
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Masks
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Using EDA tools, layout designers
completely describe the circuit patterns
electrically
The digital data produced by the EDA
tool then drives a pattern generator,
which is an electron-beam lithographic
system that transfers the patterns
directly to electron-sensitized mask
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Masks (Contd)
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The mask consists of a fused silica substrate
covered with chromium layer. 15x15cm2 in
size and 0.6cm in thickness
The pattern on a mask defines one level of an
IC design. The composite layout is broken
into mask levels that correspond to the IC
process sequence
Typically 15-20 different mask levels are
required for a complete IC process cycle
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Masks (Contd)
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Defects can be introduced during the
manufacture of mask or during the
subsequent lithographic processes
Yield is defined as the ratio of number of
good chips to the total number of chips per
wafer
y = e –DA , where D(Defect Density) is the
average number of fatal defects per unit area
and A is the area of a chip
For a N level mask the final yield is y = e -NDA
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Photoresist
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A radiation-sensitive compound
Types
- Positive resists – The exposed region
becomes more soluble and can be removed
of more easily during development. The
pattern formed is same as on the mask
- Negative resists – The exposed regions
become less soluble and the pattern formed
is the reverse of that on the mask
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Photoresist (Contd)
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Positive resist
- Consists of a photosensitive compound, a
base resin and an organic solvent
- Prior to exposure the photosensitive
compound is insoluble in the developer
solution. After exposure, the photosensitive
compound absorbs the radiations, changes its
chemical structure and becomes soluble in
the developer solution
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Photoresist (Contd)
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Negative resist
- Consists of polymers combined with a
photosensitive compound
- After exposure, the photosensitive
compound absorbs the optical energy and
converts it into chemical energy to initiate a
polymer linking reaction. These cross-linked
polymers become insoluble in the developer
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Etching
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Cleaning of the wafer to remove
contamination that results from handling and
storing and also for selective removal of
certain portion of the deposited material on a
wafer
The material to be removed can be the
contamination, insulating layer, the
photoresist, the metal layers et al
Two methods are :
- Wet Chemical etching
- Dry or Plasma Etching
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Wet Chemical Etching
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Three basic steps are involved
- The reactants are transported by
diffusion to the reacting surface
- Chemical reaction occurs at the
surface
- The products form the surface are
removed by diffusion
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Wet Chemical Etching (Contd)
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Silicon Etching
- First the silicon is oxidized using Nitric acid
in water or acetic acid (CH3COOH)
Si + 4NHO3  SiO2 + 2H2O + 4NO2
- HydroFluoric acid is used to dissolve the
SiO2 layer
SiO2 + 6HF  H2 SiF6 + 2H2O
Polysilicon etching is similar to Si etching
except the rate of etching is faster and hence
need to be controlled precisely
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Wet Chemical Etching (Contd)
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Silicon Dioxide Etching
- SiO2 etching is accomplished using a dilute
solution of HydroFluoric acid
SiO2 + 6HF  H2 + SiF6 + 2H2O
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Silicon Nitride Etching
- Si3N4 is etched using HydroFluoric (HF) acid
and Phosphoric acid (H3PO4)
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Wet Chemical Etching (Contd)
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Aluminum Etching
- Etched using heated solutions of
Phosphoric acid, Nitric acid, acetic acid
and DI water
- Nitric acid (HNO3) oxidizes the
aluminum and then the oxide is
dissolved in Phosphoric acid (H3PO4)
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Dry or Plasma Etching
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Plasma is a fully or partially ionized gas
compound
When an electric field of sufficient
magnitude is applied to a gas, the gas
breakdowns and becomes ionized
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Plasma Etching (Contd)
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Plasma Etching process takes place in 5 steps
- The etchant species is generated in plasma
- The reactant is then transported by diffusion
through the stagnant gas layer to the surface
- The reactant is absorbed on the surface
- Chemical reaction takes place to form a
volatile compound
- The compounds are desorbed in from the
surface, diffused into the bulk gas and
pumped out of the system
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Plasma Etching (Contd)
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Two methods
- Physical Method
Positive Ions bombard the surface at
high velocity
- Chemical Method
Neutral reactive species generated
by the plasma interact with the material
surface to form volatile products
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Impurity Doping
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Introduction of controlled amounts of
impurity dopants into the
semiconductor. This changes the
electrical properties of the
semiconductors
Two methods
- Diffusion
- Ion Implantation
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Diffusion
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Dopant atoms are placed on or near the
surface of the wafer by deposition from
the gas phase of the dopant or by using
doped-oxide sources
At elevated temperatures, the dopant
diffuses into the wafer because of high
concentration
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Open tube diffusion system
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Wafer is placed in a controlled high
temperature quartz-tube furnace
Gas containing the required dopant is
passed over it at around 6000C
Boron is used for p-type
Arsenic and Phosphorous are used for
n-type
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Open tube diffusion system (Contd)
An example for phosphorous diffusion
using a liquid source is
4POCl3 + 3O2  2P2O5 + 6Cl2
P2O5 forms a glass on silicon wafer and is
then reduced to phosphorous by Si
2P2O5 + 5Si  4P + 5SiO2
Phosphorous then diffuses into the wafer
and Cl2 is released
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Ion Implantation
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Introduction of energetic, charged
particles into a substrate
More precise control and reproducibility
of impurity doping and its lower
processing temperature
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Medium-Energy Ion Implantor
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Ion source has a heated filament to break up
the source gas like BF3 or AsH3 (B+ or As+).
An external voltage causes the charged ions
to move out of the ion-source chamber into a
mass analyzer
Mass analyzer filters out ions other then
those with the required mass-to-charge ratio
The selected ions are then accelerated using
high voltage source
Using electrostatic deflection plates the ion is
scanned over the wafer
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