VLSI Design
MOSFET
Zhuo Feng
1.1
Z. Feng VLSI Design
Silicon Lattice
■ Transistors are built on a silicon substrate
■ Silicon is a Group IV material
■ Forms crystal lattice with bonds to four neighbors
1.2
Si
Si
Si
Si
Si
Si
Si
Si
Si
Z. Feng VLSI Design
Dopants
■ Silicon is a semiconductor
■ Pure silicon has no free carriers and conducts poorly
■ Adding dopants increases the conductivity
■ Group V: extra electron (n-type)
■ Group III: missing electron, called hole (p-type)
Si
Si
Si
Si
Si
Si
As
Si
Si
B
Si
Si
Si
Si
Si
-
+
N-type
1.3
Z. Feng VLSI Design
+
-
Si
Si
Si
P-type
P-N Junctions
■ A junction between p-type and n-type
semiconductor forms a diode.
■ Current flows only in one direction
Current flow direction
p-type
n-type
Electron flow direction
anode
1.4
cathode
Z. Feng VLSI Design
NMOS Transistor
■ Four terminals: gate, source, drain, body
■ Gate – oxide – body stack looks like a capacitor
► Gate and body are conductors
► SiO2 (oxide) is a very good insulator
► Called metal – oxide – semiconductor (MOS) capacitor
► Even though gate is no longer made of metal
Source
Gate
Drain
Polysilicon
SiO2
n+
Body
p
n+
bulk Si
Substrate, body or bulk
1.5
Z. Feng VLSI Design
NMOS Operation
■ Body is commonly tied to ground (0 V)
■ When the gate is at a low voltage:
► P-type body is at low voltage
► Source-body and drain-body diodes are OFF
► No current flows, transistor is OFF
Source
Gate
Drain
Polysilicon
SiO2
0
n+
n+
S
p
1.6
Z. Feng VLSI Design
bulk Si
D
NMOS Operation Cont.
■ When the gate is at a high voltage:
► Positive charge on gate of MOS capacitor
► Negative charge attracted to body
► Inverts a channel under gate to n-type
► Now current can flow through n-type silicon from source
through channel to drain, transistor is ON
Source
Gate
Drain
Polysilicon
SiO2
1
n+
n+
S
p
1.7
Z. Feng VLSI Design
bulk Si
D
PMOS Transistor
■ Similar, but doping and voltages reversed
► Body tied to high voltage (VDD)
► Gate low: transistor ON
► Gate high: transistor OFF
► Bubble indicates inverted behavior
Source
Gate
Drain
Polysilicon
SiO2
p+
p+
n
1.8
Z. Feng VLSI Design
bulk Si
Power Supply Voltage
■ GND = 0 V
■ In 1980’s, VDD = 5V
■ VDD has decreased in modern processes
► High VDD would damage modern tiny transistors
► Lower VDD saves power
■ VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
1.9
Z. Feng VLSI Design
Transistors as Switches
■ We can view MOS transistors as electrically
controlled switches
■ Voltage at gate controls path from source to
drain
d
nMOS
pMOS
g=1
d
d
OFF
g
ON
s
s
s
d
d
d
g
OFF
ON
s
1.10
g=0
Z. Feng VLSI Design
s
s
CMOS Inverter
A
VDD
Y
0
1
A
A
Y
Y
GND
1.11
Z. Feng VLSI Design
CMOS Inverter
A
VDD
Y
0
1
OFF
0
A=1
Y=0
ON
A
Y
GND
1.12
Z. Feng VLSI Design
CMOS Inverter
A
Y
0
1
1
0
VDD
ON
A=0
Y=1
OFF
A
Y
GND
1.13
Z. Feng VLSI Design
CMOS NAND Gate
A
B
0
0
0
1
1
0
1
1
Y
Y
A
B
1.14
Z. Feng VLSI Design
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
0
1
1
1.15
ON
ON
Y=1
A=0
B=0
Z. Feng VLSI Design
OFF
OFF
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
1.16
OFF
ON
Y=1
A=0
B=1
Z. Feng VLSI Design
OFF
ON
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
1.17
ON
A=1
B=0
Z. Feng VLSI Design
OFF
Y=1
ON
OFF
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
0
1.18
OFF
A=1
B=1
Z. Feng VLSI Design
OFF
Y=0
ON
ON
CMOS NOR Gate
A
B
Y
0
0
1
0
1
0
1
0
0
1
1
0
1.19
A
B
Y
Z. Feng VLSI Design
3-input NAND Gate
■ Y pulls low if ALL inputs are 1
■ Y pulls high if ANY input is 0
Y
A
B
C
1.20
Z. Feng VLSI Design
CMOS Fabrication
■ CMOS transistors are fabricated on silicon wafer
■ Lithography process similar to printing press
■ On each step, different materials are deposited or
etched
■ Easiest to understand by viewing both top and
cross-section of wafer in a simplified
manufacturing process
1.21
Z. Feng VLSI Design
Inverter Cross-section
■ Typically use P-type substrate for NMOS
transistors
■ Requires N-well for body of PMOS transistors
► Silicon dioxide (SiO2) prevents metal from shorting to other
layers
input A
GND
VDD
Y
SiO2
n+ diffusion
n+
n+
p+
p+
n well
p substrate
nMOS transistor
1.22
p+ diffusion
polysilicon
metal1
pMOS transistor
Z. Feng VLSI Design
Well and Substrate Taps
■ P-type substrate (body) must be tied to GND
■ N-well is tied to VDD
■ Use heavily doped well and substrate contacts (
taps)
► Establish a good ohmic contact providing low resistance for
bidirectional current flow
A
GND
VDD
Y
p+
n+
n+
p+
p+
n well
p substrate
well
tap
substrate tap
1.23
Z. Feng VLSI Design
n+
Inverter Mask Set
■ Transistors and wires are defined by masks
► Inverter can be obtained using six masks: n-well,
polysilicon, n+ diffusion, p+ diffusion, contacts and metal
■ Cross-section taken along dashed line
A
Y
GND
VDD
nMOS transistor
well tap
substrate tap
1.24
pMOS transistor
Z. Feng VLSI Design
Detailed Mask Views
■ Six masks
► n-well
n well
► Polysilicon
Polysilicon
► N+ diffusion
n+ Diffusion
► P+ diffusion
p+ Diffusion
► Contact
Contact
► Metal
Metal
1.25
Z. Feng VLSI Design
Fabrication
■ Chips are built in huge factories called fabs
■ Contain clean rooms as large as football fields
Courtesy of International
Business Machines (IBM) Corporation.
Unauthorized use not permitted.
1.26
Z. Feng VLSI Design
Fabrication Steps
■ Start with blank wafer
■ Build inverter from the bottom up
■ First step will be to form the n-well
► Cover wafer with protective layer of SiO2 (oxide)
► Remove layer where n-well should be built
► Implant or diffuse n dopants into exposed wafer
► Strip off SiO2
p substrate
1.27
Z. Feng VLSI Design
Oxidation
■ Grow SiO2 on top of Si wafer
► 900 – 1200 Celcius with H2O or O2 in oxidation
furnace
SiO2
p substrate
1.28
Z. Feng VLSI Design
Photoresist
■ Spin on photoresist
► Photoresist is a light-sensitive organic polymer
► Softens where exposed to light
Photoresist
SiO2
p substrate
1.29
Z. Feng VLSI Design
Lithography
■ Expose photoresist through n-well mask
■ Strip off exposed photoresist
Photoresist
SiO2
p substrate
1.30
Z. Feng VLSI Design
Etch
■ Etch oxide with hydrofluoric acid (HF)
■ Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
1.31
Z. Feng VLSI Design
Strip Photoresist
■ Strip off remaining photoresist
► Use mixture of acids called piranha etch
■ Necessary so resist doesn’t melt in next step
SiO2
p substrate
1.32
Z. Feng VLSI Design
N-well
■ N-well is formed with diffusion or ion implantation
■ Diffusion
► Place wafer in furnace with arsenic gas
► Heat until As atoms diffuse into exposed Si
■ Ion Implantation
► Blast wafer with beam of As ions
► Ions blocked by SiO2, only enter exposed Si
SiO2
n well
1.33
Z. Feng VLSI Design
Strip Oxide
■ Strip off the remaining oxide using HF
■ Back to bare wafer with n-well
■ Subsequent steps involve similar series of steps
n well
p substrate
1.34
Z. Feng VLSI Design
Polysilicon
■ Deposit very thin layer of gate oxide (SiO2)
► < 20 Å (6-7 atomic layers)
■ Chemical Vapor Deposition (CVD) of silicon layer
► Place wafer in furnace with Silane gas (SiH4)
► Forms many small crystals called polysilicon
► Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate
1.35
Z. Feng VLSI Design
Polysilicon Patterning
■ Use same lithography process to pattern
polysilicon
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
1.36
Z. Feng VLSI Design
Self-Aligned Process
■ Use oxide and masking to expose where n+
dopants should be diffused or implanted
■ N-diffusion forms NMOS source, drain, and nwell contact
n well
p substrate
1.37
Z. Feng VLSI Design
N-diffusion
■
■
■
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
n+ Diffusion
n well
p substrate
1.38
Z. Feng VLSI Design
N-diffusion cont.
■ Historically dopants were diffused
■ Usually ion implantation today
■ But regions are still called diffusion
n+
n+
n+
n well
p substrate
1.39
Z. Feng VLSI Design
N-diffusion cont.
■ Strip off oxide to complete patterning step
n+
n+
n+
n well
p substrate
1.40
Z. Feng VLSI Design
P-Diffusion
■ Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
p+
n+
n+
p+
p+
n well
p substrate
1.41
Z. Feng VLSI Design
n+
Contacts
■ Now we need to wire together the devices
■ Cover chip with thick field oxide
■ Etch oxide where contact cuts are needed
Contact
Thick field oxide
p+
n+
n+
p+
p+
n well
p substrate
1.42
Z. Feng VLSI Design
n+
Metallization
■ Sputter on aluminum over whole wafer
■ Pattern to remove excess metal, leaving wires
Metal
Metal
Thick field oxide
p+
n+
n+
p+
p+
n well
p substrate
1.43
Z. Feng VLSI Design
n+
Layout
■ Chips are specified with set of masks
■ Minimum dimensions of masks determine
transistor size (and hence speed, cost, and
power)
■ Feature size f = distance between source and
drain
► Set by minimum width of polysilicon
■ Feature size improves 30% every 3 years or so
■ Normalize for feature size when describing
design rules
■ Express rules in terms of l = f/2
► E.g. l = 0.3 mm in 0.6 mm process
1.44
Z. Feng VLSI Design
Simplified Design Rules
■ Conservative rules to get you started
1.45
Z. Feng VLSI Design
Inverter Layout
■ Transistor dimensions specified as Width / Length
► Minimum size is 4l / 2l, sometimes called 1 unit
► In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long
1.46
Z. Feng VLSI Design
Summary
■ MOS Transistors are stack of gate, oxide, silicon
■ Can be viewed as electrically controlled switches
■ Build logic gates out of switches
■ Draw masks to specify layout of transistors
■ Now you know everything necessary to start
designing schematics and layout for a simple chip!
1.47
Z. Feng VLSI Design