ITRS Emerging Logic Device working
group
George Bourianoff, Intel
San Francisco, Ca
July 10, 2011
April 10, 2011
2011 ERD Meeting Potsdam, Germany
1
Outline
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Overview
Review transition Table
Table 1
Table 2
Table 3
issues and observations
2
Overview
• Section organization and tables unchanged
from previous edition
• New format for Transition table
• Some Technology Entries changed tables
based on revised classification
• Several new Technology Entries from NRI
• Improved connection to ERM
• Connection to ERA still weak
3
2011 Logic Transition Table
Table ERD6
2009
Table 1
CNT FET
CNT FET
GNR FET
GNR FET
Nanow ire FET
Nanow ire FET
Tunnel FET
transferred from table 2
III-V FET
Com pound III-V chanel FETs
partially transferred to PIDs
Ge FET
Ge N channel MOSFET
renam ed
Unconventional Georm etries
Transferred to PIDs
Spin FET/ Spin MOSFET
Spin FET / Spin MOSFET
IMOS
IMOS
MEMs
MEMs
Table 2
Atom ic Sw itch
New entry
Mot FET
New entry
Ferroelectric FET
transferred to table 3
Tunnel FET
transferred to table 1
SET
dropped - insufficient research activity
Collective Spin Devices
Spin Wave Devices
Nano m agnetic logic
Nano m atgnetic logic
Pseudospintronic
BISFET
Molecular
Table 3
Comment
2011
nam e change
nam e change
insufficient research activity
Excitonic FET
new device concept
Atom ic Sw itch
transferred to table 2
Moving Dom ain Wall
insufficient research activity
Ferroelectric Neg Cg
Transferred and m odified from table 2
Spin Torque Majority gate
All spin logic
new device concept
new device concept
4
Transition table discussion
• Adds clarity
– Unchanged entries – no comment
– Dropped entries – easy to indicate reason
– New entries – show up clearly
– Holding entries for possible future inclusion• easy to indicate
• None in current table
2011 Table 1 MOSFETs Extending MOSFETs
to the End of the roadmap
Table ERD7aMOSFETS: Extending MOSFETs to the End of the Roadmap.”
Device
Nanowire FETs
Density
(device/cm 2 )
Switch Speed
Circuit Speed
Switching
Energy, J
Binary
Throughput,
GBit/ns/cm
2
N channel MOSFETS
P channel MOSFETs
All Si, Ge and silicide
source, VLS
nanowire
N Ge FET
Ga(In)Sb
FET [A]
Si CMOS
CNT FET
Graphene Nanoribbon
FET
100 nm
100 nm
100 nm
Demonstrated
590 nm
1.4μm[G]
1.4μm[G]]
1 µ [N]
20 nm
sub 60
nm[A],60nm[B]
Projected
1.00E+10
1.00E+10
1.00E+10
5.9E+10 [M]
channel down to 20nm
[C, D]: 1E10
Demonstrated
2.80E+08
5.10E+07
5.10E+07
5.2E+07 [M]
not known
Projected
12 THz
7 THz [H]
7 THz [H]
6.5 THz [O]
Si /InAs TFET:
60GHz/3THz [E]
Demonstrated
1.5 THz
300GHz [I]
300GHz [I]
250 GHz [P]
not known
Si/InAs TFET inverter:
20GHz, 1THz [E]
Typical example devices
Cell Size
(spatial pitch)
[B]
Tunnel FET
Projected
40 nm [M]
Projected
61 GHz
not known
not known
100 GHz [Q]
Demonstrated
5.6 GHz
22 kHz [J]
22 kHz [J]
11.7 MHz [R]
not known
TBD
80nm = Lg x 2 [B]
60nm = Lg x 2 [A]
1.5E+10 = 1/(4*Lg^2)
[B]
2.7E+10 = 1/(4*Lg^2) [A]
140GHz [B]
601GHz [A]
Not Known
TBD
10-18 J
TBD
Projected
3.00E-18
not known
not known
4E-20 [S]
Demonstrated
1.00E-16
not known
not known
6.0E-16 [T]
CGG*VDD^2 (J/um)
< 2E-17 [F]
CGG*VDD^2 (J/um) =1E16 [F]
N/A
TBD
Projected
238
not known
not known
5.90E+03
not known
Not Known
TBD
Demonstrated
1.6
not known
not known
6.08E-04
not known
Not Known
TBD
TBD
Operational Temperature
Material Challenges
Research Activity [AD]
RT
Si
RT
CNT density,
contacts
RT
RT
dialectrics, substrates,
Si, Ge, III-V, II-VI,
in situ mobility,
In2O3, ZnO, TiO2, SiC
contacts
330
TBD
RT
RT
not known
Low defect oxide
interfaces
TBD
not known
Not Known
TBD
TBD
6
Table 1 discussion
• Si CMOS reference – which device?
• Demonstrated CNTFET circuit speed increased from 220Hz to
56 MHz
• Demonstrated τs for GNRFET increased from 26 GHz to 300
GHz
• Significant progress on Ge/oxide interface to improve N
channel mobility, short channel, N type Ge MOSFET elusive,
lower resistance contacts needed
• Tunnel FETs: many demonstrations of SS< 60mV/ decade and
Ion/Ioff >105. Low Ion remains problem
2001 Table II –Charge based beyond
CMOS
Japan
EU
EU
Japan
US
Table ERD7b Charge based Beyond CMOS: Non-Conventional FETs and other Charge-based information carrier devices
Device
FET [A]
Spin FET and Spin
MOSFET
I MOS
Typical example devices
Si CMOS
Spin MOSFET
Si, SiGe ([I1-I4]
Projected
100 nm
100nm [L]
100nm
Demonstrated
590 nm
Not known
Projected
1.00E+10
1E10[L]
Demonstrated
2.80E+08
Not known
Projected
12 THz
10 THz or less [N]
Demonstrated
1.5 THz
bCell Size
(spatial pitch) [B]
Density
(device/cm 2 )
Switch Speed
Not known
sub-1000nm [I2-I4]
1.00E+10
<1E7
Limited by carrier
mult. delay (CMD)
and stat. retard.
delay (SRD) [I5-I6]
For IMOS with
Lg=100nm,
CMD=0.6ns,
SRD=1.2ns [I6]
MEM
Atomic Switch
Mott FET
Atomic Switch
MottFET
100nm
40 nm
10nm[1]
sub-1000nm
Not known
1umx150um [2]
>1.00E10 (due to
anchors)
Not known
~1E12
[1/(10nm*10nm)]
>1E8 [M4]
Not known
~6.7E5
[1/(1um*150um)]
~1GHz [M5]
Not known
2THz (0.5ps) [3]
0.18GHz [M6]
~ 2 ns
13.3THz-0.1GHz(75fs9ns) [4]
~1GHz [M5]
Not known
0.18MZ [M6]
Not known
<5E-17 [M7]
Not known
Not known
Not known
polySiGe/metal
[M1], CNT [M2],
TiN [M3]
Similar to CMOS [I7]
Projected
61 GHz
10 GHz or less [N]
Circuit Speed
Switching Energy,
J
limit by CMD &SRD
Demonstrated
5.6 GHz
Projected
3.00E-18
Demonstrated
1.00E-16
Not known
not known
~1E-17 [N]
Similar to CMOS [I7]
Not known
not known
0.1uW [3]
Table II discussion
• Si CMOS reference – which device?
• MEM density increased from ~103/cm2 to >108/cm2
• Atomic Switch: 1011 cycles demonstrated, basic device
physics still not understood
• IMOS entry reflects new fundamental understanding
– Switch speed limited by “multiplication delay”. However, very
steep ST slopes achieved ~2 mV/decade (but at high voltage)
• Spin MOSFET : major progress from use of high quality,
full Haussler alloy, half metal source/drains
• MottFET: Very fast phase transition <<ps observed
Table ERD7C Alternative information
processing devices
Table ERD7C Alternative information processing devices
Spin Wave Devices
State Variable
magnetization
Function
MAJ, NOT
Class—Example
Adders , counters ,
s pecial tas k logic units
(e.g. image proces s ing)
Nanomagnetic
Logic
Magnetization
Boolean Logic
Majority Gate
Excitonic FET
BISFET
Excitonic ins ulator in
the off-s tate,
exis tance or not of
Conventional
s uperfluid excitonic
conductor in the oncondens ate
s tate
Gate enables
trans ition from the
" conventional"
device on-s tate into
the excitonic
ins ulating s tate by
tuning the electron
and hole dens ity to
become identical
Gate controled
negative
differnential
res is tance (NDR)
Steep s ubthres hold
s lope device
s uperconducting,
ps eudos pin
device—BiSFET
Architecture
s ys tolic, non-volatile
Sys tolic/pipelined
Conventional CMOS
Morphic
Application
Boolean and NonBoolean logic
Low power, nonvolatile, radiation
hard
Device for lowpower applications
low power, high
s peed, general
purpos e logic
Comments
Status
Material Issues
allows for parallel data
proces s ing on multiple
frequences (each
frequency as a dis tinct
information channel)
Room Temperature,
GHz frequency
operating prototypes
have been
demons trated
multiferroic materials
W hile drag has been
obs erved [1-4] and
excitons have been
detected in s ys tems
Compatible memory
with s patially
technology: MRAM
s eparated channels
[5-7], the trans ition
to an excitonic
ins ulator has not
been obs erved.
Feas ibility, CMOS
compatible clocking
experimentally
demons trated
Experimental work to
create this device is
ongoing in my
group
MRAM/CMOS
compatible
W e believe that
graphene is ideally
s uited for this
application becaus e
of the s ymmetry of
the electron and
hole dis pers ion
Extremely low
power; 4-phas e
clocked power
s upply
Simulated
Ferroelectric Neg
Cg
Spin Torque
Majority Gate
Charge[8]
Spin wave
frequency
Three terminal
s witch[9]
Performs the
majority logic gate
operation via
phas e locking of
s pin torque
os cillators with a
common
ferromagnetic
nanowire free layer
s pin wave bus [A,
B]
All Spin Logic
Spin/Magnetizatio
n [13]
Non-linear
Median function
[14]
MOSFET[9]
A ferromagnetic
nanowire s pin
wave bus on a
metallic s ubs trate
with s everal
injectors of s pinpolarized current
for s pin-torque
excitation of s pin
waves [C, D]
Switch[9]
Majority logic gate
operation with s pin
waves [E]
Drop in MOSFET
repplacement with
reduced Vdd[9]
Development of
this device will
leverage the s pin
wave device
development effort
becaus e s pin
torque provides
energy-effieicnet
excitation of s pin
waves
Phas e locking of
two s pin torque
proof of concept
os cillators via s pin
demons trated[10,11,
waves in the
12]
common free layer
is demons trated
[A, B]
Morphic
General
purpose/Non
volatile/Reconfigur
able logic [17]
High speed, low
power and zero
standby power
Simulation / some
low temperature
experiments
(a) Spin coherent
channels with
Low defect paired
integration of
reduced
graphene layers
appropriate
NiFe, Cu, Ru, IrMn,
electromigration.
and compatible
ferroelectric with
CoFe, MgO,
(b) Magnets with
thin dielectrics , low
s emiconductors is
CoFeB, Ta
high aniostropy for
res is tance contacts needed[8,9,10,11,12]
low energy
operation [15,16]
Table III Discussion
• 4 new devices from NRI
– Excitonic FET –ultra steep SS, room temperature operation problem
– Spin Torque Majority Gate – 2 types, simulations only
– All Spin Logic- simulations only
• NML: Clocking from fields generated by a metal line clad,
ferromagnetic line, metastable magnetic configurations to
reduce energy
• Ferroelectric negative Cg: Transferred from table 2 and
modified: - SS <60mV/ decade demonstrated, single crystal
ferroelectric oxide on Si an issue
Issues and observations
#
1.
2.
Decisions Made
Memory:
♦ Put Vertical MOSFET in the Memory Section.
Logic:
♦ Leave n-channel Ge and InP MOSFETs and p-channel GaSb
MOSFETs in ERD/ERM
♦ The Tunnel FET should remain in the main Logic Tables and Section.
♦ Nanowire FET stays in ERD/ERM.
♦ Remove molecular from Logic Section – does not meet criteria
♦ Add MOTT-FET to the Logic Section
♦ Remove SET or move SET to the MtM Section
♦ Keep InP and Ge n-channel and GaSb p-channel MOSFETs in the
Logic Section
♦ Add devices from NRI that meet the selection criteria
♦ Do not include Vertical MOSFET in Logic; keep/put in Memory
Section.
♦ Change “Collective Spin Wave? to “Spin Wave”.
♦ Logic Working Group is: Shamik (Nanowires), Adrian (Tunnel
FET),??(InP, Ge, GaSb), Jeff Welser (NRI Devices added), Jeff Kitun?
♦ Include the Spin Torque Majority Gate.
♦ Keep the Atomic Switch in Logic Tables (corrected Feb. 17, 2011)
April 10, 2011
2011 ERD Meeting Potsdam, Germany
13