Chapter 5 MOS Capacitor
MOS: Metal-Oxide-Semiconductor
Vg
Vg
gate
gate
metal
SiO2
SiO2
N+
Si body
MOS capacitor
N+
P-body
MOS transistor
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-1
Chapter 5 MOS Capacitor
P-Silicon body
SiO2
N +polysilicon
Ec
Ec
Ef , E c
Ef
Ev
Ev
Gate
Si
Body
Ev
This energy-band diagram for Vg = 0 is not the simplest one.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-2
5.1 Flat-band Condition and Flat-band Voltage
E0
cSiO2 =0.95 eV
Ec
qg
q s = cSi + (Ec –Ef )
3.1 eV cSi
3.1 eV
=4.05eV
Ec, Ef
Ec
qVfb
Ev
N+ -poly-Si
E0 : Vacuum level
E0 – Ef : Work function
E0 – Ec : Electron affinity
Si/SiO2 energy barrier
9 eV
P-body
4.8 eV
Ef
Ev
The band is flat at
the flat band voltage.
V fb   g  s
Ev
SiO2
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-3
5.2 Surface Accumulation
Make Vg < Vfb
Vg  V fb  s  Vox
3.1eV
Vox
Ec , Ef
s : surface potential, band
Ev
E0
qVg
q s
bending
Vox: voltage across the oxide
Ec
Ef
Ev
M
O
s
is negligible when
the surface is in
accumulation.
S
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-4
5.2 Surface Accumulation
Vox  Vg V fb
Vg <Vt
Gauss’s Law
Vox  Qacc / Cox
Qacc  Cox (Vg  V fb )
Vox  Qs / Cox
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-5
5.3 Surface Depletion ( Vg
>
Vfb )
qVox
++++++
-- -- -- -- -- -- -------depletion layer
2
qVg
Wdep
depletion
region
Ec, Ef
charge, Q dep
P-Si body
Ev
M
Ef
Ev
--
SiO
V
Ec
q s
gate
O
S
qNa 2 s s
Qdep qNaWdep
Qs
Vox  



Cox
Cox
Cox
Cox
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-6
5.3 Surface Depletion
Vg  V fb   s  Vox  V fb   s 
qNa 2 s s
Cox
This equation can be solved to yield s .
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-7
5.4 Threshold Condition and Threshold Voltage
Threshold (of inversion):
ns = Na , or
Ec
st
 A=B, and C = D
kT  N a 
st  2B  2 ln 
q  ni 
C =qB
A
D
(Ec–Ef)surface= (Ef – Ev)bulk , or
Ei
B
qVg = qVt
Ec, Ef
Ev
M
O
S
kT  N v  kT  N v  kT  N a 
 

q B 
 ( E f  Ev ) |bulk 
ln  
ln
ln
2
q  ni  q  N a  q  ni 
Eg
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-8
Ef
Ev
Threshold Voltage
Vg  Vfb φs Vox
At threshold,
kT  N a 
 st  2B  2 ln 
q  ni 
qNa 2 s 2B
Vox 
Cox
qNa 2 s 2B
Vt  Vg at threshold  V fb  2B 
Cox
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-9
Threshold Voltage
Vt (V), P+ gate/N-body
V t(V), N+ gate/P-body
Tox = 20nm
Body Doping Density (cm -3 )
Cox
ody
T = 20nm
+ for P-body,
– for N-body
ox
Modern Semiconductor Devices for Integrated
Circuits (C. Hu)
ody
Vt  V fb  2 B 
qNsub(a)2 s 2 B
Slide 5-10
5.5 Strong Inversion–Beyond Threshold
Vg > Vt
Wdep  Wdmax
2 s 2B

qNa
Vg > Vt
-
gate
---
++++++++++
V
- - - - - - Q dep
Qinv
Ef
Ev
qVg
SiO2
- - - - - - - -
Ec
Ec, Ef
Ev
P - Si substrate
M
O
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
S
Slide 5-11
Inversion Layer Charge, Qinv (C/cm2)
Vg  V fb  2B 
 Vt 
Qdep
Cox
qNa 2 s 2B Qinv
Qinv

 V fb  2B 

Cox
Cox
Cox
Qinv
Cox
 Qinv  Cox (Vg Vt )
Vg > Vt
Vg > Vt
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-12
5.5.1 Choice of Vt and Gate Doping Type
Vt is generally set at a small
positive value so that, at Vg =
0, the transistor does not
have an inversion layer and
current does not flow
between the two N+ regions
• P-body is normally paired with N+-gate to achieve a small
positive threshold voltage.
• N-body is normally paired with P+-gate to achieve a small
negative threshold voltage.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-13
Review : Basic MOS Capacitor Theory
s
2B
accumulation Vf depletion
V
Vg
inversion
t
b
Wdep
Wdmax
Wdmax = (2s2B /qN a )1/2
 (s)1/2
accumulation Vf
b
depletion
V
t
Vg
inversion
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-14
Review : Basic MOS Capacitor Theory
Qdep=- qNaWdep
Vfb
accumulation
depletion
(a)
inversion
0 Vt
–qNaWdep
Vg
total substrate charge, Qs
Qs  Qacc  Qdep  Qinv
–qNaWdmax
Qinv
Qs
accumulation depletion
(b)
Vfb
Vt
inversion
Vg
accumulation
regime
depletion
regime
inversion
regime
slope =  Cox
Vfb
Vg
0 Vt
Qacc
Qinv
slope =  Cox
(c)
Vfb
slope =  Cox
Vt
accumulation depletion
inversion
Vg
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-15
5.6 MOS CV Characteristics
dQg
dQs
C

dVg
dVg
MOS Capacitor
C-V Meter
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-16
5.6 MOS CV Characteristics
dQg
dQs
C

dVg
dVg
Qs
accumulation depletion
regime
regime
inversion
regime
Cox
C
Vfb
Vg
0 Vt
Qinv
slope =  Cox
V
Vt
accumulation fb depletion
inversion
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-17
Vg
CV Characteristics
Cox
Vfb depletion
accumulation
In the depletion regime:
C
Vt
Vg
inversion
1
1
1


C Cox Cdep
1
1 2(Vg  V fb )


2
C
Cox
qN a s
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-18
Supply of Inversion Charge May be Limited
gate
gate
Cox
Cox
++ ++ + ++ ++
C
- - - - - dep
- Wdep
Accumulation
Depletion
P-substrate
P-substrate
gate
gate
Cox
N+
- - - - - - - -
Cox
DC
- - - - - - - - -
C
- - -dmax--
Inversion
DC and AC Wdmax
P-substrate
AC
Inversion Wdmax
P-substrate
In each case, C = ?
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-19
Capacitor and Transistor CV (or HF and LF CV)
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-20
Quasi-Static CV of MOS Capacitor
Cox
accumulation
Vfb depletion
C
Vt
Vg
inversion
The quasi-static CV is obtained by the application of a slow linearramp voltage (< 0.1V/s) to the gate, while measuring Ig with a very
sensitive DC ammeter. C is calculated from Ig = C·dVg/dt. This allows
sufficient time for Qinv to respond to the slow-changing Vg .
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-21
EXAMPLE : CV of MOS Capacitor and Transistor
C
MOS transistor CV,
QS CV
Does the QS CV or the HF
capacitor CV apply?
HF capacitor CV
Vg
(1) MOS transistor, 10kHz.
(Answer: QS CV).
(2) MOS transistor, 100MHz.
(Answer: QS CV).
(3) MOS capacitor, 100MHz.
(Answer: HF capacitor CV).
(4) MOS capacitor, 10kHz.
(Answer: HF capacitor CV).
(5) MOS capacitor, slow Vg ramp. (Answer: QS CV).
(6) MOS transistor, slow Vg ramp. (Answer: QS CV).
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-22
5.7 Oxide Charge–A Modification to Vfb and Vt
Q ox/C ox
Ec
Ef, Ec
Ef, Ec
Vfb0
Ef
Ev
Vfb
Ev
+
+
+
Ec
Ev
Ef
Ev
gate
oxide body
(a)
gate
oxide body
(b)
V fb  V fb0  Qox / Cox   g  s  Qox / Cox
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-23
5.7 Oxide Charge–A Modification to Vfb and Vt
Types of oxide charge:
• Fixed oxide charge, Si+
• Mobile oxide charge, due to Na+contamination
• Interface traps, neutral or charged depending on Vg.
• Voltage/temperature stress induced charge and
traps--a reliability issue
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-24
EXAMPLE: Interpret this measured Vfb dependence on oxide
thickness. The gate electrode is N+ poly-silicon.
Vfb
10 nm
20 nm
30 nm
0
Tox
–0.15V


–0.3V

What does it tell us? Body work function? Doping type? Other?
Solution: V fb   g  s  QoxTox /  ox
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-25
from intercept
 g  s  0.15 V
E0 , vacuum level
g
s = g + 0.15V
Ef , Ec
Ec
Ef
Ev
Ev
N+ -Si gate
Si body
N-type substrate, Nd  n  Nce0.15 eV kT  1017 cm-3
from slope
Qox  1.7 108 C / cm2
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-26
5.8 Poly-Silicon Gate Depletion–Effective
Increase in Tox
Wdpoly   oxEox / qN poly
Gauss’s Law
1
P+ poly-Si
Cpoly
Co x
P+
Ec
Ef
+ + + + + + + + P+
N-body
Ev
(b)
 1

 Tox Wdpoly 
1
 

C 



C

C
s 
ox
poly
  ox



 ox
Tox  Wdpoly / 3
If Wdpoly= 15 Å, what is the
effective increase in Tox?
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-27
1
Effect of Poly-Gate Depletion on Qinv
Qinv  Cox (Vg   poly  Vt )
Wdpoly
Ec
Ef , E v
q poly
• Poly-gate depletion degrades
MOSFET current and circuit speed.
• How can poly-depletion be
minimized?
Ec
Ef
Ev
P+ -gate
N-substrate
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-28
EXAMPLE : Poly-Silicon Gate Depletion
Vox , the voltage across a 2 nm thin oxide, is –1 V. The P+ polygate doping is Npoly = 8 1019 cm-3 and substrate Nd is 1017cm-3.
Find (a) Wdpoly , (b) poly , and (c) Vg .
Solution:
(a)
Wdpoly   oxEox / qN poly   oxVox / Tox qN poly
3.9 8.85 10 (F/cm)  1 V

3
7
19
19
2 10 cm 1.6  10 C  8 10 cm
 1.3 nm
14
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-29
EXAMPLE : Poly-Silicon Gate Depletion
(b)
Wdpoly 
2 s poly
qN poly
2
dpoly  qNpolyWdpoly
/ 2 s  0.11V
(c) Vg  V fb   st  Vox   poly
kT  N c
V fb 

ln
q
q  Nd

  1.1 V  0.15 V  0.95 V

Vg  0.95 V  0.85 V  1 V  0.11 V  1.01 V
Eg
Is the loss of 0.11 V from the 1.01 V significant?
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-30
5.9 Inversion and Accumulation Charge-Layer
Thickness–Quantum Mechanical Effect
Average inversion-layer location below the Si/SiO2 interface is
called the inversion-layer thickness, Tinv .
Electron Density
Gate
poly-Si
depl eti on
region
SiO2
Tinv
Si
Quantum
mechanical theory
-50 -40 -30 -20 -10
0
10
20
30
40
Å
50 A
Physical Tox
Effective Tox
n(x) is determined by Schrodinger’s eq.,
Poisson eq., and Fermi function.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-31
Electrical Oxide Thickness, Toxe
• Tinv is a function of
the average electric
field in the inversion
layer, which is (Vg +
Vt)/6Tox (Sec. 6.3.1).
• Tinv of holes is larger
than that of electrons
because of difference
in effective mass.
•Toxe is the electrical
oxide thickness.
Toxe  Tox  Wdpoly / 3  Tinv / 3 at Vg=Vdd
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-32
Effective Oxide Thickness and Effective
Oxide Capacitance
Qinv  Coxe (Vg  Vt )
Toxe  Tox Wdpoly / 3 Tinv / 3
C
Basic CV
Cox
with poly-depletion
with poly-depletion and
charge-layer thickness
measured data
Vg
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-33
Equivalent circuit in the depletion and the inversion regimes
C p oly
Cox
Co x
Cdep
Cp oly
Cox
Co x
Cdep
Cin v
(a)
General case for
both depletion and
inversion regions.
Cdep, min
(b)
In the depletion
regions
Cinv
Cinv
(c)
Vg  Vt
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
(d)
Strong inversion
Slide 5-34
5.10 CCD Imager and CMOS Imager
5.10.1 CCD Imager
-
Ec
Ef
--
Ev
+
Ec, E f
Ec , Ef
Ev
Ev
(a)
(b)
Deep depletion, Qinv= 0
Exposed to light
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-35
CCD Charge Transfer
V3
V2
V1
V1 > V2 = V3
(a)
- - - - -
depletion region
oxide
- - -
- - - - - -
P-Si
V1
V2
V3
V1
V3
V2
V1
V2 > V1 > V3
oxide
- - - - -
(b)
depletion region
- - -
P-Si
V1
V2
V3
V1
V2
V3
V1
V2 > V1 = V3
(c)
- - - - -
oxide
depletion region
- - -
P-Si
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-36
two-dimensional CCD imager
Signal out
Reading row,
shielded from light
Charge-to-voltage converter
The reading row is shielded from the light by a metal film.
The 2-D charge packets are read row by row.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-37
5.10.2 CMOS Imager
PN junction
charge
collector
switch
V1
Amplifier
circuit
V2
V3
Shifter circuit
CMOS imagers can be
integrated with signal
processing and control
circuitries to further
reduce system costs.
However, The size
constrain of the sensing
circuits forces the CMOS
imager to use very
simple circuits
Signal out
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-38
5.11 Chapter Summary
N-type device: N+-polysilicon gate over P-body
P-type device: P+-polysilicon gate over N-body
V fb  g  s  (Qox / Cox )
Vg  V fb  s  Vox   poly
 V fb  s  Qs / Cox   poly
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-39
5.11 Chapter Summary
st  2B or  (B  0.45 V)
kT N sub
B 
ln
q
ni
qNsub 2 s |  st |
Vt  V fb   st 
Cox
+ : N-type device, – : P-type device
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-40
Accumulation
Flat-band
Vg<Vfb<0
Vg>Vfb>0
Vg=Vfb>0
Ef Vg=Vfb<0
Ef
5.11 Chapter Summary
N-type Device Eff
(N+-gate over P-substrate)
Ef
Vg0>Vfb
Ef
P-type Device
(P+-gate over N-substrate)
Eff
Flat-band
Depletion
Vg=Vfb<0
Ef
Ef
Ef
Ef
Vg=Vfb>0
Ef
Vg0<Vfb
Ef
Ef
Ef
Depletion
Vg0>Vfb
Ef Vg=Vt>0
Vg0<Vfb
Vg=Vt <0
Threshold
Ef
Ef
Ef
Ef
Ef
Ef
Ef
Threshold
Inversion g
What’s the diagram like at V > VVg=Vt ?t<0 at Vg= 0?
Vg=Vt>0
Ef
Vg>Vt>0
Ef
Vg<Vt
E
f
Modern Semiconductor Devices
for Integrated
Ef Circuits (C. Hu)
Ef
Slide 5-41
Ef
5.11 Chapter Summary
+
N-type Device
P-type Device
+
(N -gate over P-substrate)
(P -gate over N-substrate)
QS CV
Transistor CV
Capacitor
(HF) CV
Vg
Vg
What is the root cause of the low C in the HF CV branch?
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-42