IEE5011 – FALL 2013
Memory Systems
LPDDR3 DRAM for Mobile Applications
Balakumar
Department of Electronics Engineering
National Chiao Tung University
balakumar.meirtt@gmail.com
Balakumar
January16, 2014
Outline
 Motivation
 PC Like Performance
 Mobile DRAM Evolutionary Path
 LPDDRx (Across generations)
 LPDDR3
 ISM (Inner Stack Memory Module)
 Comparison with Wide I/O
 Samsung LPDDR3
 Conclusion
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Motivation
Energy efficiency is the major optimization criteria
for systems-on-chip (SoCs) for mobile devices
(smartphones and tablets).
Performance and power consumption of DRAMs
(LPDDRs) depends on the configuration of system
level parameters, such as operating frequency,
interference bandwidth, request size, and memory
map.
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What is PC-Like Memory Performance
Memory implementation by manufacturer
Number of bits in DRAM interface/interface data rate
Computer
Type
Price Range
Company
1
Tablet / Small
$300-$500
64/800**
Thin % Light
$500-$700
64/1600
Entry Laptop
$450-$500
Power Laptop
Company
3
Company
4
Company
5
128/800*
*
128/
1333**
128/800**
64/1600
64/
1333**
64/1333**
64/1333
128/1333
128/
1333**
128/1333
$1250$1500
128/1600
**
128/1600
128/
1333**
128/1600
Entry Desktop
$275-$330
64/1600
64/1600
128/
1333*
64/1333
Power
Desktop
$1200$2500
256/1333
256/1600
128/
1333**
128/1600
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Company
2
128/1600
192/1333
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Common PC Configurations
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System Performance Trend (PC vs Smartphone)
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Mobile DRAM Evolution
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Future Mobile DRAM Positioning
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MDRAM will Exceed PC DRAM Performance
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Mobile DRAM Density Requirement
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Memory PKG Trend for Smartphone Application
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Mobile Application Thickness Trend
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Low Power Memory - Today
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Low Power DRAM- Features
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Low Voltage
Low I/O Capacitance
Unterminated I/Os
Typically x16 orx32 data width per die
Multi-die packages
No DLL
Very Low Standby Power
Temperature Compensated in Standby mode
Deep Power Down mode
Partial Array Self- Refresh
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Low Power LPDDR vs Low Voltage DDR3L
 DDR3L is a Lower Voltage version in PC DRAM
 LPDDR3 is used in Mobile Devices
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LPDDR2 to LPDDR3 Migration
Increase bandwidth 50% LPDDR2-1066
- From 8.5GB/s to 12.8GB/s
 Fast time-to market
- Re-use existing LPDDR2 infrastructure
- No change or limited changes to interface, command protocol, state
machine, etc.
- Only changes which enables higher speed operation should be
considered.
- SOC vendors and DRAM vendors should re-use as much as
possible from LPDDR2 in order to meet very aggressive time-to-market.
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LPDDR3-Key Features Comparison
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LPDDR3-Addressing
Overlap between LPDDR2/3 at 4-8GB
- Same addressing for maximum IP re-use from LPDDR2
Additional 16GB & 32GB definitions
- 32GB TBD- feasibility still to be determined.
- 16GB addressing defined, but refresh requirements still TBD.
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LPDDR3-Mobile Platform
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LPDDR3-Power
 LPDDR2 LPDDR3: no change in VDD
 Larger Pre-fetch, higher R/W Power.
 Faster tCK: Higher IO Power.
Low-Power DRAM?
- Power efficiency (pJ/bit) improvement with higher performance- performance
increase out-gains power increase
- 2-ch LPDDR2 delivers 8.3GB/sec at 533MHz, approx 11.9pJ/bit
- 2-ch LPDDR3 delivers 12.8GB/sec at 800MHz, approx 9.2pJ/bit
- Higher performance also allows for faster data transfer of fixed quantity resulting in
longer idle time for additional power savings.
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LPDDR3-Low Power Features
 TCSR- same feature as LPDDR2
 PASR- same as LPDDR2 (identical bank & segment
masking as S4)
 DPD- supported
 Power-down mode
 Self-refresh mode
 New Requirements
- tCPDED required for PD/SREF/DPD entry
- tMRRI required upon PD exit
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LPDDR3-Low Power Mode Changes
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LPDDR3-Memory Partitioning Concept
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LPDDR3-System Design Considerations
 Signal Integrity is significantly affected by these parameters.
- CIO (capacitance)
- Driver slew rate
- Package design
- Power delivery (key in PoP implementation)
 Great care must be taken to design a system that has good signal
integrity at 1600 MT/s with this PHY
 It is highly recommended to work with memory vendors to model
your system using extracted driver and package parameters.
 Additional features can be employed to improve signal margin.
- DQ on Die Termination (ODT)
- Asym drive strength
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LPDDR2 and LPDDR3 (PoP)
 Package-on-Package offers low power and area
 Compared to packaged parts on PCB, PoP can reduce power, area and volume
- Short Paths with relatively good signal integrity properties.
- Saves PCB area by using vertical direction.
- May lead to thermal issues if fie underneath is generating heat
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Challenges in Mobile DRAM Channel
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ISM (Inner-Stack Memory Module)
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2-channel ISM design for LPDDR2/3
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Understanding LPDDR3 and Wide I/O
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Finding Ideal PCB Environment
Pop provides very short Electrical Connection for
high speed and low power
- Power dissipation is limited
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SoC Construction
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LPDDR3 vs Wide I/O
Attribute
LPDDR3 2 Channel
Wide I/O
Peak Bandwidth
102Gbit/s
102Gbit/s
Core power
Predicted to be similar for both technologies
I/O Voltage
1.2V
1.2V
I/O Capacitance
1.8pF
0.5pF
Full-bandwidth, all chip
I/O Power (a/2 fcv2)
64*0.5*1600*fcv2=
51200cv2
512*0.5*200*fcv2=
51200cv2
First-order approximation Difference in IO is proportional to c
Power down, Self-Refresh One power state for each
and DPD capability
channel per die, 1-2
channels per system
4 channels per die
SoC Power
DLL/PLL not required
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PHY may require DLL/PLL
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Samsung LPDDR3 Review
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Gain exceptional design advantages

Benefits of using Samsung Mobile DRAM in computing, consumer,
and communication devices include:
• Reduced power consumption in standby mode enabled by advanced, on-chip
technologies such as temperature-compensated self-refresh (TCSR).
• Extended battery life in operational mode with power consumption as low as
1.2V.
• High operational speeds that keep pace with today´s fast mobile CPUs and
large displays, enabling users to power through demanding applications and
multitasking.
• Design flexibility with a choice of thin, small form-factor packages that occupy
very little board space.
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Samsung LPDDR3 DRAM
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Conclusion
Future DRAM bandwidth will continue to increase
Power is reduced in LPDDR3, but still proportional
to bandwidth.
Use multiple techniques to meet performance and
power goals of high bandwidth low power DRAM.
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Refrence
1.
2.
3.
4.
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6.
7.
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Kwang-Il Park; Jung-Hwan Choi; Jung-Bae Lee; Joo-Sun Choi, "A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O
interface with LowVoltage-Swing Terminated Logic and adaptive calibration scheme for mobile application,"
VLSICircuits (VLSIC), 2013 Symposium on , vol., no., pp.C240,C241, 12-14 June 2013.
A. B. Kahng and V. Srinivas, “Mobile System Considerations for SDRAM Interface Trends,” in Proc. SLIP, 2011.
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Weis, C.; Loi, I.; Benini, L.; Wehn, N., "Exploration and Optimization of 3-D Integrated DRAM Subsystems," ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.32, no.4, pp.597,610, April 2013.
Gomony, M.D.; Weis, C.; Akesson, B.; When, N.; Goossens, K., "DRAM selection and configuration for real-time
mobile systems," Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012 , vol.,no., pp.51,56, 1216 March 2012 doi: 10.1109/DATE.2012.6176432.
“JEDEC Low Power Double Data Rate (LPDDR3) SDRAM Standard,” Sep 2011.
“JEDEC Low Power Double Data Rate (LPDDR2) SDRAM Standard,” Dec 2010.
“JEDEC Low Power Double Data Rate (LPDDR) SDRAM Standard,” Feb 2009.
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Reference
10. B. Akesson et al., “Memory Controllers for High-Performance and Real-Time MPSoCs,” in Proc. CODES+ISSS, 2011.
11. JEDEC Standard Wide IO SDR specification. Dec. 2011.
12. Y.C. Bae, et al. “A 1.2V 1.6Gb/s/pin 4Gb Low Power DDR3 SDRAM with Input Skew Calibration and Enhanced
Refresh Control Schemes” IEEE ISSCC, pp. 44-45, Feb. 2012.
13. Park, S.-S. et ai, "Integrated circuit package-inpackage system with side-by-side and offset packaging, US patentNo.
US 7,812,435 B2.
14. http://www.samsung.com/global/business/semiconductor/product/mobile-dram/overview.
15. http://www.samsung.com/global/business/semiconductor/news-events/pressreleases/detail?newsId=12979.
16.
https://memorylink.samsung.com/ecomobile/mem/ecomobile/product/productOverview.do?topMenu=P&subMenu=mob
ileDram&partSetNo=LPDDR3&partSetLabel=LPDDR3.
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