Development of fast
electronics for the
GRAPES-3
experiment at Ooty
K.C. RAVINDRAN
On Behalf of GRAPES-3
Collaboration
K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY
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FAST Electronics DEVELOPMENT AND
PERFORMANCE
• 8 Channel Discriminator
• 8 Channel Combined Amplifier and
discriminator
• 32 Channel Time to Digital Converter (TDC)
• 32 Channel High Performance TDC (HPTDC)
• 4 Fold Logic Unit
GENERAL
• Quad Gated Scaler
• JTAG protocol in Parallel port
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Basic elements for each scintillation
detector
Philips TDC
GRAPES TDC
Needs JTAG
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8 Channel discriminator module
development
• Dual comparator by Analog Devices
(AD96687)
• Characteristics
–
–
–
–
Propagation delay = 2.5 ns,
Dispersion = 50 ps (for overdrive 100mV - 1V)
ECL outputs
Power dissipation: 118 mW per channel
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Performance of discriminator
Philips TDC
Model- 7186
Muon
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TDC Resolution- 25ps
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Time distribution with muon trigger
FWHM=4.9ns
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Relative time distribution of 2 channels of
GRAPES discriminator
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Relative time distribution between Lecroy
and GRAPES discriminator
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SUMMARY
• The timing error 125 -135 ps with muon trigger
– represents combined statistical widths of two separate
distributions
– Timing error due to intrinsic width of GRAPES discriminator
is ~ 100 ps
• Intrinsic double pulse resolution of GRAPES
discriminator is 4 ns
• Future Upgrade
•
•
•
Maxim comparator MAX9693EPE
• Propagation delay =1.2ns
• Delay dispersion = 150ps (for overdrive: 10mv-100mv)
• ECL outputs
• 350mW per channel
Sample IC is being tested , same pin configuration
Cost effective & expect better performance
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GRAPES Discriminator Module
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Development of Fast Amplifiers
Specifications
AD8350-20
LMH6626
Manufacturer
Analog
National
Bandwidth
at Gain=10
700 MHz.
200 MHz
Slew Rate
2000V / μs
350V / μs
Input Impedance
200 Ω
4.6 kΩ
Output Impedance 200 Ω
10 mΩ
K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY
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Performance of Combined GRAPES Amplifier &
Discriminator Module
Muon
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Performance: Timing response to Muons
Philips
Philips
GRAPES-8350
σ =3ns
σ =3.1ns
K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY
GRAPES-LMH6626
σ =3ns
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Intrinsic timing response using Muons
Difference distribution
Philips & GRAPES-8350
σ=128ps
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Difference distribution
Philips & GRAPES-LMH6626
σ=178ps
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Summary
• Fast intrinsic timing response of ~125 ps
– Timing response comparable to commercial module
• Standard NIM Module
• Highly customized (but still modular) to GRAPES
needs
– On-board NIM/TTL converter with monoshots
– Multiple buffered outputs as per our experimental
requirement
• Highly cost effective
• No delays in repair
• Low power consumption
– Almost half compared to commercial modules
• Amplifier and Discriminator in same module
– Cost saving on connectors
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8-Channel GRAPES LMH6626 Amplifier & Discriminator
Module
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Time to Digital Converter (TDC) Development
 Based on TDC32 ASIC Chip
Developed by Micro Electronics Group of
CERN, Geneva
Trigger mode operation
 Multi-hit capability
 Number of channels: 32 + 1 Common start
 Time resolution = 520ps @60MHz
 Dynamic range: 21 bits
 Double pulse resolution: 15ns
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Block Diagram of Calibration Setup
Calibration Module
PHILLIPS TDC Module
START
40MHz
START
32MHz
25MHz
STOP
20MHz
FANOUT
Module
FANOUT
Module
16MHz
Ch. 1
Ch. 2
Ch. 16
10MHz
GRAPES TDC Module
START
Selection of Crystal
Number of Samples
Interval between samples
Max Delay
Ch. 1
Ch. 2
Ch. 32
Control Signals from Computer
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Non-linearity of TDC
Phillips
GRAPES TDC
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GRAPES and PHILLIPS TDCs with real data!
EAS DATA OF SAME CHANNEL
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GRAPES TDC32 Module
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Further TDC Upgrade plans
TDC32
HPTDC
 Resolution
 Basic clock 40 MHz
depends on clock In built PLL-programable
max 60 MHz
 resolution programmable to
24 ps (8 ch), 98 ps, 195 ps &
781 ps
 At 60 MHz 520 ps




86 pin PLCC package
TTL standard
Power: 5 V
127 bits of data in
JTAG protocol





225 pin BGA package
LVDS & LVTTL
Power: 2.5 V and 3.3 V
~1K bits of data to program
Highly flexible
 programming complexity
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Development of Logic Unit
• Flexible Four fold logic unit
– Logic AND/OR operation
• Low propagation
delay(16ns)
• Multiple NIM outputs with
either polarity
• Provision of Veto
• Inputs: switch selectable
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QUAD gated scalar
• Four independent, 8 digit
channels
• Maximum input frequency=3 MHz
• Operation with TTL or NIM inputs
• Gated timer mode operation
• Selectable timer 1-9999 s
• Carry available for cascading the
counters
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R&D work in progress
• HPTDC work
 PCB ready
 225 pin BGA chip mounted & PCB wired - start
testing
• Testing the Amplifier with LMH6703 and
integrating with discriminator MAX9693
 Amplifier tested in wired board - bandwidth 400
MHz measured at gain 10
 Test MAX9693
 Design and fabricate PCB and avoid Lemo
connectors
• QDC development in progress
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THANKS
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PCI Interface card
• The PC’s which are available now does not have ISA
bus support
• ALS systems manufactures prototyping PCI cards
• The local address bus , data bus and control signals like
read and write are available to user
• We could read data at 1 µs / word using this card in our
DAS
• A common PCI Interface card designed and wired and
used in all our DAS at Grapes-3
• This card costs around Rs 5,500/- and the card from
Japan PCI-7200 which is a PCI, I/O card costs around
Rs 12,000/-
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THANKS
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CABLE ATTENUATION/100 m
100 METER CABLE COMPARISION
Frequency in MHz
0
0
100
200
400
300
500
-5
-10
Attn. in dB
-15
5D2
V
-20
-25
-30
RG58/U
-35
-40
-45
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Comparison of power requirement
for Phillips and CRL module
Power
supply
Voltage
+6
Philips 16 ch
Amp 776
Current mA
Phillips 16 ch CRL 8 Ch
Disc.706
Amp-Disc
Current mA
Current mA
320
400
700
-6
320
450
500
+12
150
50
-12
150
165
+24
-
80
-24
-
80
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Trigger Rate at Grapes-3 with ~400
scintillation detectors
•
•
•
•
Level-0
Level-1
Calibration
Pedestal
~ 100 Hz
~ 28 Hz
~ 5 Hz
~ 1 Hz
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