ICECS 2010
First Order Noise Shaping
Time-to-Digital Converter
Francesco Brandonisio,
Prof. M. P. Kennedy and
Prof. F. Maloberti (University of
Pavia, Italy)
12th Dec. 2010
Department of Microelectronic
Engineering, University College Cork and
Tyndall National Institute, Ireland
1/21
www.tyndall.ie
Motivations
• Goal: Increase the resolution of a TDC by means
of noise shaping of the quantization error.
• Application: All-Digital PLLs (ADPLLs).
2/21
www.tyndall.ie
Table of contents
• Architectures of ADPLLs and Time-to-Digital Converters (TDC).
• State of Art: Gated Ring Oscillator based TDC (GRO TDC).
• Our Architecture: Local Oscillator based TDC (LO TDC).
• Theoretical work the LO TDC.
• Simulink and Verilog-AMS models of TDCs.
• Experimental setup and measurements.
3/21
www.tyndall.ie
Traditional Phase Locked Loop (PLL)
• Applications: frequency synthesizers, trasmitters and
receivers for telecommunication systems.
4/21
www.tyndall.ie
TDC based ADPLL
Phase measure
Feedback loop
• PFD, loop filter and VCO replaced by digital equivalents.
• The TDC measures the phase error between the output signals
of the reference oscillator and divider.
[1] C.M. Hsu, Member, M. Z. Straayer, M. H. Perrott, “A Low-Noise Wide-BW 3.6-GHz Digital ∆Σ Fractional-N Frequency
Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation,” IEEE J. SolidState Circ., vol. 43, no. 12, pp. 2776-2786, Dec. 2008.
5/21
www.tyndall.ie
Phase accumulator based ADPLL
• The phase error is generated by means of the difference between
the reference and feedback phase signals.
• Phase accumulators generate the phase signals directly.
[2] R. B. Staszewski, P, T. Balsara , “Phase-Domain All-Digital Phase-Locked Loop,”IEEE trans. on circuits
and systems-II: express briefs, vol. 52, no. 3, Mar. 2005.
6/21
www.tyndall.ie
Time-to-Digital Converter
• A TDC uses a reference time interval to measure an unknown time
interval.
7/21
www.tyndall.ie
Types of Reference Time Interval
• Delay of a delay element: Delay-line based TDCs.
• Period of an oscillator: Oscillator based TDCs
8/21
www.tyndall.ie
Quantization Noise in TDCs
• A TDC introduces quantization noise resulting from the finite resolution (res).
• The Signal-to-Noise Ratio is decreased.
9/21
www.tyndall.ie
First Order Noise Shaping TDCs
• First order noise shaping of the quantization noise improves the SNR
10/21
www.tyndall.ie
Gated Ring Oscillator TDC: concept
• Start and stop the oscillator.
• You need to preserve the state of the oscillator.
11/21
www.tyndall.ie
Gated Ring Oscillator TDC: circuit
Charge
Redistribution:
extra circuitry
required
• Noise shaping.
• Multi-stage architecture: the reference time interval is the delay of a
CMOS inverter.
[3] B. Helal, M. Straayer, M. Perrott, “A Low Jitter 1.6 GHz Multiplying DLL Utilizing a Scrambling Time-toDigital Converter and Digital Correlation,” VLSI Symp. Dig. Tech. Papers, pp. 166-167, June 2007
12/21
www.tyndall.ie
Local Oscillator based TDC (our solution)
The time interval
that has to be
mesured is the
period of the input
signal
• Consecutive time intervals.
• The local oscillator keeps oscillating.
[4] F. Brandonisio, F. Maloberti, “An All-Digital PLL with a First Order Noise Shaping Time-to-Digital
Converter,” Proc. of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 241-244
13/21
www.tyndall.ie
LO TDC: Block Diagram
No Charge
Redistribution
Single-stage LO TDC
• No specific requirements for the architecture of the local oscillator.
• Same equations of a GRO TDC!
• Simple!
Multi-stage LO TDC
• Extra counters to increase the resolution.
14/21
www.tyndall.ie
The system "LO TDC + Filter"
Assume the system
"LO TDC plus
moving average
filter"
For a constant
input it is possible
to demonstrate
that:
15/21
www.tyndall.ie
Simulation Models
Verilog-AMS
Simulink
• Embedded
Matlab
Functions
• Triggered
Subsystems
• Simulation
Clock Source
Block
Quick data processing and testing
• Custom
models with
"electrical"
data types
• Event
detection
functions
• Current
Simulation
Time
Transistor Level Libraries
Types of Models
• Exact: analytical equations and events.
• More Realistic: Flip-Flops, counters, digital gates, oscillators.
16/21
www.tyndall.ie
Simulated Characteristics
• The simulation
results of our
Verilog-AMS and
Simulink models
are identical.
Input-output characteristics of the system
"first order noise shaping plus filter"
• The models are
implementable on
a Xilinx Virtex 5
17/21
www.tyndall.ie
LO TDC on FPGA
• The frequency
of the Local
Oscillator is
1.91667 MHz
• The moving
average filter is
implemented in
Matlab
18/21
www.tyndall.ie
Resolution of the System "LO TDC + filter"
from Predictions, Simulations and Experiments
• The Reference
Period is equal to
about 400 ns.
• Good matching
between analytical
predictions,
simulations and
experiments.
19/21
www.tyndall.ie
Experimental Results: Spectrum
• Good matching
between simulated
and measured
spectra
• All the largest
amplitude tones are
reproduced by the
simulations.
20/21
www.tyndall.ie
Conclusions
• We introduced the architecture of the LO TDC.
• We derived analytical equations to predict the resolution of
the system "LO TDC plus moving average filter".
• We developed Verilog AMS and Simulink models of our TDC.
• We verified the analytical predictions and simulations
related to the resolution of the the system "LO TDC plus
moving average filter" with experimental measurements on
Xilinx Virtex-5.
• An ADPLL with an LO TDC on Virtex-5 is under development.
21/21
www.tyndall.ie
References
[1] C.M. Hsu, Member, M. Z. Straayer, M. H. Perrott, “A Low-Noise Wide-BW 3.6-GHz
Digital ∆Σ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital
Converter and Quantization Noise Cancellation,” IEEE J. Solid-State Circ., vol. 43, no.
12, pp. 2776-2786, Dec. 2008.
[2] R. B. Staszewski, P, T. Balsara , “Phase-Domain All-Digital Phase-Locked
Loop,”IEEE trans. on circuits and systems-II: express briefs, vol. 52, no. 3, Mar. 2005.
[3] B. Helal, M. Straayer, M. Perrott, “A Low Jitter 1.6 GHz Multiplying DLL Utilizing a
Scrambling Time-to-Digital Converter and Digital Correlation,” VLSI Symp. Dig. Tech.
Papers, pp. 166-167, June 2007.
[4] F. Brandonisio, F. Maloberti, “An All-Digital PLL with a First Order Noise Shaping
Time-to-Digital Converter,” Proc. of the 2010 IEEE International Symposium on
Circuits and Systems (ISCAS 2010), pp. 241-244.
[5] F. Brandonisio, M. P. Kennedy, F. Maloberti, “First Order Noise Shaping LocalOscillator Based Time-to-Digital Converter,” To be published on Proc. of the 17th IEEE
International Conference on Electronics, Circuits, and Systems, (ICECS 2010).
www.tyndall.ie
Acknoledgments
Thanks to Science Foundation Ireland
and to
FIRB, Italian National Program, Project RBAP06L4S5.
Thanks for listening!
www.tyndall.ie