Overview
Why VLSI?
 Moore’s Law.
 The VLSI design process.

These lecture notes include my annotations, changes and additions.
These annotations, changes, and additions marked in red are not in
any way endorsed or approved by the author or publisher of the
text, Modern VLSI Design/System-on-Chip Design.
A. Yavuz Oruc, University of Maryland, College Park, MD 20742
Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Why VLSI?

Integration improves the design and fabrication:
– lower parasitics (capacitive charging, resistive
dissipation) = higher speed;
– lower power (smaller devices+ less heat dissipation at
the interface);
– physically smaller.


Integration reduces manufacturing cost-(almost)
no manual assembly.
Integration also increases system reliability by
reducing component interface and
interconnections
Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
VLSI and you

Microprocessors:
– personal computers;
– microcontrollers.
– Hand-held devices-wireless phones, pdas,video
cameras,etc…
DRAM/SRAM Memory chips
 Special-purpose processors.

Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Moore’s Law
Gordon Moore: co-founder of Intel
 Predicted that number of transistors per chip
would grow exponentially (double every 18
months).
 Exponential improvement in technology is a
natural trend: steam engines, dynamos,
automobiles.

Modern VLSI Design 3e: Chapter 1
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Moore’s Law(Cont’d)






Q(n) = 2  Q(n-1.5) =>
Q(n) = 2k  Q(n-1.5k),
Q(0) = Q0 (some initial value at some initial date)
=> k= n/1.5 and
Q(n) = Q0  2n/1.5 = Q0  2n/1.5
= Q0  (1.333)n
If we replace 1.5 by 1 we get a much steeper rise
(2n). (Count doubles every year…)
Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Moore’s Law(Cont’d)
Number of Transistors (Predicted)
Number of transistors in Intel Processors
60000000
50000000
40000000
30000000
20000000
10000000
0
1965
1970
1975
1980
1985
1990
1995
2000
2005
2010
Years
Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Moore’s Law(Cont’d)
ftp://download.intel.com/museum/Moores_Law/Printed_Materials/Moores_Law_Backgrounder.pdf
For a more complete list of intel processors and their features, see
http://en.wikipedia.org/wiki/List_of_Intel_microprocessors
Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Moore’s Law(Cont’d)
Number of Transistors-Predicted (Blue) and Actual (Pink)
700000000
Number of transistors
600000000
500000000
400000000
300000000
200000000
100000000
0
1965
1970
1975
1980
1985
1990
1995
2000
2005
2010
years
Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Moore’s Law plot
Log # transistors
This is a log plot--- Taking the log of the formula for Q(n) gives a linear
relation between the years and log of number of transistors: Log Q(n)
= Log Q0 + n  Log 1.333 (See slide 5)
Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
The cost of fabrication
Current cost: $2-3 billion.
 Typical fab line occupies about 1 city block,
employs a few hundred people.
 Most profitable period is first 18 months-2
years.

Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Cost factors in ICs

For large-volume ICs:
– packaging is largest cost;
– testing is second-largest cost.

For low-volume ICs, design costs may
swamp all manufacturing costs.
Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
The VLSI design process


May be part of larger product design.
Major levels of abstraction:
– specification; (describe functionality)
– architecture; (describe functionality with building
blocks)
– logic design; (convert architecture to logic circuits)
– circuit design; (convert logic logic circuits to transistor
circuits)
– layout. (lay out the transistor circuits in VLSI)
Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Challenges in VLSI design
Multiple levels of abstraction: transistors to
CPUs.
 Multiple and conflicting constraints: low
cost and high performance are often at odds.
 Short design time: Late products are often
irrelevant.

Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Dealing with complexity
Divide-and-conquer: limit the number of
components you deal with at any one time.
 Group several components into larger
components:

–
–
–
–
transistors form gates;
gates form functional units;
functional units form processing elements;
etc.
Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Hierarchical name

Interior view of a component:
– components and wires that make it up.

Exterior view of a component = type:
– body;
– pins.
cout
a
b
Modern VLSI Design 3e: Chapter 1
Full
adder
sum
cin
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Instantiating component types

Each instance has its own name:
– add1 (type full adder)
– add2 (type full adder).

Each instance is a separate copy of the type:
cout Add2.a
Add1.a
a Add1(Full
adder)
b
Modern VLSI Design 3e: Chapter 1
sum
a Add2(Full
adder)
b
cin
sum
cin
Copyright  1998, 2002 Prentice Hall PTR
A hierarchical logic design
Incomplete--- not enough labels to specify the netlist and
component list on the next slide (Component terminal counts
do not appear to match either!)
box1
box2
x
z
Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Net lists and component lists

Net list: (list of
terminals in a net)
net1: top.in1 in1.in
net2: i1.out xxx.B
topin1: top.n1 xxx.xin1
topin2: top.n2 xxx.xin2
botin1: top.n3 xxx.xin3
net3: xxx.out i2.in
outnet: i2.out top.out
Modern VLSI Design 3e: Chapter 1

Component list (nets
connected to each pin of a
component):
top: in1=net1
n1=topin1 n2=topin2
n3=topin3 out=outnet
i1: in=net1 out=net2
xxx: xin1=topin1 xin2=topin2
xin3=botin1 B=net2
out=net3
i2: in=net3 out=outnet
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A hierarchical logic design
p
i1
i1
o1
i1 N
A
o1
i2
o2
top
q
o1 s
B
o1
C
o2
t
i2
r
Inserted & modified the labels
Modern VLSI Design 3e: Chapter 1
i1
Copyright  1998, 2002 Prentice Hall PTR
Net lists and component lists
Two-level net list:
Two-level component list
Level-1has 2 components, top and C, which appear on 6 nets:
Level-1 has 2 components, top and C and they are on the following
nets:
top = net11, net12, net13,net14,net15
C= net15, net16
net11: top.p
net12: top.q
net13: top.r
net14: top.s, C.i1
net15: top.t C.i2
net16: C.o1
Level-2 has 3 components: A, N and B, which appear on 7 nets
Level-2 has 3 components, A, N, and B, and they are on
the following nets
A = net21, net22
B = net23, net24, net25
N = net26, net27
net21: top.p, A.i1
net22: top.q, A.o2
net23: top.r, B.i2
net24: top.s, B.o1
net25: top.t, B.o2
net26: A.o1, N.i1
net27: B.i1, N.o1
Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Component hierarchy
top
i1
Modern VLSI Design 3e: Chapter 1
xxx
i2
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Hierarchical names

Typical hierarchical name:
– top/i1.foo
component pin
Modern VLSI Design 3e: Chapter 1
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Layout and its abstractions

Layout for dynamic latch: (Top view)
Modern VLSI Design 3e: Chapter 1
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Stick diagram
Modern VLSI Design 3e: Chapter 1
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Transistor schematic
Modern VLSI Design 3e: Chapter 1
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Mixed schematic
inverter
Modern VLSI Design 3e: Chapter 1
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Levels of abstraction
Specification: function, cost, etc.
 Architecture: large blocks.
 Logic: gates + registers.
 Circuits: transistor sizes for speed, power.
 Layout: determines parasitics.

Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Circuit abstraction

Continuous voltages and time:
Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Digital abstraction

Discrete levels, discrete time:
QuickTime™ and a
TIFF (Uncompressed) decompressor
are needed to see this picture.
Least
significant bit
1+1=2
Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Register-transfer abstraction

Abstract components, abstract data types:
0010
+
0001
+
0111
0100
Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Top-down v.s. bottom-up design

Top-down design adds functional detail.
– Create lower levels of abstraction from upper
levels.
Bottom-up design creates abstractions from
low-level behavior.
 Good design needs both top-down and
bottom-up efforts.

Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Design abstractions
English
Executable
program
function
Sequential
machines
Logic gates
specification
behavior
Throughput,
design time
registertransfer
Function units,
clock cycles
logic
Literals,
logic depth
transistors
circuit
Nanoseconds
power
rectangles
layout
microns
Modern VLSI Design 3e: Chapter 1
cost
Copyright  1998, 2002 Prentice Hall PTR
Design validation
Must check at every step that errors haven’t
been introduced-the longer an error remains,
the more expensive it becomes to remove it.
 Forward checking: compare results of lessand more-abstract stages.
 Back annotation: copy performance
numbers to earlier stages.

Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Manufacturing test
Not the same as design validation: just
because the design is right doesn’t mean
that every chip coming off the line will be
right.
 Must quickly check whether manufacturing
defects destroy function of chip.
 Must also speed-grade.

Modern VLSI Design 3e: Chapter 1
Copyright  1998, 2002 Prentice Hall PTR
Homework Set-1
(Due: September 19)
Problem 1.1. At the Intel site, http://www.intel.com/pressroom/kits/quickrefyr.htm, the clock speeds of intel family of
microprocessors from 1971 to 2004 are listed. Use this list to fit the clock speeds of Intel microprocessors that were
manufactured between 1971 and 2004 by a power function, i.e., determine the base b in f0  bn, where f0 is the clock speed
in MHz in 1971 and n denotes a year between 1971 and 2004. if more than one processor is listed within a given
month, use the clock speed of the fastest processor. Plot the actual clock speeds v.s. the power function you have derived.
Problem 1.2. Give the net and component lists for the following circuit by clearly marking each of the nets and components.
Vd
input-1
A
D
input-2
output
B
C
Vs
Modern VLSI Design 3e: Chapter 1
Vs
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