VLSI Test Symposium, 2011
ENHANCING ONLINE ERROR
DETECTION THROUGH AREAEFFICIENT MULTI-SITE
IMPLICATIONS
Nuno Alves, Yiwen
Shi, and R. Iris Bahar
School of Engineering,
Brown University,
Providence, RI
Jennifer Dworak
Department of Computer
Science & Engineering,
Southern Methodist
University, Dallas, TX
Kundan Nepal
Electrical Engineering
Department,
Bucknell University,
Lewisburg, PA
Outline
 Background & Previous Work
 Two-site logic implications
 Multi-site (residual) implications
 Experimental results
 Conclusions
Outline
 Background & Previous Work
 Two-site logic implications
 Multi-site (residual) implications
 Experimental results
 Conclusions
Background & Previous Work
 Online error detection aims to monitor circuit
behavior at run time and detect deviations
from its normal operating behavior while the
device is in operation.
 Redundancy in time — e.g. re-executing in a




redundant thread
Logic duplication or Triple Modular Redundancy
Codes — e.g. Parity, Berger, Bose Lin
Pre-computed test vectors and their expected
responses (stored in hardware)
High-level functional assertions
4
Outline
 Background & Previous Work
 Two-site logic implications
 Multi-site (residual) implications
 Experimental results
 Conclusions
Two-site Logic Implications
 Implications within a logic block describe expected
relationships between values at circuit sites.
n1
n2
n3
0
n4
n5
0
0
n8
0
n5 = 1 → n8 = 0
1
n6
n7
6
Two-site Logic Implications
 Violation of an expected implication indicates the
presence of an error.
n1
n2
n3
sa1
sa1
n4
n5
n6
n7
sa1
sa1
n8
n5 = 1 → n8 = 0
ERROR
7
Limitation of Simple Two-site Implications
 Each implication can only cover a limited
area of the circuit….
Reconvergent Fanout
Direct Path
P=0 → Q=0
Divergent Fanout
Q=0 → P=0
P=1 → Q=1
P
P
Q
P
Q
P
Q
P
Q
Q
P
Q
Faults along the path
may be detected
Faults along
reconverging paths may
be detected
Faults along paths to
common ancestors
8
may be detected
Checking Functions
 G = Hi OP Hj
where OP ϵ {AND, OR, XOR}
A
B
C
siteA’ AND siteB ≡ siteC
ERROR
[by I. Pomeranz and S. M. Reddy VDC1996, DFT2004]
9
Comparison of Simple Implications & Checking
Functions in error detection probability
P(Detection)
80%
60%
40%
20%
0%
10%
20%
30%
40%
50%
Area of circuit dedicated to checker logic
ISCAS85 - Simple Imp
ISCAS85 - Checking Func
ITC99 - Simple Imp
ITC99 - Checking Func
10
Simple Implication Identification
00
01
site A and B
possible values
10
11
00
01
10
observed
values in the
input space
potential simple implication:
A=1 -> B=0 (B=1 -> A=0)
11
Simple Implication Identification
00
01
site A and B
possible values
10
11
00
01
10
11
observed
values in the
input space
potential simple implication:
???
12
Outline
 Background & Previous Work
 Two-site logic implications
 Multi-site (residual) implications
 Experimental results
 Conclusions
Residual Implication Identification
Split the input space
into two pieces by a
residual pivot site P
00
01
possible values
10
11
P=0
00
01
11
site A and B
P=1
observed
values in the
input space
potential residual implication:
P=0 -> (A=1 -> B=1)
00
01
10
11
14
Implementation of the Checker Logic
using Residual Implication
 siteA = 1 -> (siteB = 0 -> siteC = 0)
A
B
C
ERROR
15
Simple Implication Selection
Start
Identify potential
implications w/ simulation
Verify implications w/ a
SAT solver
Compress implications
Select best subset for
target error detection and
overhead
End
16
Residual Implication Selection
Start
Determine optimized splitting points
Identify potential residual
implications w/ simulation
Verify implications w/ a
SAT solver
We select the splitting
sites to be those sites
whose associated faults
are propagated the
most and whose errors
are not often detected
by any simple
implications
Compress implications
Select best subset for
target error detection and
overhead
End
17
Outline
 Background & Previous Work
 Introduction to logic implications
 Multi-site (residual) implications
 Experimental results
 Conclusions
Probability of Detection for the Various Subsets of
Implications
Simple Implication
Checking Function
Simple + Residual Implication
Combined
ISCAS85
ITC99
P(Detection)
80%
60%
40%
20%
0%
10
20
30
50
40
10
20
Hardware Overhead (%)
30
40
50
19
Distribution of the Types of Relationships Making Up the
Checker Logic When All Three Types Are Combined
Simple Imp
Residual Imp
Checking Func
Implication Distribution
Optimized with
fewer redundancy
ISCAS85
ITC99
100%
80%
60%
40%
20%
0%
10
20
30
10
20
40
50
Hardware Overhead (%)
30
40
50
20
Residual Implications on
Synthesized/Optimized Circuits
 Residual implications appear to be especially useful
for circuits that have gone through some optimization
procedure.
Increase in
P(Detection)
40%
Improvement in P(Detection) for resynthesized ISCAS85
circuits using simple + residual imp vs. simple imp
30%
Un-optimized
Optimized for Area
Optimized for Delay
20%
10%
0%
10
20
30
40
50 AVG
Hardware Overhead (%)
21
Conclusions
 Introduced residual implications
 Presented an algorithm for finding and choosing a set of residual
implications to be incorporated into the checker logic for online
error detection.
 Showed that significant improvement in error detection
is possible
 Especially in the case of the ITC99 benchmarks studied.
 Proposed hybrid checker logic (residual implications +
checking functions)
 With only a 10% area overhead, we were able to detect more
than 50% of the errors in the unoptimized ISCAS85 benchmarks,
and almost 40% of the errors in the ITC99 benchmarks.