Mask Cost Reduction with Circuit
Performance Consideration for
Self-Aligned Double Patterning
H. Zhang, Y. Du, M. D.F. Wong and K. Chao
Dept. of ECE, University of Illinois at UrbanaCampaign
ASPDAC 2011
Outline
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Introduction
Overview of Self-Aligned Double Patterning (SADP)
Problem Formulation
Polygon Simplification Algorithm
Experimental Results
Conclusion
Introduction
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Double patterning lithography (DPL) is the enabling
technology for printing in sub-32nm nodes
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DPL technologies can be classified into two major
types:
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Double-exposure double-patterning (DEDP)
Single-exposure double-patterning (SEDP)
Introduction
Introduction
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The leading candidate among SEDP technologies
is self-aligned double patterning (SADP)
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In SADP, since all critical features come from a
single exposure, basically no overlay error exists
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SADP is an excellent option for the 1-D on-track
design, such as memory array
Introduction
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SADP
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Print dense lines
The portions not on the design will be trimmed away by a
cut mask
However, due to the high complexity of cut mask,
the SADP technology becomes very costly
Overview of SADP
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SADP has two major steps:
Step 1 is dense line generation
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Suppose the intended pitch of circuit patterns is p
1-D tracks, called spacer, are first manufactured on the wafer
with 2p pitch
Sidewalls are deposited along the boundary of the spacers
After the spacers are etched, the dense lines are generated by
the remaining sidewalls
Overview of SADP
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In step 2, by printing the cut patterns onto the features, an
etching process is applied
The features under the exposed region will be etched away
The cut mask will affect the final wafer only where the cut is
performed
Problem Formulation
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In SADP, what the designer can control is the circuit
wires and the corresponding cut mask patterns
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The more the cut can be merged together, the lower
the edge number of the cut polygon and therefore
the lower the cut mask cost can be obtained
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Extend some line-ends and reduce the edge
number of the intended cut
Problem Formulation
Problem Formulation
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However, the extra wire patterns on the line-end will
have a potential impact on the circuit performance
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Find an optimal way to reach the cost reduction
target and minimize the impact on circuit
performance simultaneously
Problem Formulation
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Assume the track is horizontal and reduce the edge
number of the polygon by pushing vertical edge
inwards
Recast the SADP cost reduction problem as a
polygon simplification problem:
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For a polygon set R = {r1,r2…rn} and a target edge number
k
By only pushing edges in R inwards, find a modified
polygon set R’ = {r1’,r2’…rn’} which has exact k total edges
and minimum area change
Polygon Simplification
Algorithm
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The constrained shortest path (CSP) problem is to
find, given an integer k, directed graph G, source
node S and target node T, the shortest path from S
to T that has exactly k edges in G
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CSP was initially introduced in [24] and can be
optimally solved using dynamic programming
Polygon Simplification
Algorithm
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How to transform a polygon into a directed graph
for CSP
Polygon Simplification
Algorithm
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Edge cost W(i,j) can be expressed by the area
change in the following equation:
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xi: x location of edge i
xmax(i,j): the inner-most position among all the
vertical edges between hi and hj
Lk: the length of the kth vertical edge
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Polygon Simplification
Algorithm
Polygon Simplification
Algorithm
Polygon Simplification
Algorithm
Experimental Results
Experimental Results
Experimental Results
Experimental Results
Conclusion
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When the conventional DPL (DEDP) has difficulties
handling overlay errors, SADP is considered to be a
promising method to overcome the lithography
challenges
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This paper present a mask cost reduction method
with circuit performance consideration for SADP