Studies on Channel Coupling and Floating
Body Effects and Their Impacts on Device
Performance and Reliability in SOI MOSFET
Presenter: Franklin L. Duan
Ph.D. Advisor: Prof. D.E. Ioannou
Department of Electrical & Computer Engineering
School of Information Technology and Engineering
George Mason University
Fairfax, Virginia
Outline
• MOSFET
• SOI MOSFET
• SOI Advantages
• SOI Basic Features/Problems
• Five Topics Studied
• Summary of the Results
Tree of Information Technology
SITE
IT: Information Technology
Information
Technology
Soft
Solid
Device
Circuit
Others
MOSFET
MOSFET
(Metal Oxide Silicon Field Effect Transistor)
Gate
Source
Metal
Oxide
Silicon
Drain
Scaling-down Rule of MOSFET
What to scale down
Surface dimension
Vertical dimension
Operating voltage
Results of the scaling down Delay time
Power dissipation
Power-delay product
Scale factor (K>1)
1/K
1/K
1/K
1/K
2
1/K
3
1/K
Moore’s Law of VLSI
9
10
600
256M
8
Transistors per Die
10
500
DRAM
64M
107
400
16M
4M
6
10
300
1M
200
105
256K
64K
16K
4
100
10
4K
10
0
3
0
1970
40
74
80
78
120 160
82
86
Year
200
240
280
90
94
98
Side Effects of Scaling-down
• Hot carrier degradation due to the
increased electric field and hot carrier
injections
• Lowered circuit speed due to the lower
driving current and higher capacitance
SOI (Silicon On Insulator) MOSFET
S
Si
N+
G1
D
P
N+
BOX
Si
G2
SOI Advantages
• Radiation hardness
• Low power/high speed
– Reduction in parasitic capacitance
– Improved subthreshold slope
•
•
•
•
Improved short channel effect
CMOS latch-up free
Increased ULSI packing density
Simplified fabrication
SOI Three Basic Features
in Device Physics
• Dual Gate control
• Channel Coupling
• Floating Body Effect
Three Basic Features of SOI
G1
2
3
1
G2
Five Topics Studied in the Thesis
• Dual gate control:
– Opposite channel based-hot-carrier injection (OCBI)
technique, unique tool for hot carrier study in SOI
• Channel coupling:
– trade-off between hot carrier degradation and FBE
• Floating Body Effect (FBE):
– abnormally higher impact ionization rate at the edges
• Two modes of operations in FD SOI:
– a new mixed mode structure
• Bulk technology integration:
– performance and reliability trade-off
Methodology/ Characterization
• Experimentally
• hot carrier stressing
• substrate current (as
a monitor of
degradation)
measurement
• single transistor latch
up voltage
characterization
• By simulation
• map:
• electric potential
• electric field,
• current path,
• calculate :
• hot carrier generation
• hot carrier injection
current
1. OCBI Technique
(Opposite Channel Based Injection)
VG1= 1 V
VS= 0 V
N+
P
- + Ih
VG2= -30 V
VD= 7 V
N+
Pure Hole Injection Into the BOX
1E-11
(A/m)
1E-12
10 -12
1E-13
Ih2: hole injection current
1E-14
10 -14
Ie2: electron injection current
Ie2=0
1E-15
Ih2
VD=7V, VG2= -30V.
1E-16
10 -16
0
1
2
3
V G1 (V)
4
5
Shift of ID-VG2 Characteristics
After Hole Injection
7.E-05
6.E-05
ID (A)
5.E-05
4.E-05
10 hrs stressing
3.E-05
2.E-05
Original
1.E-05
0.E+00
20
25
30
VG2
35
40
Back Threshold Voltage Shift ( - DVT2 )
as a Function of Stress Time
12
10
Standard SIMOX
DVT2(V)
8
6
4
With a supplemental
O2 implantation
2
0
10
100
1000
Time(S)
10000
Eg (eV)
2. Channel Coupling
{
1
VG2=
0
Ec
-30 V
0V
+5 V
____
Series4
Series6
Ev
-1
-2
0
0.05
ts(m)
0.1
Substrate Current Dependence on the Back
Gate Bias in FD SOI MOSFET
1E-02
-30V
1E-04
ID
0V
1E-06
+5V
ISUB
Seri
es4
Seri
es5
Seri
es6
1E-08
1E-10
1E-12
-1
0
1
VG1 (V)
2
3
Substrate Current Dependence on the Back
Gate Bias in PD SOI MOSFET
0V
10V
20V
30V
40V
ISUB (A)
8E-06
6E-06
50V
60V
4E-06
2E-06
0E+00
0
2
4
VG1 (V)
6
Channel Coupling Effect on
Hot Carrier Degradation
Channel Coupling Effect on
Single Transistor Latch-up
VDLU (V)
8.6
8.2
7.8
7.4
7.0
-70 -50 -30 -10 10
VG2 (V)
Impact Generation Rate as a Function
of Silicon Film Thickness
Ts=0.25um
0.4um
0.3um
0.8um (bulk)
3. Study of Floating Body Effect (FBE)
its Edge and Width Effect
VC
n+
p
W
SiO2
n+
VE
Contour Plot of Impact Generation Rate
for Different Channel Width
3
log G (1/[cm .s])
Abnormally Higher Impact Generation Rate
at the Edges
25
W=
 m
 m
 m
20
15
10
5
0
0
0.5
X/W
1
Impact Generation Rate
at the Edges When the Body is Grounded
Log (G (1/cm3.s))
1E+20
1E+16
1E+12
1E+08
um
W =10 um
W =2
1E+04
1E+00
0
0.5
X/W
1
Single Transistor Latch-up Voltage
as a Function of Device Width
8
VDLU (V)
Body Floating
Body Grounded
7
6
0
10
W (m)
20
Hot Carrier Degradation of Three Devices
with Different Width
1.00
10
W=10m
5W=5.0m
DID/ID
3.5
W=3.5m
Power
(3.5)
Power
(10)
Power
(5)
0.10
0.01
10
100
1000
Time (s)
10000 100000
Kink Effect Dependence on
Channel Width
300
0.0003
W=5.6m
W=5.6
ID/W (A/m)
W=3.6
W=3.6m
200
0.0002
VG=4 V
VG=3 V
100
0.0001
VG=2 V
VG=1 V
0
0.0000
0
2
4
VD (V)
6
4. A New FD SOI MOSFET Structure
Two existing FD SOI MOSFETs
P+
N+
N+
P
N+
INV: inversion mode
N+
N-
N+
ACC: accumulation mode
Potential Profiles of the Inversion and
Accumulation Mode FD SOI MOSFET
S
Pot (V)
Cha
S
nnel
D
0.4
Pot (V)
Chan
nel
0.4
0.2
D
0.2
0
0
-0.2
Fro
-0.4
-0.2
nt O
X
ck
OX
Inversion Mode
Si
-0.4
Bac
k
OX
Accumulation Mode
nt O
X
Si
Ba
Fro
Virtually Fabricated New SOI Device
(by SUPREM)
(m)
-0.2
spacer
p-poly
-0.1
0.0
n-type
p-type
n+
n+
0.1
BOX
0
0.4
0.8
1.2
(m)
Comparison of Transconductance and
Latch-up Voltage of the Three Devices
Comparison of the Hot Carrier
Injection of the Three Devices
1.8E-14
9
9.0E-16
acc
inv
mix
12
Ih1 (x10 A/m)
1.2E-14
-16
-15
Ie1 (x10 A/m)
18
Ie1
6.0E-15
6
Ih1
3.0E-16
3
0
0
15
1.5E-14
1
2
VG1 (V)
3
0
4
1
2
3
4
VG1 (V)
acc
inv
mix
acc
inv
mix
4
Ih3 (x10 A/m)
4.0E-18
10
3.0E-18
3
-18
1.0E-14
-15
Ie3 (x10 A/m)
6
6.0E-16
acc
inv
mix
01E+00
51E+00
01E+00
51E+00
01E+00
0.0E+00
0.0E+0
0
1.
1.
2.
2.
3.
Ie2
5.0E-15
5
Ih2
2.0E-18
2
1.0E-18
1
0.0E+00
0.0E+0
0
0
1
2
VG1 (V)
3
4
0
0
1
2
3
VG1 (V)
4
5
A
5. LDD Design Tradeoff in SOI MOSFET
LDD Implant
(A)
S/D Implnat
N+
N N-
(A)
(B)
(B)
Spacer
Poly -Si(p+)
Gate-OX
Si
(C)
(C)
BOX
Experimental Results:
Tradeoff Between Performance and Reliability)
1E+09
A
C
B
3.5
A
Lifetime (s)
Latch-up Voltage (V)
4
B
1E+08
1E+07
1E+06
C
1E+05
3
LDD Design
LDD Design
Contours of Impact Generation Rate
of the Three LDD Designs
Comparison of Impact Generation
Rate and Latch-up Voltage
Impact Rate Integral (1/cm2 s)
Structure
Latch-up
Voltage (V)
Top
Middle
Bottom
Average
A
8.5x1020
1.7x1022
2.9x1022
1.6x1022
3.40
B
8.0x1020
8.2x1021
2.3x1022
1.1x1022
3.55
C
7.9x1020
1.5x1021
1.8x1021
1.4x1021
3.80
Summary of the Results
• Opposite channel based injection can happen by the aid of dual
gate control and this phenomenon can be used as a tool to study the
hot carrier degradation
• Channel coupling imposes a trade-off between the hot carrier
reliability and single transistor latch-up in SOI MOSFET
• The rate of carrier generation rate is higher at the edge of SOI
MOSFET and more so for wider devices. Wider devices have lower
breakdown voltages.
• A new structure was proposed which holds the weaknesses of the
current FD SOI MOSFETs and is more resistant to hot carrier
injections
• Optimized bulk LDD technology faces a tradeoff between hot carrier
reliability and single transistor latch-up in SOI MOSFET