Grace
advertisement
MSP430 | Ultra-Low Power is in our DNA
Getting Started with the MSP430 LaunchPad
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
MSP430 Released Devices
MSP430 MCUs
An Introduction
Ultra-Low Power
Integration
World’s Lowest Power MCU
Intelligent Analog & Digital Peripherals
• Ultra-Low Power Active Mode
• Peripherals operate in low power modes
• 7 Low Power Modes
• Minimize physical footprint and Bill of Materials
• Instant Wakeup
• Featuring FRAM, USB, RF, Capacitive Touch I/O,
Metrology Engines, LCD, ADC, DAC & MORE
• All MSP430 devices are Ultra-Low Power
Extensive Portfolio, Low Cost Options
Easy to Get Started
Find the right MCU for you
Low cost and simple point of entry
• 400+ devices
• Complete kits starting @ $4.30
• Up 256kB Flash, 18kB RAM, 25+ package options
• GUI-based coding & debugging tools available
• Devices starting at $0.25 with Value Line
• MSP430Ware Software and Resource Package
• Various levels of performance & integration
-Incl. code examples, datasheets, user guides & more!
MSP430 | Ultra-Low Power is in our DNA
MSP430-Enabled Applications
Thousands of applications are
enabled by MSP430 MCUs
Differentiation is possible with MSP430 MCU’s
Ultra-Low Power performance, high analog &
digital peripheral integration, and easy-to-use
tool chain.
MSP430 | Ultra-Low Power is in our DNA
Value Line: 16-bit performance, 8-bit price
UART
16KB
ADC
MSP430G25X3
SC
ADC UART
MSP430G24X3
SC
ADC UART
MSP430G23X3
SC
ADC UART
MSP430G22X3
SC
ADC UART
MSP430G21X3
SC
ADC UART
8KB
MSP430G24X2
SC
ADC
4KB
Flash Size
SC
2KB
MSP430G23X2
SC
ADC
MSP430G22X2
SC
ADC
MSP430G22X1*
ADC
MSP430G21X2
1KB
MSP430G21X1*
.5 KB
SC
SC
SC
ADC
ADC
MSP430G2001*
14-pin
TSSOP/PDIP
10 GPIO
* 8-pin SOIC in development
16-pin
QFN
10 GPIO
20-pin
TSSOP/PDIP
16 GPIO
28-pin
TSSOP
24 GPIO
32-pin
QFN
24 GPIO
Value Line Peripherals
Value Line Peripherals
General Purpose I/O
16-bit Timer_A3
3 capture/compare registers
Extensive interrupt capabilities
WDT+ Watchdog Timer
Independently programmable
Any combination of input, output, and interrupt (edge
selectable) is possible
Read/write access to port-control registers is supported by
all instructions
Each I/O has an individually programmable pull-up/pull-down
resistor
Some parts/pins are touch-sense enabled (PinOsc)
Also available as an interval timer
Brownout Reset
Provides correct reset signal during power up and down
Power consumption included in baseline current draw
Value Line Peripherals
Serial Communication
Comparator_A+
USI with I2C and SPI support
USCI with I2C, SPI and UART support
Inverting and non-inverting inputs
Selectable RC output filter
Output to Timer_A2 capture input
Interrupt capability
8 Channel/10-bit 200 ksps SAR ADC
8 external channels (device dependent)
Voltage and Internal temperature sensors
Programmable reference
Direct transfer controller send results to conversion memory
without CPU intervention
Interrupt capable
Some parts have a slope converter
LaunchPad Development Board
USB Emulator
Connection
Embedded Emulation
6-pin eZ430 Connector
Crystal Pads
Chip Pinouts
Part and Socket
P1.3 Button
Power Connector
LEDs and Jumpers
P1.0 & P1.6
Reset Button
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
What is Code Composer Studio?
Integrated development environment for TI embedded processors
Includes debugger, compiler, editor, simulator, OS…
The IDE is built on the Eclipse open source software framework
Extended by TI to support device capabilities
CCSv5 is based on “off the shelf” Eclipse (version 3.7 in CCS 5.1)
Future CCS versions will use unmodified versions of Eclipse
Drop in Eclipse plug-ins from other vendors or take TI tools and drop them
into an existing Eclipse environment
Users can take advantage of all the latest improvements in Eclipse
Integrate additional tools
TI contributes changes directly to the open source community
OS application development tools (Linux, Android…)
Code analysis, source control…
Linux support soon
Low cost! $445 or $495
Common Tasks
Creating New Projects
Build options
Very simple to create a new project for a device using a template
Many users have difficulty using the build options dialog and find it
overwhelming
Updates to options are delivered via compiler releases and not
dependent on CCS updates
Sharing projects
Easy for users to share projects, including working with version
control (portable projects)
Setting up linked resources has been simplified
Workspaces and Projects
Workspace
Project 1
Link
Project 2
Project 3
Settings and preferences
Project
Project
Project
Source
files
Link
Source files
Source
Header
filesfiles
Link
Header Files
Header
Library
filesFiles
Library files
Library
filessettings
Build
and tool
Build and tool settings Link
Build and tool settings
Source files
Code and Data
Header files
Declarations/Defines
Library files
Code and Data
A workspace contains
your settings and
preferences, as well as
links to your projects.
Deleting projects from
the workspace deletes
the links, not the files
A project contains
your build and tool
settings, as well as
links to your input
files.
Deleting files from the
workspace deletes the
links, not the files
Project Wizard
Single page wizard for majority of
users
Debugger setup included
Next button will show up if a template
requires additional settings
If a specific device is selected, then
user can also choose their connection,
ccxml file will be created
Simple by default
Compiler version, endianness… are
under advanced settings
MSP430 | Ultra-Low Power is in our DNA
Various IDE options
Free Integrated Development Environments (IDE) available
Code Composer Studio
•
Eclipse-based IDE (Compiler, debugger, linker, etc) for all TI embedded processors
•
Unrestricted version available for $495
•
Free versions are available!
• Free 16kB code-limited version available for download
• Free, full-featured, 120-day trial version available
IAR Embedded Workbench
•
Strong third-party IDE offering with project management tools and editor. Includes
config files for all MSP430 devices.
•
Free versions are available!
• Free 4/8/16kB code-limited Kickstart version available for download
• Free, full-featured, 30-day trial version available
MSPGCC
•
Free, Open source, GCC tool chain for MSP430
•
includes the GNU C compiler (GCC), the assembler and linker (binutils), the debugger (GDB)
•
Tools can be used on Windows, Linux, BSD and most other flavors of Unix.
•
Learn more @ http://mspgcc.sourceforge.net/
Other MSP430 IDE options are available! Learn more @ www.ti.com/msp430tools
Lab1: Code Composer Studio
• Lab1:
• Create a new workspace
• Create Lab1 Project
• Add in temperature sense demo
• Compile it and run
Step 1: Create CCS workspace
• Put the Lab files onto your desktop
• Launch CCS v5 Core Edition
• Select a “Workspace” location
18
Step 2: Create a CCS Project
•
•
•
•
•
•
File > New > CCS Project
Project Name: Lab1
Device>Family: MSP430
Variant: MSP430G2452
Project templates and examples
: Empty Project
19
Step 3: Add a File to the CCS Project
•
•
•
Project > Add Files
Navigate to Lab source folder
And select :
Temperature_Sense_Demo.c
20
CCS Window – C/C++ Perspective Overview
1-click project Debug
Independent Debug and
C/C++ Project Perspectives
Project Outline
• Shortcut to project parts
Project View
• List of all
Projects
Problems View
• Information,
Warnings, Errors
Console
• Build Information
Code Window
• Real-time breakpoints, Syntax highlighting
21
CCS Window – Debug Perspective Overview
1-click project Debug
Independent Debug
and C/C++ Project
Perspectives
Highly configurable
window layout
• User preferences
• Plugin support
Target control
• Start
• Stop
• Halt
• Stepping
• Stack Trace
Real-time, in-system
MSP430 information
• Register access
• Flash, RAM, Info
segment access
• Disassembly view
Program Size Info
Code Window
• Real-time breakpoints, Syntax highlighting
22
Step 4: Build & Debug a CCS Project
Click the “BUG” to build the
code & launch the debugger
23
Step 5: Run, Terminate a CCS Project
“RUN”
“TERMINATE”
Perspectives
24
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
MSP430G2xx Structure
Ultra-low Power
0.1uA power down
0.8uA standby mode
220uA / 1MIPS
<1us clock start-up
<50nA port leakage
Zero-power brown-out reset
(BOR)
Clock
FLASH
RISC
CPU
16-bit
MAB 16
MDB 16
Ultra-Flexible
6
0.5k-16kB In-System
Programmable (ISP) Flash
16-bit Timer
SPI, I2C
10bit ADC
Embedded emulation
RAM
...
JTAG/Debug
...
ACLK
SMCLK
Digital
Peripheral
Analog
Peripheral
16-bit RISC CPU
7
Deep single-cycle register
file
4 special purpose
12 general purpose
No accumulator
bottleneck
RISC architecture
27 core instructions
24 emulated instructions
7 address modes
Atomic memory-to-memory
addressing
Bit, byte and word
processing
Constant generator
15
R0/PC
R1/SP
R2/SR
R3/CG
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
0
16
16
16-bit ALU
Memory Map
G2452 shown
Flash programmable via JTAG or
In-System (ISP)
ISP down to 2.2V. Single-byte or
Word
Main memory: 512 byte segments
(0-n). Erasable individually or all
Information memory: 64 byte
segments (A-D)
Section A contains device-specific
calibration data and is lockable
Programmable Flash Memory
Timing Generator
0FFFFh
0FFE0h
FFDFh
0E00h
Interrupt Vector Table
010FFh
01000h
Information
Memory
02FFh
0200h
01FFh
0100h
0FFh
010h
0Fh
0h
Flash/ROM
RAM
16-bit
Peripherals
8-bit
Peripherals
8-bit Special
Function
Registers
Clock System
Very Low Power/Low Frequency
Oscillator (VLO)
4 – 20kHz (typical 12kHz)
500nA standby
0.5%/°C and 4%/Volt drift
Crystal oscillator (LFXT1)
Programmable capacitors
Failsafe OSC_Fault
Minimum pulse filter
Digitally Controlled Oscillator
(DCO)
0-to-16MHz
+ 3% tolerance
Factory calibration in Flash
VLO
Min. Puls
Filter
ACLK
Peripherals
OSC_Fault
MCLK
CPU
16MHz
DCO
SMCLK
Peripherals
On PUC, MCLK and SMCLK are
sourced from DCOCLK at ~1.1 MHz.
ACLK is sourced from LFXT1CLK in
LF mode with an internal load
capacitance of 6pF.
G2xxx - No Crystal Required DCO
// Setting the DCO to 1MHz
if (CALBC1_1MHZ ==0xFF || CALDCO_1MHZ == 0xFF)
while(1);
// Erased calibration data? Trap!
BCSCTL1 = CALBC1_1MHZ;
// Set range
DCOCTL
// Set DCO step + modulation
= CALDCO_1MHZ;
G2xx1 devices have 1MHz DCO constants only. Higher frequencies must be
manually calibrated
G2xx2 & G2xx3 have all 4 constants + calibration values for the ADC & temperature
sensor
Run Time Calibration of the VLO
Calibrated 1 MHz DCO
TAR
fVLO = 8MHz/Counts
CCRx
ACLK/8 from VLO
Calibrate the VLO during runtime
Clock Timer_A runs on calibrated 1MHz DCO
Capture with rising edge of ACLK/8 from VLO
fVLO = 8MHz/Counts
Code library on the web (SLAA340)
System MCLK & Vcc
Match needed clock speed with required Vcc to achieve the lowest power
External LDO regulator required
Unreliable execution results if Vcc < the minimum required for the selected frequency
All G2xxx device operate up to 16MHz
Lab2: Basic Clock Configure
• Lab2
• Import Lab2 project to Workspace
• Setup DCO = 1MHz
• Use DCO/8 as MCLK, LED Blink
• Use VLO/8 as MCLK, LED Blink
Lab 2:
// Configure Basic Clock
BCSCTL1 = __________; // Set range
DCOCTL = ___________;// Set DCO step + modulation
BCSCTL3 |= LFXT1S_2;// Set LFXT1
// Configure MCLK
BCSCTL2 |= ________ + DIVM_3; // Set MCLK
• Reference User’s Guide, Datasheet & Schematic
Lab 2: BCSCTL2 in 2xx User Guide
Lab 2: BCSCTL2 in MSP430G2453 head file
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
Interrupts and the Stack
Entering Interrupts
Any currently executing instruction is completed
The PC, which points to the next instruction, is pushed onto the stack
The SR is pushed onto the stack
The interrupt with the highest priority is selected
The interrupt request flag resets automatically on single-source flags;
Multiple source flags remain set for servicing by software
The SR is cleared; This terminates any low-power mode; Because the
GIE bit is cleared, further interrupts are disabled
The content of the interrupt vector is loaded into the PC; the program
continues with the interrupt service routine at that address
Vector Table
Interrupt Source Interrupt
Flag
System
Interrupt
Word Address
Priority
Power-up
External Reset
Watchdog Timer+
Flash key violation
PC out-of-range
PORIFG
RSTIFG
WDTIFG
KEYV
Reset
0FFFEh
31
(highest)
NMI
Oscillator Fault
Flash memory access
violation
NMIIFG
OFIFG
ACCVIFG
Non-maskable
Non-maskable
Non-maskable
0FFFCh
30
0FFFAh
29
0FFF8h
28
Comparator_A+
CAIFG
maskable
0FFF6h
27
Watchdog Timer+
WDTIFG
maskable
0FFF4h
26
Timer_A3
TACCR0
CCIFG
maskable
0FFF2h
25
Timer_A3
TACCR1
CCIFG TAIFG
maskable
0FFF0h
24
0FFEEh
23
0FFECh
22
ADC10
ADC10IFG
maskable
0FFEAh
21
USI
USIIFG
USISTTIFG
maskable
0FFE8h
20
I/O Port P2 (2)
P2IFG.6
P2IFG.7
maskable
0FFE6h
19
I/O Port P1 (8)
P1IFG.0 to
P1IFG.7
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
0FFDEh to 0FFCDh
15 - 0
Unused
ISR Coding
#pragma vector=WDT_VECTOR
__interrupt void WDT_ISR(void)
{
IE1 &= ~WDTIE;
// disable interrupt
IFG1 &= ~WDTIFG;
// clear interrupt flag
WDTCTL = WDTPW + WDTHOLD;
// put WDT back in hold state
BUTTON_IE |= BUTTON;
// Debouncing complete
}
#pragma vector - the following function is an ISR for the listed vector
_interrupt void - identifies ISR name
No special return required
Controlling GPIO Ports
GPIO Register
GPIO Code Example
Input Register PxIN
P1DIR |= BIT4;
P1SEL |= BIT4;
Output Register PxOUT
Direction Register PxDIR
Function Select PxREN
Function Select PxSEL
Function Select PxSEL2
Interrupt Edge PxIES
Interrupt Enable PxIE
Interrupt Flags PxIFG
26
For GPIO Int
P1DIR |= BIT0;
P1OUT |= BIT0;
Pin Muxing
Each
pin has multiple functions
Register bits select pin function
See device specific datasheet
Lab3: GPIO
Lab3
• Setup P1.3 to Button
• Setup P1.0 to LED control
• LED toggle with Button
Lab 3:
P1DIR
P1IES
_____
_____
|=
|=
&=
|=
BIT0; // Set P1.0 to output direction
BIT3; // P1.3 Hi/lo edge
~BIT3; // P1.3 IFG cleared
BIT3; // P1.3 interrupt
// Port1 interrupt service routine
#pragma vector = __________
__interrupt void Port_1(void)
// Port1 interrupt service routine
P1OUT ^= BIT0;
// P1.0 = toggle
______ &= ~BIT3; // P1.3 IFG cleared
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
Timer_A
Asynchronous
16-Bit timer/counter
Continuous,
up-down,
up count modes
Multiple
capture/compare
registers
PWM outputs
Interrupt vector
register for fast
decoding
Can trigger DMA
transfer
On all MSP430s
16-bit Timer
TAR
TACLK
ACLK
SMCLK
INCLK
Set
TAIFG
CCR0
CCR1
CCR2
Capture
Mode
CCI2A
CCI2B
GND
VCC
TACCR2
Compararator 2
CCI
SCCI
Y
A
EN
Set
CCIFG2
Output
Unit2
70
Count
Mode
Timer_A Counting Modes
Stop/Halt
Continuous
Timer is halted
Timer continuously counts up
0FFFFh
0h
0FFFFh
Up
Up/Down
Timer counts between 0 and CCR0
Timer counts between 0 and CCR0 and 0
0FFFFh
CCR0
CCR0
0h
0h
CCR – Count Compare Register
71
UP/DOWN Mode
Timer_A Interrupts
The Timer_A Capture/Comparison Register 0 Interrupt Flag
(TACCR0) generates a single interrupt vector:
TACCR0 CCIFG
TIMERA0_VECTOR
No handler required
TACCR1, 2 and TA interrupt flags are prioritized and combined
using the Timer_A Interrupt Vector Register (TAIV) into another
interrupt vector
TACCR1 CCIFG
TACCR2 CCIFG
TAIV
TIMERA1_VECTOR
TAIFG
Your code must contain a handler to determine which Timer_A1
interrupt triggered
72
TAIV Handler Example
TAIV
0 0 0 0 0 0 0 0 0 0 0 x x x x 0
15
0
#pragma vector = TIMERA1_VECTOR
__interrupt void TIMERA1_ISR(void)
{
switch(__even_in_range(TAIV,10))
{
case 2 :
// TACCR1 CCIFG
P1OUT ^= 0x04; break;
case 4 :
// TACCR2 CCIFG
P1OUT ^= 0x02; break;
case 10 :
// TAIFG
P1OUT ^= 0x01; break;
}
}
IAR C code
73
Source
TAIV Contents
No interrupt pending
0
TACCR1 CCIFG
02h
TACCR2 CCIFG
04h
Reserved
06h
Reserved
08h
TAIFG
0Ah
Reserved
0Ch
Reserved
0Eh
0xF814
0xF818
0xF81A
0xF81C
0xF81E
0xF820
0xF822
0xF824
0xF828
0xF82A
0xF82E
0xF830
0xF834
add.w
reti
jmp
jmp
reti
reti
jmp
xor.b
reti
xor.b
reti
xor.b
reti
&TAIV,PC
0xF824
0xF82A
0xF830
#0x4,&P1OUT
#0x2,&P1OUT
#0x1,&P1OUT
Assembly code
Timer_A PWM Example
CCR2
CCR2
CCR2
MSP430F11x1
TEST
Vcc
P2.5
Vss
XOUT
XIN
RST
P2.0
P2.1
P2.2
74
TA2/P1.7
P1.6
P1.5
P1.4
P1.3
TA1/P1.2
P1.1
P1.0
P2.4
P2.3
CCR1
CCR1
CCR0
CCR1
CCR0
CCR0
Completely automatic
Independent frequencies with different duty cycles can be
generated for each CCR
Code examples on the MSP430 website
Direct Hardware Control With Timer_A
Example: ADC12
65536
TAR
TACCR1 = 557
0
2s
TAIFG:
Reference & ADC on
TACCR1:
Ref delay / ADC trigger
ADC12IFG:
Process ADC result
Ref/ADC Off
17ms
CPU Active Mode
UART ...
75
WDT+ Module: Overview
WDTCTL
• Found on all MSP430 devices
• Two modes
Watchdog
Interval timer
16-Bit
Counter
• Access password protected
• Separate interrupt vectors for POR
and interval timer
Password
Compare
EQU
EQU
R/W
• Sourced by ACLK or SMCLK
• Controls RST/NMI pin mode
• WDT+ adds failsafe/protected clock
MDB
Control
Register
Watchdog Timer Failsafe Operation
If ACLK / SMCLK fail, clock
source = MCLK
(WDT+ fail safe feature)
If MCLK is sourced from a
crystal, and the crystal
fails, MCLK = DCO
(XTAL fail safe feature)
16-bit
Counter
CLK
MCLK
Fail-Safe
Logic
SMCLK
1
ACLK
1
WDTSSEL
A
EN
WDTHOLD
WDT clock source …
WDT: Common Design Issues
• Program keeps resetting itself!
• Program acting wacky – how did execution get to
that place?
Try setting interrupt near beginning of main() to see if code is re-starting
• CPU seems to freeze before even getting to first
instruction
Is this a C program with a lot of initialized memory?
Generally can occur only with very large-memory versions of the device
Solution: Use __low_level_init() function, stop watchdog there
void main(void)
{
WDTCTL = WDTPW+WDTHOLD;
.
.
}
// Stop the dog
WDT: Interval Timer Function
• No PUC issued when interval
is reached
• If WDTIE and GIE set when
interval is reached, a WDT
interval interrupt generated
instead of reset interrupt
• Selectable intervals
Lab4: Timer and Interrupts
Lab4
• Use TimerA to implement Lab2
• Configure Timer_A3 Count Cycle:
5100
•Occurs a interrupt when TAR =100
Lab 4:
// Configure TimerA
TACTL = __________________; // Source: ACLK, UP mode
CCR0 = 5100;
//Timer count 5100
CCR1 = 100;
//Timer count 100
CCTL0 = CCIE;
//CCR0 interrupt enabled
CCTL1 = CCIE;
//CCR1 interrupt enabled
// Timer A0 interrupt service routine
#pragma vector = __________
__interrupt void Timer_A0(void)
// Timer A1 interrupt service routine
#pragma vector = __________
__interrupt void Timer_A1(void)
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
Ultra Low Power Feature
Ultra-Low Power Is In Our DNA
MSP430
designed for ULP
from ground up
Peripherals
optimized to
reduce power and
minimize CPU usage
Intelligent,
low power
peripherals can operate
independently of CPU and
let the system stay in a
lower power mode longer
www.ti.com/ulp
Multiple operating modes
100
nA power down (RAM retained)
0.3 µA standby
110 µA / MIPS from RAM
220 µA / MIPS from Flash
Instant-on stable high-speed clock
1.8 - 3.6V single-supply operation
Zero-power, always-on BOR
<50nA pin leakage
CPU that minimizes cycles per task
Low-power intelligent peripherals
ADC that automatically transfers data
Timers that consume negligible
power
100 nA analog comparators
Performance over required operating
conditions
Ultra-Low Power Activity Profile
Active
Average
Low
Power
Mode
Minimize
active time
Maximize time in Low Power Modes
Interrupt driven performance on-demand with <1μs wakeup time
Always-On, Zero-Power Brownout Reset (BOR)
MSP430 Low Power Modes
CPU Off
DCO on
ACLK on
Active
DCO on
ACLK on
45µA
220µA
LPM0
<1µs
Off
All
Clocks Off
100nA
<1µs
LPM4
• RAM/SFR retained
Stand-by
DCO off
ACLK on
0.3µA
Specific values vary by device
LPM3
• RTC function
• LCD driver
• RAM/SFR retained
Low Power Mode Configuration
Reserved
V
SCG1 SCG0 OSC
OFF
CPU
OFF
GIE
N
Z
C
R2/SR
Active Mode
0
0
0
~ 250uA
LPM0
0
0
0
1
~
LPM3
1
1
0
1
~ 0.8uA
LPM4
bis.w
0
#CPUOFF,SR
1
1
1
1
35uA
~ 0.1uA
; LPM0
LPM in Assembly
34
Low Power Modes In Stack
Item1
Item2
Item1
Item2
PC
SR=0018
SP
Mainloop
bis.w
xor.b
jmp
#CPUOFF+GIE,SR
#01h,&P1OUT
Mainloop
WDT_ISR
bic.w
reti
#CPUOFF,0(SP)
ORG
DW
ORG
DW
0FFFEh
RESET
0FFF4h
WDT_ISR
SP
Item1
Item2
PC
SR=0008
Item1
Item2
PC
ORG
0F000h
RESET
mov.w
#300h,SP
mov.w
#WDT_MDLY_32,&WDTCTL
bis.b
#WDTIE,&IE1
bis.b
#01h,&P1DIR
SP
SR
LPM in C
35
ULP is Easy!
Using our Low Power Modes are easy
void main(void)
{
WDT_init(); // initialize Watchdog Timer
while(1)
{
__bis_SR_register(LPM3_bits + GIE);
activeMode();
}
}
#pragma vector=WDT_VECTOR
__interrupt void watchdog_timer (void)
{
__bic_SR_register_on_exit(LPM3_bits);
}
// Enter LPM3, enable interrupts
// in active mode. Do stuff!
// Clear LPM3 bits from 0(SR), Leave LPM3, enter active mode
10-yr Embedded Real-Time Clock
= LPM3 + RTC_Function
32768
100µs
1000000µs
0.80µA + 250µA *
0.80µA + 0.030µA = 0.83µA
1mA
100µA
MSP430F20x1
Interface
// Partial RTC_Function
incrementseconds();
incrementminutes();
incrementhours();
//
10µA
1µA
Time
Low-Power Operation
Power-efficient MSP430 apps:
Minimize instantaneous current draw
Maximize time spent in low power modes
The MSP430 is inherently low-power, but your
design has a big impact on power efficiency
Proper low-power design techniques make the
difference
“Instant on” clock
Move Software Functions to Peripherals
MCU
P1.2
// Endless Loop
for (;;)
{
P1OUT |= 0x04; // Set
delay1();
P1OUT &= ~0x04; // Reset
delay2();
}
100% CPU Load
47
// Setup output unit
CCTL1 = OUTMOD0_1;
_BIS_SR(CPUOFF);
Zero CPU Load
Power Manage Internal Peripherals
MSP430F20x1
Px.x
CAON
P1.0
Comparator_A
+
Ref
-
P1OUT |= 0x02;
CACTL1 = CARSEL + CAREF_2 + CAON;
if (CAOUT & CACTL2)
P1OUT |= 0x01;
else
P1OUT &= ~0x01;
P1OUT &= ~0x02;
CACTL1 = 0;
48
// Power divider
// Comp_A on
// Fault
// de-power divider
// Disable Comp_A
Power Manage External Devices
MCU
TLV2760
Sensor
SD
Px.x
"1uA OPA"
Sensor
ADC
ADC
0.01uA = Shutdown
20uA = Active
--------------------------0.06uA = Average
1uA = Quiescent
1uA = Active
----------------------1uA = Average
Op-amp with shutdown can be 20x lower total power
49
MCU
Unused Pin Termination
Digital input pins subject to shoot-through current
Input voltages between VIL and VIH cause shoot-through if
input is allowed to “float” (left unconnected)
Port I/Os should
Driven as outputs
Be driven to Vcc or ground by an external device
Have a pull-up/down resistor
Lab5: Low Power Mode
Lab5
• Optimize Lab4 to implement LPM
Lab 5:
Enter Low Power Modes with just 1 line of code!
_BIS_SR(_________);//Enter Low Power Mode;
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
Fast Flexible ADC10
10-bit 8 channel SAR ADC
200 ksps+
Selectable conversion clock
Autoscan
6 external channels
Vcc and internal temperature
Single
Sequence
Repeat-single
Repeat-sequence
Internal or External reference
Timer-A triggers
Interrupt capable
Data Transfer Controller (DTC)
Auto power-down
1.5V or 2.5V
Auto
AVSS
S/H
AVCC
VRVR+
10-bit SAR
ADC10SC
TA1
TA0
TA2
Batt Temp
Direct
Data
Transfer
Transfer
Controller
Controller
RAM, Flash,
Peripherals
Sample Timing
Reference must settle for <30uS
Selectable hold time
13 clock conversion process
Selectable clock source
- ADC10OSC (~5MHz)
- ACLK
- MCLK
- SMCLK
AUTO
Autoscan + DTC Performance Boost
ADC
DTC
// Software
Res[pRes++] = ADC10MEM;
ADC10CTL0 &= ~ENC;
if (pRes < NR_CONV)
{
CurrINCH++;
if (CurrINCH == 3)
CurrINCH = 0;
ADC10CTL1 &= ~INCH_3;
ADC10CTL1 |= CurrINCH;
ADC10CTL0 |= ENC+ADC10SC;
}
70 Cycles / Sample
Data2
Data1
Data0
Data2
// Autoscan + DTC
_BIS_SR(CPUOFF);
Fully Automatic
Comparator_A
0V
VCC
CAEX
CA0
References usable
internally and
externally
Low-pass filter
selectable by software
Input terminal
multiplexer
One interrupt vector
with enable
CA1
+
+
CCI1B
--
CAOUT
0V
set CAIFG
Flag
VCC
CAON
CAREF
0.5xVCC
0.25xVCC
G
D
S
Comparator-Based Slope ADC
10-bit+ accuracy
Resistive sensors
Very low cost
App note SLAA038
Px.x
REF
Px.x
+
-
Timer_A
Capture
VSS
t_x = R_x x C x ln VCAREF
Vcc
...
t_NTC
R_NTC = 10k x
t_10k
0.25xVCC
~0.55V
Example: Thermistor
V1
VCC
RREF = 10K, RM = NTC
VCAREF = VCC*e(-t/RC)
Relationship simplifies to single
multiply & divide operations
CAREF
VSS
t_5tu
R_NTC
=
10k
t_NTC
V
C x ln CAREF
Vcc
t_10k
VCAREF
C x ln
Vcc
t_10k
t_5tu
t_NTC
t_NTC
R_NTC = 10k x
t_10k
t
Timer Triggers – Low-Power
Timer
Memory
ADC
// Interrupt
; MSP430 ISR to start conversion
BIS #ADC12SC,&ADC12CTL0 ; Start conversion
RETI
; Return
;
CPU cycles
6
5
5
16
Timer triggered interrupts – no software wait loops
64
Selecting an MSP430 ADC
channels
ADC10
ADC12
SD16
SD16_A
8
12
3 ind
4 mux'd
f SAM PLE (ksps)
SINAD
res
(typ)
min
max
34
34
200+
200+
~4
~0.03
Voltage
~5
10
12
16
16
57
68
85
85
A IN
Vss to Vref
Vss to Vref
+/-600mV
+/-600mV
reference
Ref IN Ref OUT Ref I_OUT
1.4-3.6 1.5/2.5V
1.4-3.6 1.5/2.5V
1.0-1.5 1.2V
1.0-1.5 1.2V
+/-1mA
+/-1mA
+/-1mA
+/-1mA
triggering
gain
SW/Timer/Cont N/A
SW/Timer/Cont N/A
SW/Cont
to 32x
SW/Cont
to 32x
features
DTC
Conv Mem
Preload
Buffered input
range to be measured?
Bits
24
Max frequency for AIN?
20
Sigma-Delta
How much resolution?
16
SAR
Differential inputs?
12
Slope
Reference range?
8
10
100 1k 10k 100k 1M
Samples
per Second
Multiple channels?
Lab6: ADC10
• Measure internal temperature
•Additional CCS features
Lab 6:
//Configure ADC10
// Choose ADC Channel as Temp Sensor
ADC10CTL1 = _______ + ADC10DIV_3;
//Choose ADC Ref sourceCCTL1
ADC10CTL0 = _______ + ADC10SHT_3 + REFON + ADC10ON +ADC10IE;
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
USI
MSP430G2xx1/2 devices
Variable length shift
register
Supports I2C
Supports SPI
83
START/STOP detection
SCL held after START
SCL held after counter
overflow
Arbitration lost
detection
8/16-bit Shift Register
MSB/LSB first
Flexible Clocking
Interrupt Driven
SDO
8/16-Bit Shift
Register
Bit Counter
USIIFG
USIIFG
USISTTIFG
SCLK
ACLK
SMCLK
SWCLK
TA0
TA1
TA2
SDA
SDI
START
STOP
Detect
SCL Hold
Divider
HOLD
USIIFG
USISTTIFG
USISTP
SCL
SCLK
USI for Data I/O
Data
shift register: up to 16
bits supported
Number of bits transmitted
and received is controlled
by a bit counter
Transmit and Receive is
simultaneous
Data I/O is user-defined:
MSB or LSB first
Bit counter automatically
stops clocking after last bit
& sets flag
No data buffering needed
84
Data Shift
Register
Data I/O
USICNTx
Bit Counter
USISSELx
SCLK
ACLK
SMCLK
SMCLK
USISWCLK
TA0
TA1
TA2
USIDIVx
Clock Divider
/1/2/4/8…/128
HOLD
USIIFG
Set USIIFG
USI Reduces CPU Load for SPI
Peripheral
MSP430
SCLK
SDO
SDIN
//Shift16_inout_Software
SR = DATA;
for (CNT=0x10;CNT>0;CNT--)
{
P2OUT &= ~SDO;
if (SR & 0x8000)
P2OUT |= SDO;
SR = SR << 1;
if (P2IN & SDIN)
SR |= 0x01;
P2OUT |= SCLK;
P2OUT &= ~SCLK;
}
425 Cycles
85
// Shift16_inout_USI
USISR |= DATA;
USICNT |= 0x10;
10 Cycles
I2C Slave has as little as 4us
from clock edge to data
Traditional software-only
solution allows time for little else
USI hardware enables practical
and compliant I2C
Code on MSP430 website
USCI
Designed for Ultra-Low Power:
Auto-Start from any
Low-Power Mode
Two Individual Blocks:
SMCLK
ACLK
UCAxCLK
USCI_A:
UART or SPI
USCI_B:
SPI or I2C
Double Buffered TX/RX
Baudrate/Bit Clock Generator:
USCI_A
Auto-Baud Rate Detect
Flexible Clock Source
UART
SPI
IrDA
7
UCx
Serial Interface
USCI_B
SMCLK
ACLK
UCBxCLK
RX glitch suppression
DMA enabled
Error Detection
Recommended USCI initialization/re-configuration
process is shown in your workbook.
88
Baud Rate
Generator
SPI
I2C
Bit Clock
Generator
4
Serial Interface
UCx
USCI Enhanced Features
New standard MSP430 serial interface
Auto clock start from any LPMx
Two independent communication blocks
Asynchronous communication modes
UART standard and multiprocessor protocols
UART with automatic Baud rate detection
(LIN support)
Two modulators support n/16 bit timing
IrDA bit shaping encoder and decoder
Synchronous communication modes
SPI (Master & Slave modes, 3 & 4 wire)
I2C (Master & Slave modes)
UxRXBUF
Receiver Shift
Register
UCLKI
ACLK
SMCLK
SMCLK
URXD
SOMI
Baud-Rate
Generator
STE
SIMO
Transmit Shift
Register
UTXD
UxTXBUF
Clock Phase and Polarity
89
UCLK
USCI Baudrate Generator
Oversampling Baud Rate Generation
Two Modulators:
UCBRSx and UCBRFx select modulation pattern
RX sampled using BITCLK16
LSB UCAxBR0
UC0CLK
ACLK
SMCLK
SMCLK
UCAxBR1
8
8
Prescaler/Divider
1st Modulator
BITCLK16
3
UCBRSx
BITCLK16
/16
RXD
2nd Modulator
4
UCBRFx
90
BITCLK
1 Bit
Sampling for majority votes
Value Line Communication Modules
USI
USCI
Universal Serial
Communication Interface
G2xx1/2
U
A
R
T
S
P
I
I
2
C
82
Two modulators; supports
n/16 timings
- Auto baud rate detection
- IrDA encoder & decoder
- Simultaneous USCI_A
USCI_B (2 channels)
Two SPI (one each on
USCI_A and USCI_B)
- Master and slave modes
- 3 and 4 wire modes
- Simplified interrupt usage
- Master and slave modes
- Up to 400kbps
Universal Serial
Interface
G2xx3
--. and
- One SPI available
- Master and slave modes
- SW state machine needed
- Master and slave modes
Low-Overhead UART Implementation
MSP430
TA0/P1.1
P2.2/TA0
RXD
compare - logic level latched in SCCI
- add 1 bit length to CCR0
TXD
SCCI
A
Y EN
Stop
Capture/Compare
Start
Output
Unit0
- CCR0 = TAR
- add 1.5 bit length to CCR0
- switch to compare mode
OUTMODx
76
100% hardware bit latching and output
Full speed from LPM3 and LPM4
Low CPU Overhead
App Note SLAA078 on web
Software UART Implementation
A simple UART implementation, using the Capture &
Compare features of the Timer to emulate the UART
communication
Half-duplex and relatively low baud rate (9600 baud
recommended limit), but 2400 baud in our code (1 MHz DCO
and no crystal)
Bit-time (how many clock ticks one baud is) is calculated
based on the timer clock & the baud rate
One CCR register is set up to TX in Timer Compare mode,
toggling based on whether the corresponding bit is 0 or 1
The other CCR register is set up to RX in Timer Capture
mode, similar principle
The functions are set up to TX or RX a single byte (8-bit)
appended by the start bit & stop bit
Application note: http://focus.ti.com/lit/an/slaa078a/slaa078a.pdf
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
GraceTM
Grace
™
A free, graphical user interface that
generates source code and eliminates
manual peripheral configuration
Visually Enable & Configure MSP430 Peripherals
Developers can interface
with buttons, drop downs,
and text fields to
effortlessly navigate high
above low-level register
settings
Grace generates fully
commented C code for all
F2xx and G2xx Value Line
Microcontrollers from
MSP430
What is Grace?
Grace – Graphical Code Engine
Is:
• Generates MSP430 peripheral initialization code in CCSv4
• Enable a new user to have running program in 15 minutes
• Heavy emphasis on ease of use
• Currently in “Public Beta” stage
• Will extend to cover all MCU devices
Is not:
• Graphical application builder
01/26/2011
TI Confidential – NDA Restrictions
98
Project Structure and Build Flow
“xxxxx.cfg”
Application
C/C++
Source Files
This is the device peripheral configuration file and
is edited with the graphical Grace view.
“src” Folder
Automatically generated inside the “Debug” or
“Release” folder. Contains MSP430 C-code
that initializes all configured peripherals.
C/C++ Compiler
01/26/2011
Linker
TI Confidential – NDA Restrictions
Final Executable
MSP430 Output File
99
User Code Skeleton Example
/*
* ======== Standard MSP430 includes ========
*/
#include <msp430.h>
You know this one…
/*
* ======== Grace related includes ========
*/
#include <ti/mcu/msp430/csl/CSL.h>
/*
* ======== main ========
*/
int main(int argc, char *argv[])
{
// Activate Grace-generated configuration
CSL_init();
Master include file for all
Grace-related content
Performs all Graceconfigured peripheral setup
__enable_interrupt(); // Set GIE
// >>>>> Fill-in user code here <<<<<
User code from here…
return (0);
}
01/26/2011
TI Confidential – NDA Restrictions
100
Grace – Adding a Peripheral
• Right-click on the peripheral and select “Use”
• All blocks shaded blue can be configured
01/26/2011
TI Confidential – NDA Restrictions
101
How to tell a peripheral is added?
• Look at the bottom left corner of the peripheral on the CSL
view, it will show a checkmark if the peripheral is initialized.
01/26/2011
TI Confidential – NDA Restrictions
102
Grace – Navigation
• Left-click on a peripheral to navigate to its detail view
• Use home button to go back to the top-level device view
• Forward/backward buttons are available as well
01/26/2011
TI Confidential – NDA Restrictions
103
Grace – Configuring a Peripheral
• Each peripheral has 4 different representations:
“Overview,”
“Basic User”,
“Power User”,
“Registers”
• You can edit any
of the them, they
are all connected
• Validate the
current config by
clicking “Refresh”
01/26/2011
TI Confidential – NDA Restrictions
104
Grace – Removing a Peripheral
• Right-click on the peripheral and select “Stop Using”
01/26/2011
TI Confidential – NDA Restrictions
105
Lab8: Grace
• Use Grace to configure all the
required peripherals
• To do Lab3 again
• Enter LPM4
Lab 8: step by step
• Disable the Watchdog timer
• Configure the DCO to run off the internal pre-calibrated
8MHz constants
• Setup the LaunchPad’s S2 button for interrupt operation
• Enter LPM4 in the main() function
• Provide a button interrupt handler that clears the IFGs and
wakes up the MCU upon return
• Toggle between the red LED in main()
• Enter LPM4 in the main() again
01/26/2011
TI Confidential – NDA Restrictions
107
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
What is Capacitive Touch?
C4
C3
text
C1
C2
A change in Capacitance …
When a conductive element is present - Finger or stylus
• Add C3 and C4, resulting in an increase in capacitance C1 + C2 + C3||C4
• This becomes part of the free space coupling path to earth ground
When the dielectric (typically air) is displaced
• Thick gloves or liquid results in air displacement and change in dielectric
• Capacitance is directly proportional to dielectric, capacitance (C2) increases
(air ~1, everything else > 1)
MSP430 Capacitive Touch Options
Pin oscillator method
(PinOsc with internal RO)
< 3uA/Button
No external components required
Timer used
Currently MSP430G2xx2 and MSP430G2xx3
RO method
10uA/Button
Most robust against interference
Timer used, comparator used
MSP430 devices with comparator
RC method
Lowest power method
Supports up to 16 keys
GPIO plus timer used
Any MSP430 device
1uA/Button
Library Structure
Configuration
APPLICATION LAYER:
0/1
Z
X
Offset
Array of deltas
A
Schedule:
Sensor
Peripherals
Period definition
16bit
Capacitance
Compensation
Capacitance Sensor
Sensor Delta
Wheel
Slider
Proximity
Button
CAP TOUCH
LAYER
SCHEDULER
Sensor:
Electrodes
Reference
Sensor Type
Measurement Method
Peripherals
Peripheral settings
Measurement Parameters
Determination of threshold crossing
PHYSICAL LAYER:
PinOsc
Fast Scan RO
RO
RC
HAL
Filter Method Type:
Element:
Port I/O
definitions
Capacitive Touch BoosterPack
Part Number: 430BOOST-SENSE1
• Capacitive Touch plug-in
for LaunchPad
• Touch button, scroll wheel
& proximity sensor
• Includes MSP430G2xx2
with Cap Touch I/O module
• Example design for scroll
wheels & Proximity sensor
• Full support for Capacitive
Touch Library
• Only $10
• www.ti.com/capacitivetouch
Thank you!
