Transferring Technical Knowledge to Practical Applications

Intended Audience:
• Electrical engineers with a knowledge of simple electrical circuits
• An understanding of MOSFET devices
Topics Covered:
• What is Electrostatic Discharge (ESD)
• What is Electrical Over Stress (EOS)
• What is Safe Operating Area (SOA)
Expected Time:
• Approximately 90 minutes

• What is ESD
– Where does ESD come from
– MOSFET Gate susceptibility
– Test Standards
– Component level vs. module level tests
• What is EOS
• What is SOA

• We are all familiar with a common form of electrostatic discharge (ESD):
Shaggy Carpet
• ESD is the sudden transfer of electrostatic charge between objects at different electrostatic potentials

• Triboelectric Charging
– Mechanical Contact and Separation
– “Walking on carpet”
 Direct Charging
– Mobile Charge Transfer
– “Plugging in a cable” (e.g. USB to PC)
 Ionic Charging
– Not properly balanced Air Ionizer can charge an object (instead of intended operation to neutralize/balance charge)
–Charged object comes into contact with a grounded object (such as machine pick-up probe or grounded human operator)
–This is example of charged device model (CDM) event—more to come!!!

• Which levels can occur?
– Below 3-4kV you see, hear or feel nothing!
– Just above 4kV, air-gap-sparks can occur
– 1mm == 1kV (5mm spark ~ 5kV)
 Why does a 2kV protected device survive the real world?
– You are charged relatively to earth, not to “pin7”
– You do not have 4kV between your thumb and your index finger

• Influence of Air Humidity
– Higher relative air humidity does cause a
“moisture” film on surfaces
– Charge is more distributed, lower voltages thus occur
– But dry air does not have a higher inherent
“resistance”
4
3
6
5
2
1
8
7
10
9
16
15
14
13
12
11 office room (winter) without air humidity regulation synthetic wool anti-static
5 10 20 30 40 50 60 70 80 90
15% 35%
100
% Relative Air Humidity

Source
Often, the source is grounded
Gate
Insulating
SiO
2
Gate
Drain
SiO
2 n n p-type

Source Gate
But, the charge is
Drain stuck on gate due to insulating SiO
2
SiO
2 n
Cgs n p-type

Voltage
• Think of voltage as an amount of possible electrical work
• A high voltage means additional electrical work is possible
• If the voltage is improperly directed or used, unintended (and potentially harmful) work will be performed
+12V Ground
Battery
Capacitance

• Variables and Constants:
C

Capacitance
Q

Charge
V

Voltage
 
0 ox

Permittivity of Silicon Dioxide
A

Area of Capacitor Plates d

Distance Between Conductors
• Two Basic Equations:
C

Q
V
C


0 ox d
A
• Rearranging yields:
V

Q

C
Q
 
0 ox
A d

Qd
  ox
A

V

Qd
  ox
A
•
 
0 ox is a constant for a given material (SiO
2
)
• As the charge (Q) on the capacitor increases the voltage across the capacitor increases….

V
GATE

Q d
GATE
 
0 ox
A
V
GATE

100 V
POP

2
Allowable E-field within SiO
2 exceeded

2
MOSFET cannot turn on
Gate-Source
Short

V

Qd
  ox
A
• As the charge (Q) on the capacitor increases the voltage across the capacitor increases….
• If the transistor decreases in size the thickness of the SiO
2 gate (d) decreases but, the area (A) of the gate decreases faster -
• For the same amount of charge, the voltage across the capacitor is higher for a smaller transistor
• More advanced technologies may require additional ESD precautions



• 3
 m Process (Minimum Size Transistor)
– t ox
= 400
– L = 3
 m
Å = 4x10 -8 m
– W = 3
 m
V

– Q = 1.16x10
-11 C
  

1.16 10

11
C

12
F m


4.0 10

8 m x

6 m


3.0 10

6 m


1.5
kV
• 1.2
 m Process (Minimum Size Transistor)
– t ox
= 200 Å
– L = 1.2
 m
= 2x10 -8
V m

– W = 1.2
 m



11 C


2.0 10

8 m
 

12
F m x

6 m


1.2 10

6 m

– Q = 1.16x10
-11 C

4.7
kV
Note:
0 OX
(3.9)(8.85x10
-12 F/m )

• ESD Standards & Tests should simulate “real world” events as realistic as possible
• There is no “single/one size fits all” ESD Test available 
Different handling/mounting conditions have resulted in different ESD tests
– e.g. car-manufacturers follow different ESD standards than componentsuppliers: both are talking about ESD but not about the same applied ESD- standards
 Be careful to know complete standard definition
– “ESD 2kV”, “2kV HBM” ,… does not mean much: The Standard is missing
 e.g JEDEC22-A114; MIL-STD883, Method 3015.7, ……(more complete)

ESD Standards & Tests: Overview
• A “ Standard ” consists of …
– … a used MODEL
(HBM, MM, …)
– … VALUES for the elements used in the model
(R=1500 Ohm, C=100pF)
– … plus
TEST PROCEDURE: how to apply the standard
(e.g. 3 pulses)
Standard = Model + Values + Procedure
 Therefore Standards can differ in each subset, in the
–
MODEL
–
VALUES
–
TEST PROCEDURE
 “ HBM 2kV” is not specific
– “2kV JEDEC22-A114” is better defined

ESD Models: Human Body Model
R
• Human Body Model (HBM) consists of a Capacitor and a series Resistor
• Values are defined in the specific standard
– Commonly used: C =100pf, R=1500
Ohm (JEDEC, Mil, etc.)
• Test Procedure is defined in the specific standard
– Commonly used: 1 to 3 pulses, both polarities, 3 devices/voltage level
Commonly used for component tests
C
Model
HBM Standards
(R=1500 Ohm, C=100 pF)
•
JEDEC JESD 22-A114 [2]
• Military Standard Mil.883 3015.7 [3]
• ANSI/ESD STM5.1 [4]
• IEC 61340-3-1
“Human ESD Model”
(R=2000 Ohm, C=150 pF
– 330 pF)
• ISO/TR 10605 [5]
“Human Body Representative”
(R=330 Ohm, C=150 pF)
• IEC 61000-4-2 [6]


• HBM Jedec22-A1114
Waveform:
1kV
– 10ns rise time typically (short)
• 2-10ns are allowed
– Peak current:
• Rule of Thumb:
– 1kV = 2/3 Ampere
Ipeak

Vesd
1500
W
]
V
ESD
(V) I peak -
I peak+10%
(A)
1000
2000
0.67 – 0.74
1.33 – 1.45

• Machine Model (MM) consists of a
Capacitor and no series Resistor
• Values are defined in the specific standard
– Commonly used: C =200pF,
• Test Procedure is defined in the specific standard
– Commonly used: 1 to 3 pulses, both polarities, 3 devices/level
Some definitions use MM
“standard” with a 25 Ohm series resistor, which at least doubles the achievable ESD Level!
Model
C
MM Standards
(C=200 pf)
• JEDEC JESD 22-A115 [11]
• ANSI/ESD STM5.2
“Philips Standard”
( C=200 pF, R=10-25 Ohm, L=0.75-
2.5µH)
• Standard??

• MM stress is similar to
HBM
– Oscillations due to setup parasitics
• MM and HBM failure modes are similar
• Less reproducible than
HBM
Source: T. Brodbeck; Models.pdf
V
ESD
(kV) I peak -
I peak+30%
(A)
0.1
0.2
1.5 - 2.0
2.8 - 3.8

• Models an ESD event which occurs when a device acquires electrostatic charge and then touches a grounded object
Device discharges Device placed through ground probe in dead-bug position
Dielectric
Field Plate
High Voltage Source

CDM Waveform: Highly dependent on die size and package capacitance
500V with 4pF verification module t r
<400psec / I p1
~4.5A / I p2
<0.5I
p1
Source: AEC-Q100-011B
/ I p3
<0.25I
p1

• Automotive Electronic Council (AEC) Stress
Test Qualification “ 100 ” : AEC Q100 – xxx
AEC is not a single standard but a collection of requirements for automotive suppliers
 AEC Q100 validated suppliers have to fulfill the ESD regarding qualification described in it
– AEC Q100-002: HBM (JEDEC) 2000V OR AEC Q100-003: MM
(JEDEC) 200V
AND
– AEC Q100-011: CDM (JEDEC)
 Corner Pins 750V / Non-corner pins 500V

Component vs. Module level tests
• ESD (pulses) testing originates from a subset of the wide field of EMC
(Electromagnetic Compatibility, EMI … Immunity)
• Due to the importance in the Semiconductor Industry, ESD testing has evolved into its own field of specialization
 The ESD/EMC world in general can be divided into two mainfields:
(Powered) Systems (Unpowered) Components

ESD Standards & Tests:
System vs. Component
Goal: UNDISTURBED functionality during and after ESD stress under powered / functional conditions
Goal: UNDESTROYED components after ESD stress:
All specification-parameters should stay within its limits
ESD is a part of EMC qualification
Different “behavior criteria” in response to
ESD on system level exists (class A to D)
 Just dedicated pin combinations feasible
 I/O vs. GND
 The reference/enemy is always earth potential
 Relative measure of robustness of end product during operation
ESD is a part of product qualification
“Pass”/”fail” criteria
 All pin combinations can occur and are tested
 Relative measure of robustness during handling/manufacturing

Module/System Level
Human Body Model
(HBM)
150pF / 330
W
EN 61000-4-2
(so called “GUN Test”)
Component Level
Human Body Model (HBM)
100pF / 1500
W
JEDEC-Norm JESD22-A114-B
(MIL-STD883D, method 3015)
Human Body Model (HBM)
150pF / 2000
W
ISO 10605
Human Body Model (HBM)
330pF / 2000
W
ISO 10605
Machine Model (MM)
200pF / 0
W
JEDEC-Norm JESD22-A115-A
(correlates to HBM)
Charged Device Model (CDM)
Package pF / 0
W
JEDEC-Norm JESD22-C101-A


• A “ Pin-to-Pin ” ESD Tester
(like HBM, MM Testers) consists of the HV source and the model with its values, connected to two “ Terminals ”
HV
C
R Terminal A
Terminal B
• The Terminals are not changed for polarity reversal …
 The capacitance is charged one time positively and one time negatively
 Tester-Ground along with parasitics stay constant


• 2 different Pin-Combination-Types are tested
– Supply-Pin-Tests
• All Pins (individually one at a time) at Terminal A vs. Supply-X at
Terminal B
• Repeat for Supply-Y, Supply-Z, etc. at Terminal B
– Non-Supply-Pin-Test
• “All Non-Supplies (individually one at a time) at Terminal A vs. all other non-supplies together at Terminal B”
• Repeat for each non-supply at Terminal A
• 1 positive and 1 negative pulse for each pin-combination
• Step-Stress, 500V, 1kV, 2kV and 4kV should be used; different levels and steps can be defined
– A new set of 3 devices per level is used
ESD Product Qualification Test @ IFX according to
JEDEC EIA/JESD 22-A114-B [2] described in IFX
Procedure [1]

ESD Supply-Pin Test: HBM ESD Each pin vs. Supply-1 (GND)
• ESD Test P1.1
– All pins vs. Supply 1 (in this case GND)
– In this case:
• 10 different combinations
• 1+ and 1- pulse for each combination
•  20 pulses for each voltage step

ESD Supply-Pin Test: HBM ESD Each pin vs. Supply-2 (VBB)
• ESD Test P1.2
– All pins vs. Supply 2 (in this case VBB)
– Then subsequently All pins vs. Supply 3 (Vdd)
– In this case:
• 11 different combinations
• 1+ and 1- pulse for each combination
•  22 pulses for each voltage step

ESD Non-Supply-Pin Test: HBM ESD Each nonsupply vs all other non-supply
• ESD Test P2
– Each non-supply vs. All other non-supply
– One non-supply at a time on Terminal A
– All other non-supplies at Terminal B
– In this case:
• 8 different combinations
• 1+ and 1- pulse for each combination
•  16 pulses for each voltage step

• Direct Discharge: Test points of normal accessibility.
– The Reference-’”Pin” at
System-Level test is “Earth” and not a part of the DUT
• Indirect Discharge into couple plate: Test for radiated disturbance immunity

• Some Customers ask for systemlevel test at component level
– Component is not powered
– Only pins which are accessible to the outside world are tested
– Reference pin(s) are the component ground pin(s)
– Pass/Fail according to Component test-program
– ESD current is 5x higher at a dedicated voltage level compared to component
ESD tests
7.5A
ESD @ 2kV
Red: IEC (“GUN”)
Blue: JEDEC “HBM”
1.3A
1ns 10ns

Discharge generated Pulses (RC)
Application Standard/Pulse
Vma x [V]
Duratio n
(10-
90%)
Component "HBM" JESD 22-114 8000 150ns
"GUN" IEC 61000-4-
2 8000 120ns System
System/Vehic le
System/Vehic le
ISO/TR 10605 inside 8000
ISO/TR 10605 outside
1µs
# of Pulses
Ri
[Ohm]
C
[pF
]
1 1500 100
10 330 150
3 2000 330
8000 360ns 3 2000 150
Voltage generated Pulses
Vehicle ISO 7637: 1 -100 2ms 5000 10 -
Ipeak
[A] Charge
5.3
800nC
33 1.2µC
30 2.64µC
30 1.2µC
Vehicle
Vehicle
Vehicle
ISO 7637: 2
ISO 7637: 3a
ISO 7637: 3b
100 50µs
150 100ns
150 100ns
5000
1h
(3.6x10^6)
1h
(3.6x10^6)
10 -
50 -
Charge relatively to HBM,
JESD22-
114
1
1.5
3.3
1.5
10 20mC 25x10^3
10 0.5nC
6.25x10^-
4
3 300nC
2 200nC
0.375
0.25

Very small damage area due to low energy of ESD pulses, normally cannot be seen with “naked eye”

This device had a G-S short and you can see the burn mark is right at the boundary region of gate poly and source metal which is common since this is the area of highest
E field strength
Gate contact metal Gate Polysilicon Source contact metal

• Electrostatic discharge sensitive components can be protected in an automobile
• Installation of spark gap topologies
• Establishing a predictable charge well topology such as capacitors

Decrease ESD Sensitivity with a
Predictable Charge Well Topology
• Recall our earlier equation:
V

Qd
  ox
A
• Place a capacitor across the device/pin to be protected
• The additional external capacitor sheds the electrostatic discharge energy, reducing the voltage at the pins of the semiconductor device

Decrease ESD Sensitivity with a
Predictable Charge Well Topology
ESD generator IC
Protected
Pin
C protection
ESD current/charge
For most robust design, the voltage at this point should be lowered to be less than internal ESD structure breakdown voltage so all current/energy is shed thru external capacitor. Please note that there is no resistor between C_prot and IC so high current/energy can flow into IC if internal ESD structure breaks down and begins to conduct current

Decrease ESD Sensitivity with a
Predictable Charge Well Topology
• System level/gun tests ESD voltages may need to be 15,000V
(direct contact)
– Gun tests uses 330pf for source capacitor
• For automotive technologies having ESD structures with 40-
45V breakdown is common
C
_prot
= (C
_gun
/ V br_ESD
) * V
_gun
= (330pF / 45V) * 15kV
= 110nF

Ground Referenced Protection V
Supply
IC
Referenced Protection
V
Supply
External
Pin
IC

• Electrostatic discharge occurs when excessive static charge on an object builds up to a very high voltage (thousands of volts) and causes device damage during contact and subsequent discharge (current flow) with another object
• MOS devices with insulating SiO
2 susceptible to ESD damage gates are especially
• Different test standards have evolved for component level and system level tests and confusion can result if these standards are not understood and clarified in reports and communication
• The very fast (HBM=nsecs / CDM=psecs) ESD pulses have low energy and result in VERY small physical damage signatures

• What is ESD
– Where does ESD come from
– MOSFET Gate susceptibility
– Test Standards
– Component level vs. module level tests
• What is EOS
• What is SOA

• Electrical Over Stress is exactly what it says….
A device is electrically stressed over it’s specified limits in terms of voltage, current, and/or power/energy
• Unlike ESD events, EOS is the result of "long" duration stress events (millisecond duration or longer)
– Excessive energy from turning off inductive loads
– Load Dump
– Extended operation at junction temperatures > 150degC
– Repetitive excessive thermal cycling
– Excessive/extended EMC exposure, etc.
• EOS often results in large scorch marks, discoloration of metal, melted metallization and/or bond wires, and massive destruction of the semiconductor component

• Failures from EOS can result in the following:
– Hard failure: failure is immediate and results in a complete non-operational device
– Soft failure: EOS results in a marginal failure or a shift in parametric performance of the device
– Latent failure: At first the EOS results in a non-catastrophic damage but after a period of time further degradation occurs resulting in a hard or soft failure

Lifetime
10 000 h
Point of accelerated device qualification
Lifetime curve for device worst case parameters
1 000 h
100 h
270°C
10 h
1 h
0.1 h
170°C
Overtemperature shutdown
220°C 260°C
Soldering
Ⅰ
Spec valid, full lifetime, full function
150°C
Ⅱ 200°C
Spec restricted, reduced lifetime, limited functionality
Ⅲ 270°C
No spec, no permanent damage, highly reduced lifetime, no function guaranteed app. 350°C
Irreversible damage
Device temperature
350°C Ⅳ
Device destruction, irreversible damage, permanent out of control

Scorched/Melted metal (≥650ºC)
Degradation/recrystalisation of metal (≥400ºC)
---also repetitive fast transients<100
ºC
Melted silicon (≥1200ºC)

EOS Failure Signatures---Generalities
Visualization of single- and repetitive pulse events
: max. Chip temperature single mode melting point in thermal hot spot repetitive mode number of cycles
1 (e.g.) 10 2 10 6
This isn‘t a completely black & white effect, but there can be a significant difference in single- and repetitive pulse failure signatures

EOS: Failure signature from excessive inductive turn-off energy
• Example – Inductive clamp single pulse
I
DS(start)
=10A, t=11.8 ms, T=25 ° C, V bb
= 12V
I_ramp(10A/11.8ms) E=2.14 Joules
Failure signature (10A):
- No metal degradation
- Scorch in DMOS field
- NO bond fuse
EOS at the
„hot spot“
No metal degradation near bond

EOS: Failure signature from repetitive thermal cycling combined with high current
Severely degraded recrystalized metal

• A common failure for electrical over stresses is
MELTED METALLIZATION AND/OR BOND WIRES
Gold Wire DC Ratings*
50
 m
2.5A
Aluminum Wire DC Ratings*
350
 m
40A
25
 m
1A
50
 m
2A
*Assumes T
J
< 150C, T
Leads
< 85C, T
Wire
< 220C, and Wire Length<3mm
125
 m
8A

• Put components in/out of sockets while power already applied (hot plug)
• Applying electrical signals which exceeds a component’s ratings
• Apply an input signal to a device before applying supply voltage and/or ground
• Apply an input signal to a device output
• Use an inexpensive power supply (supply overshoot)
• Provide insufficient noise filtering on the board’s input line(s)
• Use a poor ground with high resistance and inductance

• Electrical over stress refers to a condition when a device is electrically stressed over its specified limits
• EOS often catastrophically damages devices by degrading or melting of metallization and bond wires
• Operation of devices within the specified Safe
Operating Area will eliminate electrical over stress damage

• What is ESD
– Where does ESD come from
– MOSFET Gate susceptibility
– Test Standards
– Component level vs. module level tests
• What is EOS
• What is SOA

• The safe operating area is a set of conditions specified for a certain device
• Within the safe operating area, the semiconductor component is specified to operate as expected
• By definition, no electrical over stress occurs within the specified safe operating area

• Single pulse, T case
= 25C, T junction
< 125C
100A
4
 s
15
 s
50
 s
10A
200
 s
1ms
1A
DC
0.1A
1V 10V 100V
V
DS
, Drain-Source Voltage
1000V

• V
OUT
150mA
= 5V, T junction
< 150C
Soldered to board with 3cm 2 copper heatsink
100mA
T a
= 25C
50mA
0A
10V 15V 20V
V
IN
, Input Voltage
25V
T a
= 85C
T a
= 125C

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