COE 202: Digital Logic Design
Sequential Circuits
Part 1
Dr. Ahmad Almulhem
Email: ahmadsm AT kfupm
Phone: 860-7554
Office: 22-324
Ahmad Almulhem, KFUPM 2009
Objectives
• Sequential Circuits
• Memory Elements
• Latches
• Flip-Flops
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Combinational vs Sequential
inputs X
Combinational
Circuits
outputs Z
A combinational circuit:
• At any time, outputs depends only on inputs
• Changing inputs changes outputs
• No regard for previous inputs
• No memory (history)
• Time is ignored !
Ahmad Almulhem, KFUPM 2009
Combinational vs Sequential
inputs X
Combinational
Circuits
outputs Z
next state
present state
Memory
A sequential circuit:
• outputs depends on inputs and previous inputs
• Previous inputs are stored as binary information into
memory
• The stored information at any time defines a state
• next state depends on inputs and present state
Ahmad Almulhem, KFUPM 2009
Examples of sequential systems
Traffic light
ATM
Vending machine
What is common between these systems?
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Combinational Adder
• 4-bit adder (ripple-carry)
• Notice how carry-out propagates
• One adder is active at a time
• 4 full adders are needed
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Sequential Adder




1-bit memory and 2 4-bit memory
Only one full-adder!
4 clocks to get the output
The 1-bit memory defines the circuit state (0 or 1)
Ahmad Almulhem, KFUPM 2009
Types of Sequential Circuits
• Two types of sequential circuits:
• Synchronous: The behavior of the circuit
depends on the input signal values at discrete
intervals of time (also called clocked)
• Asynchronous: The behavior of the circuit
depends on the order of change of the input
signals at any instance of time (continuous)
Ahmad Almulhem, KFUPM 2009
Clock
inputs X
Combinational
Circuits
outputs Z
next state
present state
Memory
clock
• A clock generator produces a periodic train of pulses
(alternating 0s and 1s)
• A clock signal is required for generating discrete time intervals in
synchronous circuits
• The memory/state changes with the clock
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Memory - Latches
•
•
•
•
•
A latch is binary storage component
Can store a 0 or 1
The most basic memory element
Built with gates (NORs, NANDs)
Can be used to build flip-flops
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SR Latch
What does this circuit do?
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SR Latch
•
•
•
•
Two states: Set (Q = 1) and Reset (Q = 0)
When S=R=0, Q remains the same, S=R=1 is not allowed!
Provide a simple form of memory
State of the circuit depends not only on the current inputs,
but also on the recent history of the inputs
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S’ R’ Latch
How about this circuit?
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S’ R’ Latch
•
•
•
•
Similar to SR latch (complemented)
Two states: Set (Q = 0) and Reset (Q = 1)
When S=R=1, Q remains the same
S=R=0 is not allowed!
Ahmad Almulhem, KFUPM 2009
SR Latch with Clock
• An additional input signal (Clock) can be introduced to
make sure that the operation of the latch is modified
depending on the value of the Clock (C) signal
• When C=0, the S and R inputs have no effect on the latch
• When C=1, the inputs affect the state of the latch and
possibly the output
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D Latch
How can we eliminate the undefined state?
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D Latch
• Ensure S and R are
never equal to 1 at
the same time
• Add inverter
• D stands for data
• Output follows the
input when C = 1
• When C = 0, Q
remains the same
Ahmad Almulhem, KFUPM 2009
Characteristic Table
• Similar to the truth table in combinational circuits
• Next state is defined in terms of the current state and
the inputs
• K-Map can be used to obtain the characteristic
equation
• The indeterminate states can be expressed as don’t
cares
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Characteristic Table – SR Latch
Q(t)
S
R
Q(t+1)
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
undefined
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
undefined
Ahmad Almulhem, KFUPM 2009
Characteristic Table – SR Latch
Q(t)
S
R
Q(t+1)
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
undefined
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
undefined
Characteristic Equation
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S=R=1 is not permitted,
therefore this condition is
all included here
Characteristic Table – D Latch
Q(t)
D
Q(t+1)
0
0
0
0
1
1
1
0
0
1
1
1
Ahmad Almulhem, KFUPM 2009
Characteristic Table – D Latch
Q(t)
D
Q(t+1)
0
0
0
0
1
1
1
0
0
1
1
1
Characteristic Equation for
the D Latch
Ahmad Almulhem, KFUPM 2009
Excitation Table
• Defines the input conditions for which a certain next state
is reached from a certain current state for a circuit
• Lists the inputs for moving from one state to another
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Excitation Table
• Defines the input conditions for which a certain next state
is reached from a certain current state for a circuit
• Lists the inputs for moving from one state to another
Example: SR Latch
Q(t)
Q(t+1)
S
R
0
0
0
X
0
1
1
0
1
0
0
1
1
1
X
0
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Clocked JK Latch
extra feedbacks
How does it work?
Function table?
Characteristic Table/Equations?
Excitation Table?
Ahmad Almulhem, KFUPM 2009
Clocked JK Latch
•
•
•
•
The JK latch improves on the SR latch by ensuring that the no input
combination will lead to an indeterminate state
The outputs of this latch (Q, Q’) are coupled back to the latch input
J and K behave like S and R.
• J implies the Set
• K implies the Reset
For J=K=1, the latch switches to its complement state, i.e. Q becomes 0 if
it was already 1 and vice versa
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JK Latch – Characteristic Table
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JK Latch – Excitation Table
• For the next state and present
state to be equal to 0, J must
be equal to 0
• For both next and current
states to be equal to 1, K must
be equal to 0
• To change state from 0 to 1, J
must be 1
• To change state from 1 to 1, K
must be 1
Ahmad Almulhem, KFUPM 2009
Clocked T Latch
• The clocked T latch is a single input version of the JK latch
• The letter ‘T’ stands for Toggle, as it toggles the current
state when equal to 1
• When T=1, the next state is the complement of the current
state
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T Latch (Tables)
Characteristic table/equation
Functional table
Excitation table
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Problem with Latches
Clock
•
•
•
D
Q
C
Q
Q
What happens Clock=1? What will be the value of Q when Clock
goes to 0?
Problem: A latch is transparent; state keep changing as long as
the clock remains active
Due to this uncertainty, latches can not be reliably used as storage
elements.
Ahmad Almulhem, KFUPM 2009
Flip Flops
•
•
•
•
A flip-flop is a one bit memory similar to latches
Solves the issue of latch transparency
Latches are level sensitive
Flip-Flops are edge-triggered or edge-sensitive
level
positive (rising) edge
negative (falling) edge
Ahmad Almulhem, KFUPM 2009
Flip Flops Implementation
Two methods:
• Master-Slave
• Two latches (master and slave) and additional logic
• Edge-Triggered
• Usually implemented differently at the transistor level
• Can also be built with latches similar to master-slave
implementation
Ahmad Almulhem, KFUPM 2009
Master-Slave SR Flip Flop
•
Built using two latches
(Master and Slave)
•
•
•
•
C = 1, master is active
C = 0, slave is active
Q is sampled at the
falling edge
Also called pulsetriggered: data is
entered on the rising
edge of the clock pulse,
but the output does not
reflect the change until
the falling edge of the
clock pulse.
Ahmad Almulhem, KFUPM 2009
Master-Slave JK Flip Flop
• Two SR Latches (master and slave)
• Function is similar to JK Latch but
transparency issue is solved
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Edge-Triggered D Flip Flop
-ve (falling) edge
+ve (rising) edge
• This flip-flop takes exactly the form of a master-slave flipflop, with the master a D latch and the slave an SR latch.
Also, an inverter is added to the clock input of the master
latch.
• Because the master latch is a D latch, the flip-flop exhibits
edge-triggered rather than master-slave (pulse-triggered)
behavior.
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Standard Symbols
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Direct Inputs
• At power up or at reset, all or part
of a sequential circuit usually is
initialized to a known state before
it begins operation
• This initialization is often done
outside of the clocked behavior
of the circuit, i.e., asynchronously.
S
D
C
R
Q
Q
• Direct R and/or S inputs that control the state of the latches
within the flip-flops are used for this initialization.
• For the example flip-flop shown
• 0 applied to R resets the flip-flop to the 0 state
• 0 applied to S sets the flip-flop to the 1 state
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D Flip Flop with Direct Inputs
Question: What type of D-FF? Why?
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Flip Flops Sheet
(Mano’s Textbook)
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Summary
• In a sequential circuit, outputs depends on inputs
and previous inputs
• Previous inputs are stored as binary information into
memory
• The stored information at any time defines a state
• Similarly, next state depends on inputs and present state
• Two types of sequential circuits: Synchronous and
Asynchronous
• Two types of Memory elements: Latches and FlipFlops.
• A flip-flop is described using functional, characteristic
table/equation and excitation tables
Ahmad Almulhem, KFUPM 2009