COE 202: Digital Logic Design
Combinational Logic
Part 4
Dr. Ahmad Almulhem
Email: ahmadsm AT kfupm
Phone: 860-7554
Office: 22-324
Ahmad Almulhem, KFUPM 2009
Objectives
• Other Gate Types
• NAND
• NOR
• More Gates Types
• XOR
• XNOR
• Physical Properties of Gates
Ahmad Almulhem, KFUPM 2009
More Gates: NAND - NOR
NAND
NOR
X
Y
X
Y
Z
Z
F = (XY)’
F = (X+Y)’
X
Y
Z=(XY)’
0
0
1
0
1
1
1
0
1
1
1
0
X
Y
Z=(X+Y)’
0
0
1
0
1
0
1
0
0
1
1
0
Sometimes it is desirable to build circuits
using NAND gates only or NOR gates only
Ahmad Almulhem, KFUPM 2009
NAND Gate is Universal
NOT
AND
OR
X
X
Y
X
Y
X’
XY
X+Y
BUT
X’
X
X
BUT
Y
X
BUT
XY
X+Y
Y
Therefore, we can build all functions we learned so far using
NAND gates ONLY
NAND is a UNIVERSAL gate
Ahmad Almulhem, KFUPM 2009
Graphic Symbols for NAND Gate
Two equivalent
graphic symbols
or shapes for
the SAME
function
AND-NOT
NOT-OR
X
Y
Z
X
Y
Z
Ahmad Almulhem, KFUPM 2009
(XYZ)’
X’+Y’+Z’ = (XYZ)’
Implementation using NANDs
Example: Consider F = AB + CD
A
B
F
C
D
NAND
A
B
F
C
D
NAND
Proof:
F = ((AB)’.(CD)’)’
= ((AB)’)’ + ((CD)’)’
= AB + CD
A
B
C
D
Ahmad Almulhem, KFUPM 2009
F
Implementation using NANDs
Consider F =Σm(1,2,3,4,5,7) – Implement using
NAND gates
X
X
YZ
00
0
X=1
1
Y’
Y=1
1
01
11
10
X’
Y
1
1
1
Z
1
1
Z=1
F(X,Y) = Z+XY’+X’Y
X
Y’
X’
Y
Z’
Ahmad Almulhem, KFUPM 2009
F
F
Rules for 2-Level NAND
Implementations
1. Simplify the function and express it in sum-ofproducts form
2. Draw a NAND gate for each product term (with 2
literals or more)
3. Draw a single NAND gate at the 2nd level (in place of
the OR gate)
4. A term with single literal requires a NOT
What about multi-level circuits?
Ahmad Almulhem, KFUPM 2009
NOR Gate is Universal
NOT
AND
OR
X
X
Y
X
Y
X’
BUT
X’
X
X
XY
X+Y
BUT
Y
X
BUT
(X’+Y’)’ = XY
(X+Y)’’ = X+Y
Y
Therefore, we can build all functions we learned so far
using NOR gates ONLY
NOR is a UNIVERSAL gate
Ahmad Almulhem, KFUPM 2009
Graphic Symbols for NOR Gate
Two equivalent
graphic symbols
or shapes for the
SAME function
OR-NOT
NOT-AND
X
Y
Z
X
Y
Z
Ahmad Almulhem, KFUPM 2009
(X+Y+Z)’
(X’Y’Z’)=(X+Y+Z)’
Implementation using NOR
gates
Consider F = (A+B)(C+D)E
NOR
NOR
A
B
F
A
B
C
D
C
D
E
E’
Ahmad Almulhem, KFUPM 2009
F
Implementation using NOR
gates
Consider F =Σm(1,2,3,5,7) – Implement using NOR
gates
X
X=1
YZ
X’
Z
Y=1
00
01
11
10
0
1
1
1
1
1
1
Z=1
F’(X,Y) = Y’Z’+XZ’, or
F(X,Y) = (Y+Z)(X’+Z)
F
Y
Z
X’
Z
Y
Z
Ahmad Almulhem, KFUPM 2009
F
Rules for 2-Level NOR
Implementations
1. Simplify the function and express it in product of
sums form
2. Draw a NOR gate (using OR-NOT symbol) for each
sum term (with 2 literals or more)
3. Draw a single NOR gate (using NOT-AND symbol)
the 2nd level (in place of the AND gate)
4. A term with single literal requires a NOT
What about multi-level circuits?
Ahmad Almulhem, KFUPM 2009
More Gates: XOR - XNOR
Exclusive OR
(XOR)
Exclusive NOR
(XNOR)
X
Z
Y
X
Y
Z
F = X’Y + XY’
= XY
F = XY + X’Y’
= (XY)’
Ahmad Almulhem, KFUPM 2009
X
Y
Z=XY
0
0
0
0
1
1
1
0
1
1
1
0
X
Y
Z=(XY)’
0
0
1
0
1
0
1
0
0
1
1
1
Identities
• X 0=X
• X  1 = X’
• X X=0
• X  X’ = 1
• X  Y’ = X’  Y = (X  Y)’
• X  Y = X’  Y’
• X  Y = Y  X (commutative, same with XNOR)
• X  (Y  Z) = (X  Y)  Z (associative, same with XNOR)
Ahmad Almulhem, KFUPM 2009
Odd functions
The XOR of an n-input function: F = XY Z is equal
to 1 if and only if an odd number of variables of the
function have a value of 1
The Exclusive OR of a function
acts as an ODD detector. It is 1
only if the number of 1’s in the
input is odd.
X
Y
Z
X Y Z
F
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
Ahmad Almulhem, KFUPM 2009
Even function
Is equal to 1 if and only if the total number of 1’s in the
input is an even number
Obtained by placing an inverter in front of the odd
function
X
X Y Z
F
Y
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
0
Z
Parity Check?
Ahmad Almulhem, KFUPM 2009
Physical Properties of Gates
• Building blocks of digital circuits
• Built using integrated circuits
• Integrated circuits themselves are built using various
technologies. E.g. TTL, CMOS
• Physical characteristics of an Integrated Circuit depend
on the underlying technology
• Key characteristics of ICs are:
•
•
•
•
•
Physical voltage ranges for 1 and 0
Gate propagation delay/speed
Fan-in and Fan-out
Buffers
Tri-state Drivers
Ahmad Almulhem, KFUPM 2009
Voltage Levels
• Logic values of 0 & 1 are represented in electrical
terms using a voltage level
• A range of voltage defines logic 0 and logic 1.
• Any value outside this range is invalid.
+5V
Illegal
Voltage
Range
+0V
Ahmad Almulhem, KFUPM 2009
Input & Output Voltages
• VIL is defined as the maximum input voltage that is
considered as logic 0
• VOL is the maximum output voltage that is considered
as logic 0
• VOL is less than VIL to protect against noise
disturbance in the environment, which can lead to
errors
Due to noise, VOL from the AND gate will increase before it
reaches as input VIL to the NOT gate. Therefore, a larger
range of voltage must be acceptable as input => VIL > VOL
Ahmad Almulhem, KFUPM 2009
Input & Output Voltages
• VIH is defined as the minimum input voltage that is
considered as logic 1
• VOH is the minimum output voltage that is considered
as logic 1
• VIH is less than VOH to protect against noise
disturbance in the environment, which can lead to
errors
• If VOH is equal to VIH, then due to the noise in the
environment, the voltage may drop into the invalid
voltage range
Ahmad Almulhem, KFUPM 2009
Noise Margin
Noise margin for Logic 1
VOH
VIH
VIL
VOL
Noise margin for Logic 0
Definition: Maximum voltage that can be added to the input of a signal without
generating an invalid voltage value
Ahmad Almulhem, KFUPM 2009
Propagation Delay
• The delay between when the voltage signal arrives
at the input of a circuit, and when the output of the
circuit changes, is called the propagation delay
• A circuit is considered to be fast, if its propagation
delay is less (ideally as close to 0 as possible)
X
Z
Y
Delay between input (X, Y) and change in
output Z
Ahmad Almulhem, KFUPM 2009
Timing Diagram
• The inputs to a circuit can be changed over time.
• The timing diagram shows the values of the input signals to
a circuit with the passage of time, in the form of a waveform
• It also shows a waveform for the output
Inputs
Propagation
Delay of the
Circuit = τ
X
Y
Output
Z
Timing Diagram for an AND gate
Ahmad Almulhem, KFUPM 2009
Time
Fanin
• Fanin of a gate is the number of inputs to the gate
• For a 3-input OR gate, the fanin = 3
• There is a limitation on the fanin for any gate
• In CMOS IC technology, higher fanin implies slower
gates (higher propagation delays)
• TTL IC gates can have higher fanin
Ahmad Almulhem, KFUPM 2009
Fanout
• Fanout is the number of gates that can be driven by
a driver gate
• The driven gate is called the load gate
• There is a limit to the number of load gates that can
be driven by a driver gate
Fanout = 3
Ahmad Almulhem, KFUPM 2009
Buffers
• Buffers have a single input and a single output,
where output = input
• Buffers help increase the drive capability of a circuit
by increasing the fanout
Ahmad Almulhem, KFUPM 2009
Gates with Tristate outputs
• These gates have an additional input signal called
the Enable
• This signal (Enable) if high, implies that inputs are
accepted by the gate, and outputs are generated
• If Enable = 0, the gate is in a high impedance state,
and the output is disabled
Enable
E X
Z
1 0
0
1 1
1
0 0
High Z
0 1
High Z
Ahmad Almulhem, KFUPM 2009
Conclusion
• The universal gates NAND and NOR can
implement any Boolean expression
• NAND gates (2-level SOP)
• NOR gates (2-level POS)
• XOR and OR gates
• Physical Properties of Gates
Ahmad Almulhem, KFUPM 2009