Chapter Six
Sun SPARC Architecture
SPARC Registers
• A SPARC processor includes two types of
registers:
– general-purpose or “working” data registers and
– control/status registers.
• IU’s general-purpose registers are called r registers
• FPU’s general-purpose registers are called f registers.
• Coprocessor working registers are coprocessorimplementation dependent.
SPARC Registers
• IU control/status registers include:
– Processor State Register (PSR)
– Window Invalid Mask (WIM)
– Trap Base Register (TBR)
– Multiply/Divide Register (Y)
– Program Counters (PC, nPC)
– Implementation-dependent Ancillary State
Registers (ASRs)
– Implementation-dependent IU Deferred-Trap
Queue
SPARC Registers
• FPU control/status registers include:
– Floating-Point State Register (FSR)
– Implementation-dependent Floating-Point
Deferred-Trap Queue (FQ)
• Coprocessor (CP) control/status registers, if
present, may include:
– Implementation-dependent Coprocessor State
Register (CSR)
– Implementation-dependent Coprocessor
Deferred-Trap Queue (CQ)
IU r Registers
• An implementation of the IU may contain
from 40 through 520 general-purpose32-bit r
registers.
• They are partitioned into 8 global registers,
plus an implementation-dependent number of
16-register sets.
• A register set is further partitioned into 8 in
registers and 8 local registers.
Overlapping of Windows
• Thus any procedure can access only 32
registers (r0 – r31)
– r0r7 : global registers that are accessible to all
procedures
– r8 r15 : (outs) contains parameters to be passed
to the called procedure.
– r16 r23 : (locals) contains local parameters of
the procedure
– r24 r31 : (ins) contain parameters passed by the
procedure calling the current procedure
Window Addressing
Overlapping of Windows
• Thus ‘outs’ of one window are ‘ins’ of the
other window and this results in overlapping
of windows as shown:
Overlapping of Windows
Overlapping of Windows
• The register window of the currently running
procedure, called active window is pointed by
the current window pointer (CWP), a 5-bit
counter field in the Processor State Register
(PSR).
Overlapping of Windows
• The number of windows varies from 2 to 32.
• Most SPARC architectures have 8 windows.
• The last window overlaps with the first
window, called as circular register windowing.
• An example of 8-window implementation is as
shown :
Overlapping of Windows
Overlapping of Windows
• CWP is incremented by a RESTORE (or RETT)
instruction and decremented by a SAVE
instruction or a trap.
• If the procedure using the window w0
executes a RESTORE(return), w1 will become
the current window.
• If the procedure using the window w0
executes a SAVE(call), a window_overflow trap
occurs.
IU Control/Status Registers
SPARC Registers
• IU control/status registers include:
– Processor State Register (PSR)
– Window Invalid Mask (WIM)
– Trap Base Register (TBR)
– Multiply/Divide Register (Y)
– Program Counters (PC, nPC)
– Implementation-dependent Ancillary State
Registers (ASRs)
– Implementation-dependent IU Deferred-Trap
Queue
Processor State Register(PSR)
• 32-bit PSR contains various fields that control
the processor and hold status information.
• It can be modified by the SAVE, RESTORE,
Ticc, and RETT instructions, and by all
instructions that modify the condition codes.
• The privileged RDPSR and WRPSR instructions
read and write the PSR directly.
Processor State Register(PSR)
• impl: define a unique implementation or class
of implementations of the architecture.
• ver: to identify one or more particular
implementations or is a readable and writable
state field whose properties are
implementation-dependent.
Processor State Register(PSR)
• icc: Integer Condition Codes
– n: 1 = ALU result is negative, 0 = not negative
– z: 1 = zero, 0 = nonzero.
– v: 1 = overflow, 0 = no overflow.
– c: 1 =carry, 0 = no carry.
Processor State Register(PSR)
• reserved:
• Enable Coprocessor(EC): determines whether
the implementation-dependent coprocessor is
enabled.
• Enable Floating Point(EF): determines
whether the FPU is enabled
• Processor Interrupt Level (PIL): identify the
interrupt level above which the processor will
accept an interrupt.
Processor State Register(PSR)
• Supervisor(S): determines whether the
processor is in supervisor or user mode.
1 = supervisor mode, 0 = user mode.
• Previous Supervisor(PS): contains the value of
the S bit at the time of the most recent trap.
• Enable Trap(ET): determines whether the FPU
is enabled
Processor State Register(PSR)
• Current Window Pointer (CWP): a counter
that identifies the current window
SPARC Registers
• IU control/status registers include:
– Processor State Register (PSR)
– Window Invalid Mask (WIM)
– Trap Base Register (TBR)
– Multiply/Divide Register (Y)
– Program Counters (PC, nPC)
– Implementation-dependent Ancillary State
Registers (ASRs)
– Implementation-dependent IU Deferred-Trap
Queue
Window Invalid Mask (WIM)
• Window Invalid Mask register (WIM) is
controlled by supervisor software and is used
by hardware to determine whether a window
overflow or underflow trap is to be generated
• The structure of the WIM register is designed
for 32-windows.
SPARC Registers
• IU control/status registers include:
– Processor State Register (PSR)
– Window Invalid Mask (WIM)
– Trap Base Register (TBR)
– Multiply/Divide Register (Y)
– Program Counters (PC, nPC)
– Implementation-dependent Ancillary State
Registers (ASRs)
– Implementation-dependent IU Deferred-Trap
Queue
Trap Base Register (TBR)
• This register determine the address to which
control is transferred in case of trap.
• TBA(Trap Base Address): It contains the mostsignificant 20 bits of the trap table address
• tt(trap type): This 8-bit field is written by the
hardware when a trap occurs and provides an offset
into the trap table
• zero: zeros
SPARC Registers
• IU control/status registers include:
– Processor State Register (PSR)
– Window Invalid Mask (WIM)
– Trap Base Register (TBR)
– Multiply/Divide Register (Y)
– Program Counters (PC, nPC)
– Implementation-dependent Ancillary State
Registers (ASRs)
– Implementation-dependent IU Deferred-Trap
Queue
Multiply/Divide Register (Y)
• It contains the most significant word of the
double precision product of integer
multiplication.
• It also hold the most significant word of the
double precision dividend of the integer divide
SPARC Registers
• IU control/status registers include:
– Processor State Register (PSR)
– Window Invalid Mask (WIM)
– Trap Base Register (TBR)
– Multiply/Divide Register (Y)
– Program Counters (PC, nPC)
– Implementation-dependent Ancillary State
Registers (ASRs)
– Implementation-dependent IU Deferred-Trap
Queue
Program Counters (PC, nPC)
• PC(Program Counter): contains the address of
the instruction currently being executed by IU
• nPC (Next Program Counter): holds the
address of the next instruction to be executed
SPARC Registers
• IU control/status registers include:
– Processor State Register (PSR)
– Window Invalid Mask (WIM)
– Trap Base Register (TBR)
– Multiply/Divide Register (Y)
– Program Counters (PC, nPC)
– Implementation-dependent Ancillary State
Registers (ASRs)
– Implementation-dependent IU Deferred-Trap
Queue
Ancillary State Registers (ASRs)
• ASR’s numbered 1-15 are reserved
• ASR’s numbered 16-31 are available for
implementation-dependent uses such as
timers, counters, diagnostic registers, self-test
registers and trap-control registers.
SPARC Registers
• IU control/status registers include:
– Processor State Register (PSR)
– Window Invalid Mask (WIM)
– Trap Base Register (TBR)
– Multiply/Divide Register (Y)
– Program Counters (PC, nPC)
– Implementation-dependent Ancillary State
Registers (ASRs)
– Implementation-dependent IU Deferred-Trap
Queue
IU Deferred-Trap Queue
• It contains sufficient state to implement
resumable deferred traps caused by the IU
FPU’s f registers.
• FPU contains 32 32-bit floating-point f
registers numbered from f[0] to f[31].
• At a given time an instruction has access to
any of the 32 f registers.
FPU’s f registers.
• A single f register can hold one singleprecision operand.
• A double-precision operand requires an
aligned pair of f registers.
• A quad-precision operand requires an aligned
quadruple of f registers.
FPU Control/Status Registers
Floating-Point State Register (FSR)
• RD (Rounding Direction): select the rounding
direction for floating-point results
Floating-Point State Register (FSR)
• u (Unused): reserved
• TEM(Trap Enable Masks) : enable bits for five
floating-point exceptions
– NVM(Non Valid Mask): An operand is improper for
the operation to be performed. For e.g.0÷0, ∞-∞
are invalid. (1 = invalid operand, 0 = valid operand.)
– OFM(Overflow Trap Mask):1 = overflow, 0 = no
overflow.
Floating-Point State Register (FSR)
• TEM :
– UFM(Overflow Trap Mask):1 = underflow, 0 = no
underflow.(magnitude is smaller)
– DZM(Division by Zero Trap): X÷0.Note that 0÷0 is
not considered here. 1 = division-by-zero, 0 = no
division-by-zero.
– NXM(Not Exact Trap Mask) The rounded result
differs from the infinitely precise correct result.
1 = inexact result, 0 = exact result.
Floating-Point State Register (FSR)
• NS(Not Standard): When set to 1, causes FPU
to produce results that may not correspond to
ANSI/IEEE Standard 754-1985.
• res: reserved bits
• ver: indicates version
Floating-Point State Register (FSR)
• ftt(floating point trap
type):identify floatingpoint exception trap
types
Floating-Point State Register (FSR)
• qne(queue not empty): indicates whether the
optional floating-point deferred-trap queue
(FQ) is empty. If qne = 0, the queue is empty;
if qne = 1, the queue is not empty.
• u: unused
• fcc:
Floating-Point State Register (FSR)
• fcc:
– contain the FPU condition codes.
– are updated by floating-point compare instructions
– f rs1 and f rs2 correspond to values in the f registers
specified by an instruction’s rs1 and rs2 fields.
Floating-Point State Register (FSR)
• aexc:
– Accumulate floating-point exceptions while
fp_exception traps are disabled using the TEM
field.
Floating-Point State Register (FSR)
• cexc:
– indicate that one or more IEEE_754 floating-point
exceptions were generated by the most recently
executed FPop instruction.
– The absence of an exception causes corresponding
bit to be cleared.
Floating-Point Deferred-Trap
Queue (FQ)
• FQ, if present in an implementation, contains
sufficient state information to implement
resumable, deferred floating point traps.
CP Registers
• All of the coprocessor data and control/status
registers are optional and implementationdependent.
• Coprocessor registers are accessed via
load/store coprocessor and CPop1/CPop2
format instructions.
• The architecture also provides instruction
support for reading and writing a Coprocessor
State Register (CSR) and a coprocessor deferredtrap queue (CQ).
SPARC Instruction Format
• Instructions are encoded in three major 32-bit
formats.
• They are
– CALL
– Branch Instructions
– Operate instructions(register-to-register)
SPARC Instruction Format
SPARC Instruction Format
• The instruction fields are interpreted as
follows:
• op and op2:These 2- and 3-bit fields encode
the 3 major formats and the format 2
instructions according to
SPARC Instruction Format
• rd : Selects the source address for store
instructions and destination register for all
other instructions.
SPARC Instruction Format
• a (annul bit) : It changes the behavior of the
instruction encountered immediately after a
control transfer.
• cond :It selects the condition code for
conditional branches.
• imm22 : Holds the 22-bit constant used by
SETHI instruction.
SPARC Instruction Format
• disp22 : A 22-bit sign-extended word
displacement for a branch instruction
• disp30 : A 30-bit sign-extended word
displacement for PC-relative call instruction
• Op3:Opcode Extension
• i bit: selects the second ALU operand for nonfloating point operation instructions.
– If i = 0, the operand is in a register rs2
– If i = 1, the operand is simm13
• asi
SPARC Instruction Format
• asi : This 8-bit field is the address space
identifier supplied by a load/store alternate
instruction.
• rs1 : Selects the first source operand register
• rs2 : Selects second source operand register
• Simm13 : This is a sign-extended 13-bit
immediate
• opf : It identifies a floating-point operation
instruction
Addressing Modes
• There are only 3 addressing modes for
memory access:
1. Register indirect with displacement: register
+ signed 13-bit constant
2. Register indirect indexed: register1+register2
3. PC Relative: used in call with 30-bit
displacement
SPARC Memory model
Overlapping of Windows
SPARC Memory model
• ,. Study of SuperSPARC and UltraSPARC
architectures