Chip Level
Multithreading
(CMT)
By:Tanveer Ahmed
Agenda
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Introduction to CMT Programming Model.
Background Terminology.
General CMT behavior.
Classes of CMT registers.
CMT Registers.
Parking Virtual registers.
Performance Issues for CMT Processors.
Introduction
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All UltraSPARC IV+ processors use CMT
Programming Model.
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Specifies the basic functionality for controlling
multi-core processor.
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Defines how logical processors are identified.
Background Terminology
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Thread.
Strand.
Pipeline
Physical Core.
Processor.
Virtual Processor.
General CMT behavior
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Virtual Processors are Independent in
functionality.
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OS treats a virtual processor as independent
processor
Classes of CMT registers.
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Two main classes:
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Private Registers: A Private copy of the register is
associated with each logical processor.
Shared Registers: A single copy of the register is
shared by all the logical processors.
Both can be accessed by privileged
software's.
One processor cannot access others private
registers.
CMT Registers
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Two Main Registers:
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Strand ID Register (STRAND_ID):
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Strand Interrupt ID Register (STRAND_INTR_ID)
Disabling and Parking Virtual
Registers.
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CMT provides the ability to disable virtual
processors and park them.
Key Register used:
Strand Available Register:-
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Strand Enable Status Register:-
Disabling and Parking Virtual
Registers Cont…
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Strand Enable Register:-
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Strand Running Register:-
Addition Info
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Boot Sequence.
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Resets and Trap Handling.
Performance Issues.
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Shared Resources.
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Needs complicated algorithms to make use of
functionality.
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Need knowledge of underlying architecture
for programming.
QUESTIONS