ENE 311 Lecture 7 p-n Junction • A p-n junction plays a major role in electronic devices. • It is used in rectification, switching, and etc. • It is the simplest semiconductor devices. • Also, it is a key building block for other electronic, microwave, or photonic devices. Basic fabrication steps The basic fabrication steps for p-n junction include • oxidation, • lithography, • diffusion or ion implanation, • and metallization. Basic fabrication steps Oxidation • This process is to make a high-quality silicon dioxide (SiO2) as an insulator in various devices or a barrier to diffusion or implanation during fabrication process. • There are two methods to grow SiO2: dry and wet oxidation, using dry oxygen and water vapor, respectively. • Generally, dry oxidation is used to form thin oxides because of its good Si-SiO2 interface characteristics, while wet oxidation is used for forming thicker layers since its higher growth rate. Basic fabrication steps Lithography • This process is called photolithography used to delineate the pattern of the p-n junction. Basic fabrication steps • (a) The wafer after the development. • (b) The wafer after SiO2 removal. • (c) The final result after a complete lithography process. Basic fabrication steps Diffusion & Ion Implantation • This is used to put the impurity into the semiconductor. • For diffusion method, the semiconductor surface not protected by the oxide is exposed to a high concentration of impurity. The impurity moves into the crystal by solid-state diffusion. • For the ion-implantation method, the impurity is introduced into the semiconductor by accelerating the impurity ions to a high-energy level and then implanting the ions in the semiconductor. Basic fabrication steps Metallization • This process is used to form ohmic contacts and interconnections. • After this process is done, the p-n junction is ready to use. Thermal equilibrium condition • The most important characteristic of p-n junction is rectification. • The forward biased voltage is normally less than 1 V and the current increases rapidly as the biased voltage increases. • As the reverse bias increases, the current is still small until a breakdown voltage is reached, where the current suddenly increases. Thermal equilibrium condition • Assume that both pand n-type semiconductors are uniformly doped. • The Fermi level EF is near the valence band edge in the ptype material and near the conduction band edge in the ntype material. Thermal equilibrium condition • Electrons diffuse from n-side toward p-side and holes diffuse from p-side toward n-side. • As electrons leave the n-side, they leave behind the positive donor ions (ND+) near the junction. • In the same way, some of negative acceptor ions (NA-) are left near the junction as holes move to the n-side. Thermal equilibrium condition Space-charge region neutral neutral • This forms 2 regions called “neutral” regions and “spacecharge” region. • The space-charge region is also called “depletion region” due to the depletion of free carriers. Thermal equilibrium condition • Carrier diffusion induces an internal electric field in the opposite direction to free charge diffusion. • Therefore, the electron diffusion current flows from left to right, whereas the electron drift current flows from right to left. Thermal equilibrium condition • At thermal equilibrium, the individual electron and hole current flowing across the junction are identically zero. • In the other words, the drift current cancels out precisely the diffusion current. Therefore, the equilibrium is reached as EFn = EFp. Thermal equilibrium condition • The space-charge density distribution and the electrostatic potential are given by Poisson’s equation as d 2 dE e ND N A p n 2 dx dx (1) • Assume that all donor and acceptor atoms are ionized. Thermal equilibrium condition • Assume NA = 0 and n >> p for n-type neutral region and ND = 0 and p >> n for p-type neutral region. Thermal equilibrium condition • The electrostatic potential in of the n- and ptype with respect to the Fermi level can be found with the help of n ni exp EF Ei / kT and p ni exp Ei EF / kT as kT N D n EF Ei ln e ni (2) kT N A p Ei EF ln e ni (3) Thermal equilibrium condition • The total electrostatic potential difference between the p-side and the n-side neutral region is called the “built-in potential” Vbi. It is written as kT N A N D Vbi n p ln e ni2 (5) • a) A p-n junction with abrupt doping changes at the metallurgical junction. • (b) Energy band diagram of an abrupt junction at thermal equilibrium. • (c) Space charge distribution. • (d) Rectangular approximation of the space charge distribution. Thermal equilibrium condition Ex. Calculate the built-in potential for a silicon p-n junction with NA = 1018cm-3 and ND = 1015 cm-3 at 300 K. Thermal equilibrium condition Ex. Calculate the built-in potential for a silicon p-n junction with NA = 1018cm-3 and ND = 1015 cm-3 at 300 K. Soln N AND Vbi kT ln 2 ni 18 15 10 10 0.0259ln 9.65 109 2 Vbi 0.774 eV Depletion Region The p-n junction may be classified into two classes depending on its impurity distribution: • the abrupt junction and • the linearly graded junction. Depletion Region • An abrupt junction can be seen in a p-n junction that is formed by shallow diffusion or low-energy ion implantation. • The impurity distribution in this case can be approximated by an abrupt transition of doping concentration between the n- and the p-type regions. Depletion Region • In the linearly graded junction, the p-n junction may be formed by deep diffusions or high-energy ion implantations. • The impurity distribution varies linearly across the junction. Abrupt junction • Consider an abrupt junction as in the figure above, equation (1) can be written as d 2 eN A 2 dx d 2 eN D dx 2 for -x p x 0 for 0 x xn • The charge conservation is expressed by the condition Q = 0 or N A x p N D xn Abrupt junction • To solve equation (5), we need to solve it separately for p- and n-type cases. p-side: Integrate eq.(4) once, we have d dx eN A x c We know that E d dx eN A x E p ( x) c Abrupt junction Apply boundary condition: E p ( x x p ) 0 eN A ( x p ) Ep ( xp ) c 0 c eN A x p E p ( x) eN A ( x x p ) (7) Abrupt junction n-side: • Similarly, we can have En ( x) eN D ( x xn ) Em eN D x (8) Abrupt junction • Let consider at x = 0 E p (0) En (0) eN A x p eN D ( xn ) Em (9) We may relate this electric field E to the potential over the depletion region as Vbi xn 0 xp xp xn E ( x)dx E ( x)dx E ( x)dx p side 0 n side Abrupt junction 2 A p eN x 2 D n eN x Vbi 2 2 (10) • From (6), we have xn N Axp ND N D xn xp NA (11) Abrupt junction • Substitute (11) into (10), this yields 2Vbi ND xp e N A ND N A 2Vbi NA xn e N A ND ND (12) Abrupt junction • Hence, the space-charge layer width or depletion layer width can be written as 2Vbi W x p xn e N A ND N N A D (13) Abrupt junction Ex. Si p-n diode of NA = 5 x 1016 cm-3 and ND = 1015 cm-3. Calculate (a) built-in voltage (b) depletion layer width (c) Em Abrupt junction Soln (a) kT N A N D Vbi ln 2 e ni 16 15 5 10 10 0.0259ln 1.45 1010 2 Vbi 0.679 eV Abrupt junction Soln (b) From (13) 2Vbi W e N A ND N N A D 2 8.85 1014 11.8 0.679 5 1016 1015 19 16 15 1.6 10 5 10 10 W 0.95 m Abrupt junction Soln (c) Emax E ( x 0) eN A x p eN D ( xn ) 2Vbi N xn A e N A ND ND 2 8.85 1014 11.8 0.679 5 1016 19 16 15 1015 1.6 10 5 10 10 xn 9.299 105 cm. Emax Emax eN D ( xn ) 1.6 1019 1015 9.299 105 8.85 1014 11.8 1.431 104 V/cm Abrupt junction • If one side has much higher impurity doping concentration than another, i.e. NA >> ND or ND >> NA, then this is called “one-sided junction”. • Consider case of p+-n junction as in the figure (NA >> ND), W xn 2Vbi eN D Abrupt junction • Similarly, for n+-p junction of ND >> NA W xp 2Vbi eN A • The electric-field distribution could be written as E ( x) Em eN B x where NB = lightly doped bulk concentration (i.e., NB = ND for p+-n junction) Abrupt junction • The maximum electric field Em at x = 0 can be found as Em eN BW • Therefore, the electric-field distribution E(x) can be re-written as x E ( x) W x Em 1 W eN B (16) Abrupt junction • The potential distribution can be found from integrating (16) as Vbi x x ( x) 2 W W (17) Abrupt junction Ex. For a silicon one-sided abrupt junction with NA = 1019 cm-3 and ND = 1016 cm-3, calculate the depletion layer width and the maximum field at zero bias. Abrupt junction Soln 19 16 10 10 0.895 V Vbi 0.0259ln 2 9.65 109 2Vbi W 3.41 105 0.343 m eN D Em qN BW 0.52 104 V/cm Linearly Graded Junction Linearly Graded Junction • In this case, the Possion equation (1) is expressed by d 2 dE e W W ax for - x 2 dx dx 2 2 (18) where a is the impurity gradient in cm-4 and W is the depletion-layer width Linearly Graded Junction • By integrating (18) with the boundary conditions that the electric-field is zero at W/2, E(x) can be found as 2 ea W / 2 x E ( x) 2 2 (19) • The maximum field Em at x = 0 is eaW 2 Em 8 (20) Linearly Graded Junction • The built-in potential is given by eaW 3 Vbi 12 (21) and kT aW / 2 aW / 2 2kT aW Vbi ln ln 2 e ni e 2 n i (22) Linearly graded junction in thermal equilibrium. (a) Impurity distribution. (b) Electric-field distribution. (c) Potential distribution with distance. (d) Energy band diagram. Linearly Graded Junction Ex. For a silicon linearly graded junction with an impurity gradient of 1020 cm-4, the depletionlayer width is 0.5 μm. Calculate the maximum field and built-in voltage. Linearly Graded Junction Soln 1.6 10 10 0.5 10 eaW 3 Em 4.75 10 V/cm 14 8 8 11.9 8.85 10 1020 0.5 104 2kT aW Vbi 0.645 V 2 0.0259 9 e 2ni 2 9.65 10 2 19 20 4 2 Note: Practically, the Vbi is smaller than that calculated from (22) by about 0.05 to 0.1 V.